Lines Matching +full:0 +full:x0a
25 #define BER_SRC_S 0x20
26 #define BER_SRC_S2 0x20
130 u8 data[3] = {reg >> 8, reg & 0xff, val}; in write_reg()
131 struct i2c_msg msg = {.addr = state->base->adr, .flags = 0, in write_reg()
139 return 0; in write_reg()
145 u8 msg[2] = {reg >> 8, reg & 0xff}; in i2c_read_regs16()
146 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, in i2c_read_regs16()
156 return 0; in i2c_read_regs16()
192 mask = field & 0xff; in write_field()
193 shift = (field >> 12) & 0xf; in write_field()
196 return 0; in write_field()
213 { 0, 9242 }, /* C/N= 0dB */
276 { 0, 11520 }, /* C/N= 0dB */
333 { 0, 118000 }, /* PADC= +0dBm */
361 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B,
363 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B,
365 0x1C, 0x3C, 0x1B, 0x3C, 0x3A, 0x1C, 0x3A, 0x3B, 0x3A, 0x2B,
367 0x0C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
369 0x1C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
371 0x2C, 0x2C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
373 0x3C, 0x2C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
375 0x0D, 0x3C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
377 0x1D, 0x3C, 0x0C, 0x2C, 0x2B, 0x1C, 0x1B, 0x3B, 0x0B, 0x1B,
379 0x3D, 0x0D, 0x0C, 0x2C, 0x2B, 0x0C, 0x2B, 0x2B, 0x0B, 0x0B,
381 0x1E, 0x0D, 0x1C, 0x2C, 0x3B, 0x0C, 0x2B, 0x2B, 0x1B, 0x0B,
383 0x28, 0x09, 0x28, 0x09, 0x28, 0x09, 0x28, 0x08, 0x28, 0x27,
385 0x19, 0x29, 0x19, 0x29, 0x19, 0x29, 0x38, 0x19, 0x28, 0x09,
387 0x1A, 0x0B, 0x1A, 0x3A, 0x0A, 0x2A, 0x39, 0x2A, 0x39, 0x1A,
389 0x2B, 0x2B, 0x1B, 0x1B, 0x0B, 0x1B, 0x1A, 0x0B, 0x1A, 0x1A,
391 0x0C, 0x0C, 0x3B, 0x3B, 0x1B, 0x1B, 0x2A, 0x0B, 0x2A, 0x2A,
393 0x0C, 0x1C, 0x0C, 0x3B, 0x2B, 0x1B, 0x3A, 0x0B, 0x2A, 0x2A,
405 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x39, 0x0A, 0x29, 0x0A,
407 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0A, 0x2A, 0x0A, 0x1A, 0x0A,
409 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
411 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
413 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
415 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
417 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
419 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
421 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
423 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
425 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
431 int i = 0; in get_optim_cloop()
439 i += 0; in get_optim_cloop()
457 int status = 0; in get_cur_symbol_rate()
468 *p_symbol_rate = 0; in get_cur_symbol_rate()
485 if ((timing_offset & (1 << 23)) != 0) in get_cur_symbol_rate()
486 timing_offset |= 0xFF000000; /* Sign extent */ in get_cur_symbol_rate()
493 return 0; in get_cur_symbol_rate()
505 state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2); in get_signal_parameters()
506 state->pilots = (tmp & 0x01) != 0; in get_signal_parameters()
507 state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1); in get_signal_parameters()
512 switch (tmp & 0x1F) { in get_signal_parameters()
513 case 0x0d: in get_signal_parameters()
516 case 0x12: in get_signal_parameters()
519 case 0x15: in get_signal_parameters()
522 case 0x18: in get_signal_parameters()
525 case 0x1a: in get_signal_parameters()
529 state->is_vcm = 0; in get_signal_parameters()
533 return 0; in get_signal_parameters()
541 tmp &= ~0xC0; in tracking_optimization()
545 tmp |= 0x40; in tracking_optimization()
548 tmp |= 0x80; in tracking_optimization()
551 tmp |= 0xC0; in tracking_optimization()
559 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, in tracking_optimization()
560 0x03); in tracking_optimization()
571 state->regoff, 0x2a); in tracking_optimization()
576 state->regoff, 0x2a); in tracking_optimization()
581 state->regoff, 0x2a); in tracking_optimization()
587 return 0; in tracking_optimization()
594 int imin = 0; in table_lookup()
599 /* Assumes Table[0].RegValue > Table[imax].RegValue */ in table_lookup()
600 if (reg_value >= table[0].reg_value) { in table_lookup()
601 value = table[0].value; in table_lookup()
616 if (reg_diff != 0) in table_lookup()
634 *signal_to_noise = 0; in get_signal_to_noise()
656 return 0; in get_signal_to_noise()
671 if ((regs[0] & 0x80) == 0) { in get_bit_error_rate_s()
674 state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) | in get_bit_error_rate_s()
680 0x20 | state->berscale); in get_bit_error_rate_s()
685 state->regoff, 0x20 | in get_bit_error_rate_s()
691 return 0; in get_bit_error_rate_s()
697 { 0, 0}, /* DUMMY_PLF */ in dvbs2_nbch()
745 if ((regs[0] & 0x80) == 0) { in get_bit_error_rate_s2()
750 state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) | in get_bit_error_rate_s2()
755 0x20 | state->berscale); in get_bit_error_rate_s2()
760 0x20 | state->berscale); in get_bit_error_rate_s2()
771 *bernumerator = 0; in get_bit_error_rate()
784 return 0; in get_bit_error_rate()
847 return 0; in set_mclock()
856 state->tscfgh | 0x01); in stop()
858 tmp &= ~0x01; /* release reset DVBS2 packet delin */ in stop()
861 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B); in stop()
863 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c); in stop()
864 state->started = 0; in stop()
867 return 0; in stop()
877 pls_code & 0xff); in set_pls()
879 (pls_code >> 8) & 0xff); in set_pls()
881 0x04 | ((pls_code >> 16) & 0x03)); in set_pls()
889 if (isi == 0x80000000) { in set_isi()
895 isi & 0xff); in set_isi()
896 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff); in set_isi()
899 SET_FIELD(ALGOSWRST, 0); in set_isi()
912 SET_FIELD(FORCE_CONTINUOUS, 0); in init_search_param()
913 SET_FIELD(FRAME_MODE, 0); in init_search_param()
914 SET_FIELD(FILTER_EN, 0); in init_search_param()
915 SET_FIELD(TSOUT_NOSYNC, 0); in init_search_param()
916 SET_FIELD(TSFIFO_EMBINDVB, 0); in init_search_param()
917 SET_FIELD(TSDEL_SYNCBYTE, 0); in init_search_param()
918 SET_REG(UPLCCST0, 0xe0); in init_search_param()
919 SET_FIELD(TSINS_TOKEN, 0); in init_search_param()
920 SET_FIELD(HYSTERESIS_THRESHOLD, 0); in init_search_param()
924 return 0; in init_search_param()
933 val = 0x01; in enable_puncture_rate()
936 val = 0x02; in enable_puncture_rate()
939 val = 0x04; in enable_puncture_rate()
942 val = 0x08; in enable_puncture_rate()
945 val = 0x20; in enable_puncture_rate()
949 val = 0x2f; in enable_puncture_rate()
958 state->vth[0] = 0xd7; in set_vth_default()
959 state->vth[1] = 0x85; in set_vth_default()
960 state->vth[2] = 0x58; in set_vth_default()
961 state->vth[3] = 0x3a; in set_vth_default()
962 state->vth[4] = 0x34; in set_vth_default()
963 state->vth[5] = 0x28; in set_vth_default()
964 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth_default()
970 return 0; in set_vth_default()
988 u16 reg_value = (tmp[0] << 8) | tmp[1]; in set_vth()
992 for (i = 0; i < 6; i += 1) in set_vth()
996 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth()
1015 state->demod_lock_time = 0; in start()
1019 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C); in start()
1046 ((symb >> 8) & 0x7F)); in start()
1047 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF)); in start()
1049 state->demod_bits |= 0x80; in start()
1055 reg_dmdcfgmd |= 0xC0); in start()
1058 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00); in start()
1061 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00); in start()
1062 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F); in start()
1067 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B); in start()
1068 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A); in start()
1069 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84); in start()
1070 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84); in start()
1071 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C); in start()
1072 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79); in start()
1074 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29); in start()
1075 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09); in start()
1076 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84); in start()
1077 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84); in start()
1083 write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08); in start()
1084 write_reg(state, RSTV0910_TSTRES0, 0); in start()
1088 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1090 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46); in start()
1099 (freq >> 8) & 0xff); in start()
1100 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff)); in start()
1104 (freq >> 8) & 0xff); in start()
1105 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff)); in start()
1107 /* init the demod frequency offset to 0 */ in start()
1108 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0); in start()
1109 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0); in start()
1111 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1113 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15); in start()
1118 return 0; in start()
1123 u16 offs = state->nr ? 0x40 : 0; /* Address offset */ in init_diseqc()
1127 write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00); in init_diseqc()
1128 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */ in init_diseqc()
1129 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */ in init_diseqc()
1131 return 0; in init_diseqc()
1139 state->started = 0; in probe()
1141 if (read_reg(state, RSTV0910_MID, &id) < 0) in probe()
1144 if (id != 0x51) in probe()
1148 write_reg(state, RSTV0910_P1_I2CRPT, 0x24); in probe()
1150 write_reg(state, RSTV0910_P2_I2CRPT, 0x24); in probe()
1152 write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */ in probe()
1154 write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */ in probe()
1155 write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */ in probe()
1156 write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */ in probe()
1158 write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */ in probe()
1161 write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */ in probe()
1163 write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */ in probe()
1165 write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */ in probe()
1166 write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */ in probe()
1168 write_reg(state, RSTV0910_P1_CAR3CFG, 0x02); in probe()
1169 write_reg(state, RSTV0910_P2_CAR3CFG, 0x02); in probe()
1170 write_reg(state, RSTV0910_P1_DMDCFG4, 0x04); in probe()
1171 write_reg(state, RSTV0910_P2_DMDCFG4, 0x04); in probe()
1173 write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */ in probe()
1174 write_reg(state, RSTV0910_TSTRES0, 0x00); in probe()
1176 write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00); in probe()
1177 write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00); in probe()
1179 write_reg(state, RSTV0910_P1_TMGCFG2, 0x80); in probe()
1180 write_reg(state, RSTV0910_P2_TMGCFG2, 0x80); in probe()
1185 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01); in probe()
1187 write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */ in probe()
1188 write_reg(state, RSTV0910_P1_TSCFGL, 0x20); in probe()
1192 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01); in probe()
1194 write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */ in probe()
1195 write_reg(state, RSTV0910_P2_TSCFGL, 0x20); in probe()
1200 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01); in probe()
1201 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01); in probe()
1208 write_reg(state, RSTV0910_P1_TSINSDELM, 0x17); in probe()
1209 write_reg(state, RSTV0910_P1_TSINSDELL, 0xff); in probe()
1211 write_reg(state, RSTV0910_P2_TSINSDELM, 0x17); in probe()
1212 write_reg(state, RSTV0910_P2_TSINSDELL, 0xff); in probe()
1215 return 0; in probe()
1221 u8 i2crpt = state->i2crpt & ~0x86; in gate_ctrl()
1230 * enable=0 (close I2C gate) releases the lock in gate_ctrl()
1235 i2crpt |= 0x80; in gate_ctrl()
1237 i2crpt |= 0x02; in gate_ctrl()
1241 RSTV0910_P1_I2CRPT, i2crpt) < 0) { in gate_ctrl()
1256 return 0; in gate_ctrl()
1264 if (state->base->count == 0) { in release()
1273 int stat = 0; in set_parameters()
1295 (enum fe_stv0910_roll_off)(bbheader[0] & 0x03); in manage_matype_info()
1296 state->is_vcm = (bbheader[0] & 0x10) == 0; in manage_matype_info()
1297 state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0; in manage_matype_info()
1299 state->is_vcm = 0; in manage_matype_info()
1303 return 0; in manage_matype_info()
1313 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; in read_snr()
1314 p->cnr.stat[0].svalue = 100 * snrval; /* fix scale */ in read_snr()
1316 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_snr()
1319 return 0; in read_snr()
1330 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
1331 p->pre_bit_error.stat[0].uvalue = n; in read_ber()
1332 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
1333 p->pre_bit_count.stat[0].uvalue = d; in read_ber()
1335 return 0; in read_ber()
1344 s32 padc, power = 0; in read_signal_strength()
1349 agc = (((u32)reg[0]) << 8) | reg[1]; in read_signal_strength()
1351 for (i = 0; i < 5; i += 1) { in read_signal_strength()
1353 power += (u32)reg[0] * (u32)reg[0] in read_signal_strength()
1361 p->strength.stat[0].scale = FE_SCALE_DECIBEL; in read_signal_strength()
1362 p->strength.stat[0].svalue = (padc - agc); in read_signal_strength()
1369 u8 dmd_state = 0; in read_status()
1370 u8 dstatus = 0; in read_status()
1372 u32 feclock = 0; in read_status()
1374 *status = 0; in read_status()
1378 if (dmd_state & 0x40) { in read_status()
1380 if (dstatus & 0x08) in read_status()
1381 cur_receive_mode = (dmd_state & 0x20) ? in read_status()
1388 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1389 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1390 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1391 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1393 return 0; in read_status()
1413 state->tscfgh | 0x01); in read_status()
1417 if (dmd_state & 0x40) { in read_status()
1424 feclock = (pdelstatus & 0x02) != 0; in read_status()
1431 feclock = (vstatus & 0x08) != 0; in read_status()
1441 state->first_time_lock = 0; in read_status()
1448 * FSTV0910_P2_MANUALS2_ROLLOFF = 0 in read_status()
1450 state->demod_bits &= ~0x84; in read_status()
1458 tmp |= 0x40; in read_status()
1463 tmp &= ~0x40; in read_status()
1469 state->last_bernumerator = 0; in read_status()
1477 state->last_bernumerator = 0; in read_status()
1486 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00); in read_status()
1492 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1); in read_status()
1507 mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2); in read_status()
1523 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1529 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1530 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1533 return 0; in read_status()
1545 const enum fe_modulation modcod2mod[0x20] = { in get_frontend()
1555 const enum fe_code_rate modcod2fec[0x20] = { in get_frontend()
1566 mc = ((tmp & 0x7c) >> 2); in get_frontend()
1567 p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF; in get_frontend()
1572 switch (tmp & 0x1F) { in get_frontend()
1573 case 0x0d: in get_frontend()
1576 case 0x12: in get_frontend()
1579 case 0x15: in get_frontend()
1582 case 0x18: in get_frontend()
1585 case 0x1a: in get_frontend()
1599 return 0; in get_frontend()
1621 return 0; in tune()
1624 return 0; in tune()
1635 u16 offs = state->nr ? 0x40 : 0; in set_tone()
1639 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38); in set_tone()
1641 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a); in set_tone()
1652 u16 offs = state->nr ? 0x40 : 0; in wait_dis()
1654 for (i = 0; i < 10; i++) { in wait_dis()
1657 return 0; in wait_dis()
1671 for (i = 0; i < cmd->msg_len; i++) { in send_master_cmd()
1672 wait_dis(state, 0x40, 0x00); in send_master_cmd()
1675 SET_FIELD(DIS_PRECHARGE, 0); in send_master_cmd()
1676 wait_dis(state, 0x20, 0x20); in send_master_cmd()
1677 return 0; in send_master_cmd()
1687 value = 0x00; in send_burst()
1690 value = 0xFF; in send_burst()
1694 wait_dis(state, 0x40, 0x00); in send_burst()
1696 SET_FIELD(DIS_PRECHARGE, 0); in send_burst()
1697 wait_dis(state, 0x20, 0x20); in send_burst()
1699 return 0; in send_burst()
1707 return 0; in sleep()
1753 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in stv0910_init_stats()
1755 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in stv0910_init_stats()
1757 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in stv0910_init_stats()
1759 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in stv0910_init_stats()
1773 state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40); in stv0910_attach()
1774 state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00; in stv0910_attach()
1775 state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4); in stv0910_attach()
1777 state->tsspeed = (cfg->tsspeed ? cfg->tsspeed : 0x28); in stv0910_attach()
1779 state->regoff = state->nr ? 0 : 0x200; in stv0910_attach()
1781 state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */ in stv0910_attach()
1783 state->cur_scrambling_code = (~0U); in stv0910_attach()
1784 state->single = cfg->single ? 1 : 0; in stv0910_attach()
1802 if (probe(state) < 0) { in stv0910_attach()