Lines Matching refs:mt312_writereg
129 static inline int mt312_writereg(struct mt312_state *state, in mt312_writereg() function
140 return mt312_writereg(state, RESET, full ? 0x80 : 0x40); in mt312_reset()
174 ret = mt312_writereg(state, MON_CTRL, 0x03); in mt312_get_symbol_rate()
187 ret = mt312_writereg(state, MON_CTRL, 0x05); in mt312_get_symbol_rate()
238 ret = mt312_writereg(state, CONFIG, in mt312_initfe()
265 ret = mt312_writereg(state, GPP_CTRL, 0x80); in mt312_initfe()
277 ret = mt312_writereg(state, HW_CTRL, 0x00); in mt312_initfe()
281 ret = mt312_writereg(state, MPEG_CTRL, 0x00); in mt312_initfe()
298 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32); in mt312_initfe()
312 ret = mt312_writereg(state, OP_CTRL, buf[0]); in mt312_initfe()
324 ret = mt312_writereg(state, CS_SW_LIM, 0x69); in mt312_initfe()
349 ret = mt312_writereg(state, DISEQC_MODE, in mt312_send_master_cmd()
360 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40)); in mt312_send_master_cmd()
384 ret = mt312_writereg(state, DISEQC_MODE, in mt312_send_burst()
408 ret = mt312_writereg(state, DISEQC_MODE, in mt312_set_tone()
430 return mt312_writereg(state, DISEQC_MODE, val); in mt312_set_voltage()
681 ret = mt312_writereg(state, GPP_CTRL, val); in mt312_i2c_gate_ctrl()
700 ret = mt312_writereg(state, GPP_CTRL, 0x00); in mt312_sleep()
705 ret = mt312_writereg(state, HW_CTRL, 0x0d); in mt312_sleep()
715 ret = mt312_writereg(state, CONFIG, config & 0x7f); in mt312_sleep()