Lines Matching +full:0 +full:x2180
46 } while (0)
52 } while (0)
57 __ret = (ret < 0); \
89 LG3306_UNLOCK = 0x00,
90 LG3306_LOCK = 0x01,
91 LG3306_UNKNOWN_LOCK = 0xff
95 LG3306_NL_INIT = 0x00,
96 LG3306_NL_PROCESS = 0x01,
97 LG3306_NL_LOCK = 0x02,
98 LG3306_NL_FAIL = 0x03,
99 LG3306_NL_UNKNOWN = 0xff
103 LG3306_VSB = 0x00,
104 LG3306_QAM64 = 0x01,
105 LG3306_QAM256 = 0x02,
106 LG3306_UNKNOWN_MODE = 0xff
126 u8 buf[] = { reg >> 8, reg & 0xff, val }; in lgdt3306a_write_reg()
128 .addr = state->cfg->i2c_addr, .flags = 0, in lgdt3306a_write_reg()
132 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); in lgdt3306a_write_reg()
138 msg.buf[0], msg.buf[1], msg.buf[2], ret); in lgdt3306a_write_reg()
139 if (ret < 0) in lgdt3306a_write_reg()
144 return 0; in lgdt3306a_write_reg()
150 u8 reg_buf[] = { reg >> 8, reg & 0xff }; in lgdt3306a_read_reg()
153 .flags = 0, .buf = reg_buf, .len = 2 }, in lgdt3306a_read_reg()
163 if (ret < 0) in lgdt3306a_read_reg()
168 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val); in lgdt3306a_read_reg()
170 return 0; in lgdt3306a_read_reg()
178 __val = 0; \
188 dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff); in lgdt3306a_set_reg_bit()
211 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); in lgdt3306a_soft_reset()
216 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); in lgdt3306a_soft_reset()
230 /* transport packet format - TPSENB=0x80 */ in lgdt3306a_mpeg_mode()
231 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7, in lgdt3306a_mpeg_mode()
232 mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0); in lgdt3306a_mpeg_mode()
238 * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration in lgdt3306a_mpeg_mode()
240 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0); in lgdt3306a_mpeg_mode()
244 ret = lgdt3306a_read_reg(state, 0x0070, &val); in lgdt3306a_mpeg_mode()
248 val |= 0x10; /* TPCLKSUPB=0x10 */ in lgdt3306a_mpeg_mode()
251 val &= ~0x10; in lgdt3306a_mpeg_mode()
253 ret = lgdt3306a_write_reg(state, 0x0070, val); in lgdt3306a_mpeg_mode()
269 ret = lgdt3306a_read_reg(state, 0x0070, &val); in lgdt3306a_mpeg_mode_polarity()
273 val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */ in lgdt3306a_mpeg_mode_polarity()
276 val |= 0x04; in lgdt3306a_mpeg_mode_polarity()
278 val |= 0x02; in lgdt3306a_mpeg_mode_polarity()
280 ret = lgdt3306a_write_reg(state, 0x0070, val); in lgdt3306a_mpeg_mode_polarity()
296 ret = lgdt3306a_read_reg(state, 0x0070, &val); in lgdt3306a_mpeg_tristate()
300 * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20, in lgdt3306a_mpeg_tristate()
301 * TPDATAOUTEN=0x08 in lgdt3306a_mpeg_tristate()
303 val &= ~0xa8; in lgdt3306a_mpeg_tristate()
304 ret = lgdt3306a_write_reg(state, 0x0070, val); in lgdt3306a_mpeg_tristate()
308 /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */ in lgdt3306a_mpeg_tristate()
309 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1); in lgdt3306a_mpeg_tristate()
315 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0); in lgdt3306a_mpeg_tristate()
319 ret = lgdt3306a_read_reg(state, 0x0070, &val); in lgdt3306a_mpeg_tristate()
323 val |= 0xa8; /* enable bus */ in lgdt3306a_mpeg_tristate()
324 ret = lgdt3306a_write_reg(state, 0x0070, val); in lgdt3306a_mpeg_tristate()
339 return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1); in lgdt3306a_ts_bus_ctrl()
350 if (mode == 0) { in lgdt3306a_power()
352 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); in lgdt3306a_power()
357 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0); in lgdt3306a_power()
363 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); in lgdt3306a_power()
368 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1); in lgdt3306a_power()
388 /* 0. Spectrum inversion detection manual; spectrum inverted */ in lgdt3306a_set_vsb()
389 ret = lgdt3306a_read_reg(state, 0x0002, &val); in lgdt3306a_set_vsb()
390 val &= 0xf7; /* SPECINVAUTO Off */ in lgdt3306a_set_vsb()
391 val |= 0x04; /* SPECINV On */ in lgdt3306a_set_vsb()
392 ret = lgdt3306a_write_reg(state, 0x0002, val); in lgdt3306a_set_vsb()
396 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */ in lgdt3306a_set_vsb()
397 ret = lgdt3306a_write_reg(state, 0x0008, 0x80); in lgdt3306a_set_vsb()
402 ret = lgdt3306a_read_reg(state, 0x0009, &val); in lgdt3306a_set_vsb()
403 val &= 0xe3; in lgdt3306a_set_vsb()
404 val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */ in lgdt3306a_set_vsb()
405 ret = lgdt3306a_write_reg(state, 0x0009, val); in lgdt3306a_set_vsb()
410 ret = lgdt3306a_read_reg(state, 0x0009, &val); in lgdt3306a_set_vsb()
411 val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */ in lgdt3306a_set_vsb()
412 ret = lgdt3306a_write_reg(state, 0x0009, val); in lgdt3306a_set_vsb()
417 ret = lgdt3306a_read_reg(state, 0x000d, &val); in lgdt3306a_set_vsb()
418 val &= 0xbf; /* SAMPLING4XFEN=0 */ in lgdt3306a_set_vsb()
419 ret = lgdt3306a_write_reg(state, 0x000d, val); in lgdt3306a_set_vsb()
423 #if 0 in lgdt3306a_set_vsb()
426 ret = lgdt3306a_write_reg(state, 0x0024, 0x00); in lgdt3306a_set_vsb()
431 ret = lgdt3306a_write_reg(state, 0x002e, 0x00); in lgdt3306a_set_vsb()
432 ret = lgdt3306a_write_reg(state, 0x002f, 0x00); in lgdt3306a_set_vsb()
433 ret = lgdt3306a_write_reg(state, 0x0030, 0x00); in lgdt3306a_set_vsb()
436 ret = lgdt3306a_write_reg(state, 0x002b, 0x00); in lgdt3306a_set_vsb()
437 ret = lgdt3306a_write_reg(state, 0x002c, 0x00); in lgdt3306a_set_vsb()
438 ret = lgdt3306a_write_reg(state, 0x002d, 0x00); in lgdt3306a_set_vsb()
441 ret = lgdt3306a_write_reg(state, 0x0028, 0x00); in lgdt3306a_set_vsb()
442 ret = lgdt3306a_write_reg(state, 0x0029, 0x00); in lgdt3306a_set_vsb()
443 ret = lgdt3306a_write_reg(state, 0x002a, 0x00); in lgdt3306a_set_vsb()
446 ret = lgdt3306a_write_reg(state, 0x0025, 0x00); in lgdt3306a_set_vsb()
447 ret = lgdt3306a_write_reg(state, 0x0026, 0x00); in lgdt3306a_set_vsb()
448 ret = lgdt3306a_write_reg(state, 0x0027, 0x00); in lgdt3306a_set_vsb()
454 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A); in lgdt3306a_set_vsb()
459 ret = lgdt3306a_write_reg(state, 0x002e, 0x5A); in lgdt3306a_set_vsb()
460 ret = lgdt3306a_write_reg(state, 0x002f, 0x00); in lgdt3306a_set_vsb()
461 ret = lgdt3306a_write_reg(state, 0x0030, 0x00); in lgdt3306a_set_vsb()
464 ret = lgdt3306a_write_reg(state, 0x002b, 0x36); in lgdt3306a_set_vsb()
465 ret = lgdt3306a_write_reg(state, 0x002c, 0x00); in lgdt3306a_set_vsb()
466 ret = lgdt3306a_write_reg(state, 0x002d, 0x00); in lgdt3306a_set_vsb()
469 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A); in lgdt3306a_set_vsb()
470 ret = lgdt3306a_write_reg(state, 0x0029, 0x00); in lgdt3306a_set_vsb()
471 ret = lgdt3306a_write_reg(state, 0x002a, 0x00); in lgdt3306a_set_vsb()
474 ret = lgdt3306a_write_reg(state, 0x0025, 0x06); in lgdt3306a_set_vsb()
475 ret = lgdt3306a_write_reg(state, 0x0026, 0x00); in lgdt3306a_set_vsb()
476 ret = lgdt3306a_write_reg(state, 0x0027, 0x00); in lgdt3306a_set_vsb()
479 ret = lgdt3306a_read_reg(state, 0x001e, &val); in lgdt3306a_set_vsb()
480 val &= 0x0f; in lgdt3306a_set_vsb()
481 val |= 0xa0; in lgdt3306a_set_vsb()
482 ret = lgdt3306a_write_reg(state, 0x001e, val); in lgdt3306a_set_vsb()
484 ret = lgdt3306a_write_reg(state, 0x0022, 0x08); in lgdt3306a_set_vsb()
486 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF); in lgdt3306a_set_vsb()
488 ret = lgdt3306a_read_reg(state, 0x211f, &val); in lgdt3306a_set_vsb()
489 val &= 0xef; in lgdt3306a_set_vsb()
490 ret = lgdt3306a_write_reg(state, 0x211f, val); in lgdt3306a_set_vsb()
492 ret = lgdt3306a_write_reg(state, 0x2173, 0x01); in lgdt3306a_set_vsb()
494 ret = lgdt3306a_read_reg(state, 0x1061, &val); in lgdt3306a_set_vsb()
495 val &= 0xf8; in lgdt3306a_set_vsb()
496 val |= 0x04; in lgdt3306a_set_vsb()
497 ret = lgdt3306a_write_reg(state, 0x1061, val); in lgdt3306a_set_vsb()
499 ret = lgdt3306a_read_reg(state, 0x103d, &val); in lgdt3306a_set_vsb()
500 val &= 0xcf; in lgdt3306a_set_vsb()
501 ret = lgdt3306a_write_reg(state, 0x103d, val); in lgdt3306a_set_vsb()
503 ret = lgdt3306a_write_reg(state, 0x2122, 0x40); in lgdt3306a_set_vsb()
505 ret = lgdt3306a_read_reg(state, 0x2141, &val); in lgdt3306a_set_vsb()
506 val &= 0x3f; in lgdt3306a_set_vsb()
507 ret = lgdt3306a_write_reg(state, 0x2141, val); in lgdt3306a_set_vsb()
509 ret = lgdt3306a_read_reg(state, 0x2135, &val); in lgdt3306a_set_vsb()
510 val &= 0x0f; in lgdt3306a_set_vsb()
511 val |= 0x70; in lgdt3306a_set_vsb()
512 ret = lgdt3306a_write_reg(state, 0x2135, val); in lgdt3306a_set_vsb()
514 ret = lgdt3306a_read_reg(state, 0x0003, &val); in lgdt3306a_set_vsb()
515 val &= 0xf7; in lgdt3306a_set_vsb()
516 ret = lgdt3306a_write_reg(state, 0x0003, val); in lgdt3306a_set_vsb()
518 ret = lgdt3306a_read_reg(state, 0x001c, &val); in lgdt3306a_set_vsb()
519 val &= 0x7f; in lgdt3306a_set_vsb()
520 ret = lgdt3306a_write_reg(state, 0x001c, val); in lgdt3306a_set_vsb()
523 ret = lgdt3306a_read_reg(state, 0x2179, &val); in lgdt3306a_set_vsb()
524 val &= 0xf8; in lgdt3306a_set_vsb()
525 ret = lgdt3306a_write_reg(state, 0x2179, val); in lgdt3306a_set_vsb()
527 ret = lgdt3306a_read_reg(state, 0x217a, &val); in lgdt3306a_set_vsb()
528 val &= 0xf8; in lgdt3306a_set_vsb()
529 ret = lgdt3306a_write_reg(state, 0x217a, val); in lgdt3306a_set_vsb()
548 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */ in lgdt3306a_set_qam()
549 ret = lgdt3306a_write_reg(state, 0x0008, 0x08); in lgdt3306a_set_qam()
554 ret = lgdt3306a_read_reg(state, 0x0002, &val); in lgdt3306a_set_qam()
555 val &= 0xfb; /* SPECINV Off */ in lgdt3306a_set_qam()
556 val |= 0x08; /* SPECINVAUTO On */ in lgdt3306a_set_qam()
557 ret = lgdt3306a_write_reg(state, 0x0002, val); in lgdt3306a_set_qam()
562 ret = lgdt3306a_read_reg(state, 0x0009, &val); in lgdt3306a_set_qam()
563 val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */ in lgdt3306a_set_qam()
564 ret = lgdt3306a_write_reg(state, 0x0009, val); in lgdt3306a_set_qam()
569 ret = lgdt3306a_read_reg(state, 0x0009, &val); in lgdt3306a_set_qam()
570 val &= 0xfc; in lgdt3306a_set_qam()
573 val |= 0x01; /* STDOPDETCMODE[1:0]= 1=Manual */ in lgdt3306a_set_qam()
575 val |= 0x02; /* STDOPDETCMODE[1:0]= 2=Auto */ in lgdt3306a_set_qam()
577 ret = lgdt3306a_write_reg(state, 0x0009, val); in lgdt3306a_set_qam()
582 ret = lgdt3306a_read_reg(state, 0x101a, &val); in lgdt3306a_set_qam()
583 val &= 0xf8; in lgdt3306a_set_qam()
585 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */ in lgdt3306a_set_qam()
587 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */ in lgdt3306a_set_qam()
589 ret = lgdt3306a_write_reg(state, 0x101a, val); in lgdt3306a_set_qam()
594 ret = lgdt3306a_read_reg(state, 0x000d, &val); in lgdt3306a_set_qam()
595 val &= 0xbf; in lgdt3306a_set_qam()
596 val |= 0x40; /* SAMPLING4XFEN=1 */ in lgdt3306a_set_qam()
597 ret = lgdt3306a_write_reg(state, 0x000d, val); in lgdt3306a_set_qam()
602 ret = lgdt3306a_read_reg(state, 0x0024, &val); in lgdt3306a_set_qam()
603 val &= 0x00; in lgdt3306a_set_qam()
604 ret = lgdt3306a_write_reg(state, 0x0024, val); in lgdt3306a_set_qam()
609 ret = lgdt3306a_read_reg(state, 0x000a, &val); in lgdt3306a_set_qam()
610 val &= 0xfd; in lgdt3306a_set_qam()
611 val |= 0x02; in lgdt3306a_set_qam()
612 ret = lgdt3306a_write_reg(state, 0x000a, val); in lgdt3306a_set_qam()
617 ret = lgdt3306a_read_reg(state, 0x2849, &val); in lgdt3306a_set_qam()
618 val &= 0xdf; in lgdt3306a_set_qam()
619 ret = lgdt3306a_write_reg(state, 0x2849, val); in lgdt3306a_set_qam()
624 ret = lgdt3306a_read_reg(state, 0x302b, &val); in lgdt3306a_set_qam()
625 val &= 0x7f; /* SELFSYNCFINDEN_CQS=0; disable auto reset */ in lgdt3306a_set_qam()
626 ret = lgdt3306a_write_reg(state, 0x302b, val); in lgdt3306a_set_qam()
686 return 0; in lgdt3306a_agc_setup()
698 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0); in lgdt3306a_set_inversion()
709 /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */ in lgdt3306a_set_inversion_auto()
710 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled); in lgdt3306a_set_inversion_auto()
740 nco1 = 0x34; in lgdt3306a_set_if()
741 nco2 = 0x00; in lgdt3306a_set_if()
744 nco1 = 0x38; in lgdt3306a_set_if()
745 nco2 = 0x00; in lgdt3306a_set_if()
748 nco1 = 0x40; in lgdt3306a_set_if()
749 nco2 = 0x00; in lgdt3306a_set_if()
752 nco1 = 0x50; in lgdt3306a_set_if()
753 nco2 = 0x00; in lgdt3306a_set_if()
756 nco1 = 0x56; in lgdt3306a_set_if()
757 nco2 = 0x14; in lgdt3306a_set_if()
760 ret = lgdt3306a_write_reg(state, 0x0010, nco1); in lgdt3306a_set_if()
763 ret = lgdt3306a_write_reg(state, 0x0011, nco2); in lgdt3306a_set_if()
769 return 0; in lgdt3306a_set_if()
780 return 0; in lgdt3306a_i2c_gate_ctrl()
784 /* NI2CRPTEN=0x80 */ in lgdt3306a_i2c_gate_ctrl()
785 return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1); in lgdt3306a_i2c_gate_ctrl()
799 ret = lgdt3306a_power(state, 0); /* power down */ in lgdt3306a_sleep()
803 return 0; in lgdt3306a_sleep()
823 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */ in lgdt3306a_init()
828 ret = lgdt3306a_set_inversion_auto(state, 0); in lgdt3306a_init()
839 /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */ in lgdt3306a_init()
840 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1); in lgdt3306a_init()
846 /* 0=same phase as ADC clock */ in lgdt3306a_init()
847 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0); in lgdt3306a_init()
853 /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */ in lgdt3306a_init()
854 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0); in lgdt3306a_init()
860 /* PLLSETAUTO=0x40; 0=off */ in lgdt3306a_init()
861 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0); in lgdt3306a_init()
866 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */ in lgdt3306a_init()
867 ret = lgdt3306a_read_reg(state, 0x0005, &val); in lgdt3306a_init()
870 val &= 0xc0; in lgdt3306a_init()
871 val |= 0x25; in lgdt3306a_init()
872 ret = lgdt3306a_write_reg(state, 0x0005, val); in lgdt3306a_init()
875 ret = lgdt3306a_write_reg(state, 0x0006, 0x64); in lgdt3306a_init()
879 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */ in lgdt3306a_init()
880 ret = lgdt3306a_read_reg(state, 0x000d, &val); in lgdt3306a_init()
883 val &= 0xc0; in lgdt3306a_init()
884 val |= 0x18; in lgdt3306a_init()
885 ret = lgdt3306a_write_reg(state, 0x000d, val); in lgdt3306a_init()
891 ret = lgdt3306a_read_reg(state, 0x0005, &val); in lgdt3306a_init()
894 val &= 0xc0; in lgdt3306a_init()
895 val |= 0x25; in lgdt3306a_init()
896 ret = lgdt3306a_write_reg(state, 0x0005, val); in lgdt3306a_init()
899 ret = lgdt3306a_write_reg(state, 0x0006, 0x64); in lgdt3306a_init()
903 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */ in lgdt3306a_init()
904 ret = lgdt3306a_read_reg(state, 0x000d, &val); in lgdt3306a_init()
907 val &= 0xc0; in lgdt3306a_init()
908 val |= 0x19; in lgdt3306a_init()
909 ret = lgdt3306a_write_reg(state, 0x000d, val); in lgdt3306a_init()
915 #if 0 in lgdt3306a_init()
916 ret = lgdt3306a_write_reg(state, 0x000e, 0x00); in lgdt3306a_init()
917 ret = lgdt3306a_write_reg(state, 0x000f, 0x00); in lgdt3306a_init()
921 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */ in lgdt3306a_init()
922 ret = lgdt3306a_write_reg(state, 0x0011, 0x00); in lgdt3306a_init()
925 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */ in lgdt3306a_init()
928 ret = lgdt3306a_read_reg(state, 0x103c, &val); in lgdt3306a_init()
929 val &= 0x0f; in lgdt3306a_init()
930 val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */ in lgdt3306a_init()
931 ret = lgdt3306a_write_reg(state, 0x103c, val); in lgdt3306a_init()
934 ret = lgdt3306a_read_reg(state, 0x103d, &val); in lgdt3306a_init()
935 val &= 0xfc; in lgdt3306a_init()
936 val |= 0x03; in lgdt3306a_init()
937 ret = lgdt3306a_write_reg(state, 0x103d, val); in lgdt3306a_init()
940 ret = lgdt3306a_read_reg(state, 0x1036, &val); in lgdt3306a_init()
941 val &= 0xf0; in lgdt3306a_init()
942 val |= 0x0c; in lgdt3306a_init()
943 ret = lgdt3306a_write_reg(state, 0x1036, val); in lgdt3306a_init()
946 ret = lgdt3306a_read_reg(state, 0x211f, &val); in lgdt3306a_init()
947 val &= 0xef; /* do not use imaginary of CIR */ in lgdt3306a_init()
948 ret = lgdt3306a_write_reg(state, 0x211f, val); in lgdt3306a_init()
951 ret = lgdt3306a_read_reg(state, 0x2849, &val); in lgdt3306a_init()
952 val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */ in lgdt3306a_init()
953 ret = lgdt3306a_write_reg(state, 0x2849, val); in lgdt3306a_init()
969 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in lgdt3306a_init()
986 return 0; in lgdt3306a_set_parameters()
998 fe->ops.i2c_gate_ctrl(fe, 0); in lgdt3306a_set_parameters()
999 #if 0 in lgdt3306a_set_parameters()
1030 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */ in lgdt3306a_set_parameters()
1056 return 0; in lgdt3306a_get_frontend()
1076 ret = lgdt3306a_read_reg(state, 0x21a1, &val); in lgdt3306a_monitor_vsb()
1079 snrRef = val & 0x3f; in lgdt3306a_monitor_vsb()
1081 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan); in lgdt3306a_monitor_vsb()
1085 ret = lgdt3306a_read_reg(state, 0x2191, &val); in lgdt3306a_monitor_vsb()
1088 nCombDet = (val & 0x80) >> 7; in lgdt3306a_monitor_vsb()
1090 ret = lgdt3306a_read_reg(state, 0x2180, &val); in lgdt3306a_monitor_vsb()
1093 fbDlyCir = (val & 0x03) << 8; in lgdt3306a_monitor_vsb()
1095 ret = lgdt3306a_read_reg(state, 0x2181, &val); in lgdt3306a_monitor_vsb()
1100 dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n", in lgdt3306a_monitor_vsb()
1104 ret = lgdt3306a_read_reg(state, 0x1061, &val); in lgdt3306a_monitor_vsb()
1107 val &= 0xf8; in lgdt3306a_monitor_vsb()
1108 if ((snrRef > 18) && (maxPowerMan > 0x68) in lgdt3306a_monitor_vsb()
1109 && (nCombDet == 0x01) in lgdt3306a_monitor_vsb()
1110 && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) { in lgdt3306a_monitor_vsb()
1112 val |= 0x00; /* final bandwidth = 0 */ in lgdt3306a_monitor_vsb()
1114 val |= 0x04; /* final bandwidth = 4 */ in lgdt3306a_monitor_vsb()
1116 ret = lgdt3306a_write_reg(state, 0x1061, val); in lgdt3306a_monitor_vsb()
1121 ret = lgdt3306a_read_reg(state, 0x0024, &val); in lgdt3306a_monitor_vsb()
1124 val &= 0x0f; in lgdt3306a_monitor_vsb()
1125 if (nCombDet == 0) { /* Turn on the Notch Filter */ in lgdt3306a_monitor_vsb()
1126 val |= 0x50; in lgdt3306a_monitor_vsb()
1128 ret = lgdt3306a_write_reg(state, 0x0024, val); in lgdt3306a_monitor_vsb()
1133 ret = lgdt3306a_read_reg(state, 0x103d, &val); in lgdt3306a_monitor_vsb()
1136 val &= 0xcf; in lgdt3306a_monitor_vsb()
1137 val |= 0x20; in lgdt3306a_monitor_vsb()
1138 ret = lgdt3306a_write_reg(state, 0x103d, val); in lgdt3306a_monitor_vsb()
1146 u8 val = 0; in lgdt3306a_check_oper_mode()
1149 ret = lgdt3306a_read_reg(state, 0x0081, &val); in lgdt3306a_check_oper_mode()
1153 if (val & 0x80) { in lgdt3306a_check_oper_mode()
1157 if (val & 0x08) { in lgdt3306a_check_oper_mode()
1158 ret = lgdt3306a_read_reg(state, 0x00a6, &val); in lgdt3306a_check_oper_mode()
1162 if (val & 0x01) { in lgdt3306a_check_oper_mode()
1178 u8 val = 0; in lgdt3306a_check_lock_status()
1188 ret = lgdt3306a_read_reg(state, 0x00a6, &val); in lgdt3306a_check_lock_status()
1192 if ((val & 0x80) == 0x80) in lgdt3306a_check_lock_status()
1202 ret = lgdt3306a_read_reg(state, 0x0080, &val); in lgdt3306a_check_lock_status()
1206 if ((val & 0x40) == 0x40) in lgdt3306a_check_lock_status()
1218 ret = lgdt3306a_read_reg(state, 0x1094, &val); in lgdt3306a_check_lock_status()
1222 if ((val & 0x80) == 0x80) in lgdt3306a_check_lock_status()
1236 ret = lgdt3306a_read_reg(state, 0x0080, &val); in lgdt3306a_check_lock_status()
1240 if ((val & 0x10) == 0x10) in lgdt3306a_check_lock_status()
1263 u8 val = 0; in lgdt3306a_check_neverlock_status()
1267 ret = lgdt3306a_read_reg(state, 0x0080, &val); in lgdt3306a_check_neverlock_status()
1270 lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03); in lgdt3306a_check_neverlock_status()
1279 u8 val = 0; in lgdt3306a_pre_monitoring()
1284 ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ); in lgdt3306a_pre_monitoring()
1289 ret = lgdt3306a_read_reg(state, 0x21a1, &val); in lgdt3306a_pre_monitoring()
1292 snrRef = val & 0x3f; in lgdt3306a_pre_monitoring()
1295 ret = lgdt3306a_read_reg(state, 0x2199, &val); in lgdt3306a_pre_monitoring()
1298 mainStrong = (val & 0x40) >> 6; in lgdt3306a_pre_monitoring()
1300 ret = lgdt3306a_read_reg(state, 0x0090, &val); in lgdt3306a_pre_monitoring()
1303 aiccrejStatus = (val & 0xf0) >> 4; in lgdt3306a_pre_monitoring()
1305 dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n", in lgdt3306a_pre_monitoring()
1308 #if 0 in lgdt3306a_pre_monitoring()
1310 if ((mainStrong == 0) && (currChDiffACQ > 0x70)) in lgdt3306a_pre_monitoring()
1312 if (mainStrong == 0) { in lgdt3306a_pre_monitoring()
1313 ret = lgdt3306a_read_reg(state, 0x2135, &val); in lgdt3306a_pre_monitoring()
1316 val &= 0x0f; in lgdt3306a_pre_monitoring()
1317 val |= 0xa0; in lgdt3306a_pre_monitoring()
1318 ret = lgdt3306a_write_reg(state, 0x2135, val); in lgdt3306a_pre_monitoring()
1322 ret = lgdt3306a_read_reg(state, 0x2141, &val); in lgdt3306a_pre_monitoring()
1325 val &= 0x3f; in lgdt3306a_pre_monitoring()
1326 val |= 0x80; in lgdt3306a_pre_monitoring()
1327 ret = lgdt3306a_write_reg(state, 0x2141, val); in lgdt3306a_pre_monitoring()
1331 ret = lgdt3306a_write_reg(state, 0x2122, 0x70); in lgdt3306a_pre_monitoring()
1335 ret = lgdt3306a_read_reg(state, 0x2135, &val); in lgdt3306a_pre_monitoring()
1338 val &= 0x0f; in lgdt3306a_pre_monitoring()
1339 val |= 0x70; in lgdt3306a_pre_monitoring()
1340 ret = lgdt3306a_write_reg(state, 0x2135, val); in lgdt3306a_pre_monitoring()
1344 ret = lgdt3306a_read_reg(state, 0x2141, &val); in lgdt3306a_pre_monitoring()
1347 val &= 0x3f; in lgdt3306a_pre_monitoring()
1348 val |= 0x40; in lgdt3306a_pre_monitoring()
1349 ret = lgdt3306a_write_reg(state, 0x2141, val); in lgdt3306a_pre_monitoring()
1353 ret = lgdt3306a_write_reg(state, 0x2122, 0x40); in lgdt3306a_pre_monitoring()
1357 return 0; in lgdt3306a_pre_monitoring()
1366 for (i = 0; i < 2; i++) { in lgdt3306a_sync_lock_poll()
1387 for (i = 0; i < 2; i++) { in lgdt3306a_fec_lock_poll()
1408 for (i = 0; i < 5; i++) { in lgdt3306a_neverlock_poll()
1427 ret = lgdt3306a_read_reg(state, 0x00fa, &val); in lgdt3306a_get_packet_error()
1438 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000
1444 u32 log_val = 0; in log10_x1000()
1447 if (x <= 0) in log10_x1000()
1451 return 0; /* log(1)=0 */ in log10_x1000()
1492 mse = (read_reg(state, 0x00ec) << 8) | in lgdt3306a_calculate_snr_x100()
1493 (read_reg(state, 0x00ed)); in lgdt3306a_calculate_snr_x100()
1494 pwr = (read_reg(state, 0x00e8) << 8) | in lgdt3306a_calculate_snr_x100()
1495 (read_reg(state, 0x00e9)); in lgdt3306a_calculate_snr_x100()
1497 if (mse == 0) /* no signal */ in lgdt3306a_calculate_snr_x100()
1498 return 0; in lgdt3306a_calculate_snr_x100()
1510 u8 cnt = 0; in lgdt3306a_vsb_lock_poll()
1514 for (cnt = 0; cnt < 10; cnt++) { in lgdt3306a_vsb_lock_poll()
1529 if ((snr >= 1500) && (packet_error < 0xff)) in lgdt3306a_vsb_lock_poll()
1544 for (cnt = 0; cnt < 10; cnt++) { in lgdt3306a_qam_lock_poll()
1556 if ((snr >= 1500) && (packet_error < 0xff)) in lgdt3306a_qam_lock_poll()
1569 u16 strength = 0; in lgdt3306a_read_status()
1570 int ret = 0; in lgdt3306a_read_status()
1574 if (ret == 0) in lgdt3306a_read_status()
1580 *status = 0; in lgdt3306a_read_status()
1612 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; in lgdt3306a_read_status()
1613 c->cnr.stat[0].svalue = lgdt3306a_calculate_snr_x100(state) * 10; in lgdt3306a_read_status()
1616 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in lgdt3306a_read_status()
1631 return 0; in lgdt3306a_read_snr()
1647 *strength = 0; in lgdt3306a_read_signal_strength()
1657 ret = lgdt3306a_read_reg(state, 0x00a6, &val); in lgdt3306a_read_signal_strength()
1661 if(val & 0x04) in lgdt3306a_read_signal_strength()
1675 str = 0; in lgdt3306a_read_signal_strength()
1677 str = (0xffff * 65) / 100; /* 65% */ in lgdt3306a_read_signal_strength()
1684 str = (0xffff * str) / 100; in lgdt3306a_read_signal_strength()
1700 *ber = 0; in lgdt3306a_read_ber()
1704 tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */ in lgdt3306a_read_ber()
1705 tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */ in lgdt3306a_read_ber()
1706 tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */ in lgdt3306a_read_ber()
1707 tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */ in lgdt3306a_read_ber()
1711 return 0; in lgdt3306a_read_ber()
1718 *ucblocks = 0; in lgdt3306a_read_ucblocks()
1722 *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */ in lgdt3306a_read_ucblocks()
1726 return 0; in lgdt3306a_read_ucblocks()
1733 int ret = 0; in lgdt3306a_tune()
1741 if (ret != 0) in lgdt3306a_tune()
1756 return 0; in lgdt3306a_get_tune_settings()
1761 enum fe_status status = 0; in lgdt3306a_search()
1802 i2c_adap ? i2c_adapter_id(i2c_adap) : 0, in lgdt3306a_attach()
1803 config ? config->i2c_addr : 0); in lgdt3306a_attach()
1819 ret = lgdt3306a_read_reg(state, 0x0000, &val); in lgdt3306a_attach()
1822 if ((val & 0x74) != 0x74) { in lgdt3306a_attach()
1823 pr_warn("expected 0x74, got 0x%x\n", (val & 0x74)); in lgdt3306a_attach()
1824 #if 0 in lgdt3306a_attach()
1829 ret = lgdt3306a_read_reg(state, 0x0001, &val); in lgdt3306a_attach()
1832 if ((val & 0xf6) != 0xc6) { in lgdt3306a_attach()
1833 pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6)); in lgdt3306a_attach()
1834 #if 0 in lgdt3306a_attach()
1839 ret = lgdt3306a_read_reg(state, 0x0002, &val); in lgdt3306a_attach()
1842 if ((val & 0x73) != 0x03) { in lgdt3306a_attach()
1843 pr_warn("expected 0x03, got 0x%x\n", (val & 0x73)); in lgdt3306a_attach()
1844 #if 0 in lgdt3306a_attach()
1867 0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1868 0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1869 0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1870 0x0003, /* AGCRFOUT */
1871 0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1872 0x0005, /* PLLINDIVSE */
1873 0x0006, /* PLLCTRL[7:0] 11100001 */
1874 0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1875 0x0008, /* STDOPMODE[7:0] 10000000 */
1876 0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
1877 0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
1878 0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1879 0x000d, /* x SAMPLING4 */
1880 0x000e, /* SAMFREQ[15:8] 00000000 */
1881 0x000f, /* SAMFREQ[7:0] 00000000 */
1882 0x0010, /* IFFREQ[15:8] 01100000 */
1883 0x0011, /* IFFREQ[7:0] 00000000 */
1884 0x0012, /* AGCEN AGCREFMO */
1885 0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1886 0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1887 0x0015, /* AGCREF[15:8] 00001010 */
1888 0x0016, /* AGCREF[7:0] 11100100 */
1889 0x0017, /* AGCDELAY[7:0] 00100000 */
1890 0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1891 0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
1892 0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
1893 0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1894 0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1895 0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
1896 0x0020, /* AICCDETTH[15:8] 01111100 */
1897 0x0021, /* AICCDETTH[7:0] 00000000 */
1898 0x0022, /* AICCOFFTH[15:8] 00000101 */
1899 0x0023, /* AICCOFFTH[7:0] 11100000 */
1900 0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1901 0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1902 0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1903 0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1904 0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1905 0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
1906 0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
1907 0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
1908 0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
1909 0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
1910 0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
1911 0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
1912 0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1913 0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1914 0x0032, /* DAGC1STEN DAGC1STER */
1915 0x0033, /* DAGC1STREF[15:8] 00001010 */
1916 0x0034, /* DAGC1STREF[7:0] 11100100 */
1917 0x0035, /* DAGC2NDE */
1918 0x0036, /* DAGC2NDREF[15:8] 00001010 */
1919 0x0037, /* DAGC2NDREF[7:0] 10000000 */
1920 0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
1921 0x003d, /* 1'b1 SAMGEARS */
1922 0x0040, /* SAMLFGMA */
1923 0x0041, /* SAMLFBWM */
1924 0x0044, /* 1'b1 CRGEARSHE */
1925 0x0045, /* CRLFGMAN */
1926 0x0046, /* CFLFBWMA */
1927 0x0047, /* CRLFGMAN */
1928 0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1929 0x0049, /* CRLFBWMA */
1930 0x004a, /* CRLFBWMA */
1931 0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1932 0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1933 0x0071, /* TPSENB TPSSOPBITE */
1934 0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1935 0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1936 0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1937 0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1938 0x0078, /* NBERPOLY[31:24] 00000000 */
1939 0x0079, /* NBERPOLY[23:16] 00000000 */
1940 0x007a, /* NBERPOLY[15:8] 00000000 */
1941 0x007b, /* NBERPOLY[7:0] 00000000 */
1942 0x007c, /* NBERPED[31:24] 00000000 */
1943 0x007d, /* NBERPED[23:16] 00000000 */
1944 0x007e, /* NBERPED[15:8] 00000000 */
1945 0x007f, /* NBERPED[7:0] 00000000 */
1946 0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1947 0x0085, /* SPECINVST */
1948 0x0088, /* SYSLOCKTIME[15:8] */
1949 0x0089, /* SYSLOCKTIME[7:0] */
1950 0x008c, /* FECLOCKTIME[15:8] */
1951 0x008d, /* FECLOCKTIME[7:0] */
1952 0x008e, /* AGCACCOUT[15:8] */
1953 0x008f, /* AGCACCOUT[7:0] */
1954 0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1955 0x0091, /* AICCVSYNC */
1956 0x009c, /* CARRFREQOFFSET[15:8] */
1957 0x009d, /* CARRFREQOFFSET[7:0] */
1958 0x00a1, /* SAMFREQOFFSET[23:16] */
1959 0x00a2, /* SAMFREQOFFSET[15:8] */
1960 0x00a3, /* SAMFREQOFFSET[7:0] */
1961 0x00a6, /* SYNCLOCK SYNCLOCKH */
1962 #if 0 /* covered elsewhere */
1963 0x00e8, /* CONSTPWR[15:8] */
1964 0x00e9, /* CONSTPWR[7:0] */
1965 0x00ea, /* BMSE[15:8] */
1966 0x00eb, /* BMSE[7:0] */
1967 0x00ec, /* MSE[15:8] */
1968 0x00ed, /* MSE[7:0] */
1969 0x00ee, /* CONSTI[7:0] */
1970 0x00ef, /* CONSTQ[7:0] */
1972 0x00f4, /* TPIFTPERRCNT[7:0] */
1973 0x00f5, /* TPCORREC */
1974 0x00f6, /* VBBER[15:8] */
1975 0x00f7, /* VBBER[7:0] */
1976 0x00f8, /* VABER[15:8] */
1977 0x00f9, /* VABER[7:0] */
1978 0x00fa, /* TPERRCNT[7:0] */
1979 0x00fb, /* NBERLOCK x x x x x x x */
1980 0x00fc, /* NBERVALUE[31:24] */
1981 0x00fd, /* NBERVALUE[23:16] */
1982 0x00fe, /* NBERVALUE[15:8] */
1983 0x00ff, /* NBERVALUE[7:0] */
1984 0x1000, /* 1'b0 WODAGCOU */
1985 0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
1986 0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
1987 0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
1988 0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
1989 0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
1990 0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
1991 0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
1992 0x103f, /* SAMZTEDSE */
1993 0x105d, /* EQSTATUSE */
1994 0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
1995 0x1060, /* 1'b1 EQSTATUSE */
1996 0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
1997 0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
1998 0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
1999 0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
2000 0x106e, /* x x x x x CREPHNEN_ */
2001 0x106f, /* CREPHNTH_V[7:0] 00010101 */
2002 0x1072, /* CRSWEEPN */
2003 0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
2004 0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
2005 0x1080, /* DAFTSTATUS[1:0] x x x x x x */
2006 0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
2007 0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
2008 0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
2009 #if 0 /* SMART_ANT */
2010 0x1f00, /* MODEDETE */
2011 0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
2012 0x1f03, /* NUMOFANT[7:0] 10000000 */
2013 0x1f04, /* x SELMASK[6:0] x0000000 */
2014 0x1f05, /* x SETMASK[6:0] x0000000 */
2015 0x1f06, /* x TXDATA[6:0] x0000000 */
2016 0x1f07, /* x CHNUMBER[6:0] x0000000 */
2017 0x1f09, /* AGCTIME[23:16] 10011000 */
2018 0x1f0a, /* AGCTIME[15:8] 10010110 */
2019 0x1f0b, /* AGCTIME[7:0] 10000000 */
2020 0x1f0c, /* ANTTIME[31:24] 00000000 */
2021 0x1f0d, /* ANTTIME[23:16] 00000011 */
2022 0x1f0e, /* ANTTIME[15:8] 10010000 */
2023 0x1f0f, /* ANTTIME[7:0] 10010000 */
2024 0x1f11, /* SYNCTIME[23:16] 10011000 */
2025 0x1f12, /* SYNCTIME[15:8] 10010110 */
2026 0x1f13, /* SYNCTIME[7:0] 10000000 */
2027 0x1f14, /* SNRTIME[31:24] 00000001 */
2028 0x1f15, /* SNRTIME[23:16] 01111101 */
2029 0x1f16, /* SNRTIME[15:8] 01111000 */
2030 0x1f17, /* SNRTIME[7:0] 01000000 */
2031 0x1f19, /* FECTIME[23:16] 00000000 */
2032 0x1f1a, /* FECTIME[15:8] 01110010 */
2033 0x1f1b, /* FECTIME[7:0] 01110000 */
2034 0x1f1d, /* FECTHD[7:0] 00000011 */
2035 0x1f1f, /* SNRTHD[23:16] 00001000 */
2036 0x1f20, /* SNRTHD[15:8] 01111111 */
2037 0x1f21, /* SNRTHD[7:0] 10000101 */
2038 0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
2039 0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
2040 0x1f82, /* x x x SCANOPCD[4:0] */
2041 0x1f83, /* x x x x MAINOPCD[3:0] */
2042 0x1f84, /* x x RXDATA[13:8] */
2043 0x1f85, /* RXDATA[7:0] */
2044 0x1f86, /* x x SDTDATA[13:8] */
2045 0x1f87, /* SDTDATA[7:0] */
2046 0x1f89, /* ANTSNR[23:16] */
2047 0x1f8a, /* ANTSNR[15:8] */
2048 0x1f8b, /* ANTSNR[7:0] */
2049 0x1f8c, /* x x x x ANTFEC[13:8] */
2050 0x1f8d, /* ANTFEC[7:0] */
2051 0x1f8e, /* MAXCNT[7:0] */
2052 0x1f8f, /* SCANCNT[7:0] */
2053 0x1f91, /* MAXPW[23:16] */
2054 0x1f92, /* MAXPW[15:8] */
2055 0x1f93, /* MAXPW[7:0] */
2056 0x1f95, /* CURPWMSE[23:16] */
2057 0x1f96, /* CURPWMSE[15:8] */
2058 0x1f97, /* CURPWMSE[7:0] */
2060 0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
2061 0x212a, /* EQAUTOST */
2062 0x2122, /* CHFAST[7:0] 01100000 */
2063 0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
2064 0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
2065 0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
2066 0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
2067 0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
2068 0x2162, /* AICCCTRLE */
2069 0x2173, /* PHNCNFCNT[7:0] 00000100 */
2070 0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
2071 0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
2072 0x217e, /* CNFCNTTPIF[7:0] 00001000 */
2073 0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
2074 0x2180, /* x x x x x x FBDLYCIR[9:8] */
2075 0x2181, /* FBDLYCIR[7:0] */
2076 0x2185, /* MAXPWRMAIN[7:0] */
2077 0x2191, /* NCOMBDET x x x x x x x */
2078 0x2199, /* x MAINSTRON */
2079 0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
2080 0x21a1, /* x x SNRREF[5:0] */
2081 0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
2082 0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
2083 0x2847, /* ENNOSIGDE */
2084 0x2849, /* 1'b1 1'b1 NOUSENOSI */
2085 0x284a, /* EQINITWAITTIME[7:0] 01100100 */
2086 0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
2087 0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
2088 0x3031, /* FRAMELOC */
2089 0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
2090 0x30a9, /* VDLOCK_Q FRAMELOCK */
2091 0x30aa, /* MPEGLOCK */
2095 static u8 regval1[numDumpRegs] = {0, };
2096 static u8 regval2[numDumpRegs] = {0, };
2100 memset(regval2, 0xff, sizeof(regval2)); in lgdt3306a_DumpAllRegs()
2109 if ((debug & DBG_DUMP) == 0) in lgdt3306a_DumpRegs()
2115 for (i = 0; i < numDumpRegs; i++) { in lgdt3306a_DumpRegs()
2169 return lgdt3306a_i2c_gate_ctrl(&state->frontend, 0); in lgdt3306a_deselect()
2204 1, 0, I2C_MUX_LOCKED, in lgdt3306a_probe()
2211 ret = i2c_mux_add_adapter(state->muxc, 0, 0); in lgdt3306a_probe()
2217 *config->i2c_adapter = state->muxc->adapter[0]; in lgdt3306a_probe()
2222 return 0; in lgdt3306a_probe()