Lines Matching +full:p +full:- +full:state
1 // SPDX-License-Identifier: GPL-2.0-or-later
40 static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data) in l64781_writereg() argument
44 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; in l64781_writereg()
46 if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1) in l64781_writereg()
50 return (ret != 1) ? -1 : 0; in l64781_writereg()
53 static int l64781_readreg (struct l64781_state* state, u8 reg) in l64781_readreg() argument
58 …struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 … in l64781_readreg()
59 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; in l64781_readreg()
61 ret = i2c_transfer(state->i2c, msg, 2); in l64781_readreg()
68 static void apply_tps (struct l64781_state* state) in apply_tps() argument
70 l64781_writereg (state, 0x2a, 0x00); in apply_tps()
71 l64781_writereg (state, 0x2a, 0x01); in apply_tps()
78 l64781_writereg (state, 0x2a, 0x02); in apply_tps()
82 static void reset_afc (struct l64781_state* state) in reset_afc() argument
86 l64781_writereg (state, 0x07, 0x9e); /* stall AFC */ in reset_afc()
87 l64781_writereg (state, 0x08, 0); /* AFC INIT FREQ */ in reset_afc()
88 l64781_writereg (state, 0x09, 0); in reset_afc()
89 l64781_writereg (state, 0x0a, 0); in reset_afc()
90 l64781_writereg (state, 0x07, 0x8e); in reset_afc()
91 l64781_writereg (state, 0x0e, 0); /* AGC gain to zero in beginning */ in reset_afc()
92 l64781_writereg (state, 0x11, 0x80); /* stall TIM */ in reset_afc()
93 l64781_writereg (state, 0x10, 0); /* TIM_OFFSET_LSB */ in reset_afc()
94 l64781_writereg (state, 0x12, 0); in reset_afc()
95 l64781_writereg (state, 0x13, 0); in reset_afc()
96 l64781_writereg (state, 0x11, 0x00); in reset_afc()
99 static int reset_and_configure (struct l64781_state* state) in reset_and_configure() argument
105 return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV; in reset_and_configure()
110 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in apply_frontend_param() local
111 struct l64781_state* state = fe->demodulator_priv; in apply_frontend_param() local
117 /* The Grundig 29504-401.04 Tuner comes with 18.432MHz crystal. */ in apply_frontend_param()
120 /* u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */ in apply_frontend_param()
121 /* bw_tab[p->bandWidth]<<10)/15625; */ in apply_frontend_param()
129 switch (p->bandwidth_hz) { in apply_frontend_param()
140 return -EINVAL; in apply_frontend_param()
143 if (fe->ops.tuner_ops.set_params) { in apply_frontend_param()
144 fe->ops.tuner_ops.set_params(fe); in apply_frontend_param()
145 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); in apply_frontend_param()
148 if (p->inversion != INVERSION_ON && in apply_frontend_param()
149 p->inversion != INVERSION_OFF) in apply_frontend_param()
150 return -EINVAL; in apply_frontend_param()
152 if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 && in apply_frontend_param()
153 p->code_rate_HP != FEC_3_4 && p->code_rate_HP != FEC_5_6 && in apply_frontend_param()
154 p->code_rate_HP != FEC_7_8) in apply_frontend_param()
155 return -EINVAL; in apply_frontend_param()
157 if (p->hierarchy != HIERARCHY_NONE && in apply_frontend_param()
158 (p->code_rate_LP != FEC_1_2 && p->code_rate_LP != FEC_2_3 && in apply_frontend_param()
159 p->code_rate_LP != FEC_3_4 && p->code_rate_LP != FEC_5_6 && in apply_frontend_param()
160 p->code_rate_LP != FEC_7_8)) in apply_frontend_param()
161 return -EINVAL; in apply_frontend_param()
163 if (p->modulation != QPSK && p->modulation != QAM_16 && in apply_frontend_param()
164 p->modulation != QAM_64) in apply_frontend_param()
165 return -EINVAL; in apply_frontend_param()
167 if (p->transmission_mode != TRANSMISSION_MODE_2K && in apply_frontend_param()
168 p->transmission_mode != TRANSMISSION_MODE_8K) in apply_frontend_param()
169 return -EINVAL; in apply_frontend_param()
171 if ((int)p->guard_interval < GUARD_INTERVAL_1_32 || in apply_frontend_param()
172 p->guard_interval > GUARD_INTERVAL_1_4) in apply_frontend_param()
173 return -EINVAL; in apply_frontend_param()
175 if ((int)p->hierarchy < HIERARCHY_NONE || in apply_frontend_param()
176 p->hierarchy > HIERARCHY_4) in apply_frontend_param()
177 return -EINVAL; in apply_frontend_param()
179 ddfs_offset_fixed = 0x4000-(ppm<<16)/bw/1000000; in apply_frontend_param()
190 spi_bias *= qam_tab[p->modulation]; in apply_frontend_param()
191 spi_bias /= p->code_rate_HP + 1; in apply_frontend_param()
192 spi_bias /= (guard_tab[p->guard_interval] + 32); in apply_frontend_param()
195 spi_bias *= p->code_rate_HP; in apply_frontend_param()
197 val0x04 = (p->transmission_mode << 2) | p->guard_interval; in apply_frontend_param()
198 val0x05 = fec_tab[p->code_rate_HP]; in apply_frontend_param()
200 if (p->hierarchy != HIERARCHY_NONE) in apply_frontend_param()
201 val0x05 |= (p->code_rate_LP - FEC_1_2) << 3; in apply_frontend_param()
203 val0x06 = (p->hierarchy << 2) | p->modulation; in apply_frontend_param()
205 l64781_writereg (state, 0x04, val0x04); in apply_frontend_param()
206 l64781_writereg (state, 0x05, val0x05); in apply_frontend_param()
207 l64781_writereg (state, 0x06, val0x06); in apply_frontend_param()
209 reset_afc (state); in apply_frontend_param()
212 l64781_writereg (state, 0x15, in apply_frontend_param()
213 p->transmission_mode == TRANSMISSION_MODE_2K ? 1 : 3); in apply_frontend_param()
214 l64781_writereg (state, 0x16, init_freq & 0xff); in apply_frontend_param()
215 l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff); in apply_frontend_param()
216 l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff); in apply_frontend_param()
218 l64781_writereg (state, 0x1b, spi_bias & 0xff); in apply_frontend_param()
219 l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff); in apply_frontend_param()
220 l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) | in apply_frontend_param()
221 (p->inversion == INVERSION_ON ? 0x80 : 0x00)); in apply_frontend_param()
223 l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff); in apply_frontend_param()
224 l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f); in apply_frontend_param()
226 l64781_readreg (state, 0x00); /* clear interrupt registers... */ in apply_frontend_param()
227 l64781_readreg (state, 0x01); /* dto. */ in apply_frontend_param()
229 apply_tps (state); in apply_frontend_param()
235 struct dtv_frontend_properties *p) in get_frontend() argument
237 struct l64781_state* state = fe->demodulator_priv; in get_frontend() local
241 tmp = l64781_readreg(state, 0x04); in get_frontend()
244 p->guard_interval = GUARD_INTERVAL_1_32; in get_frontend()
247 p->guard_interval = GUARD_INTERVAL_1_16; in get_frontend()
250 p->guard_interval = GUARD_INTERVAL_1_8; in get_frontend()
253 p->guard_interval = GUARD_INTERVAL_1_4; in get_frontend()
258 p->transmission_mode = TRANSMISSION_MODE_2K; in get_frontend()
261 p->transmission_mode = TRANSMISSION_MODE_8K; in get_frontend()
267 tmp = l64781_readreg(state, 0x05); in get_frontend()
270 p->code_rate_HP = FEC_1_2; in get_frontend()
273 p->code_rate_HP = FEC_2_3; in get_frontend()
276 p->code_rate_HP = FEC_3_4; in get_frontend()
279 p->code_rate_HP = FEC_5_6; in get_frontend()
282 p->code_rate_HP = FEC_7_8; in get_frontend()
289 p->code_rate_LP = FEC_1_2; in get_frontend()
292 p->code_rate_LP = FEC_2_3; in get_frontend()
295 p->code_rate_LP = FEC_3_4; in get_frontend()
298 p->code_rate_LP = FEC_5_6; in get_frontend()
301 p->code_rate_LP = FEC_7_8; in get_frontend()
307 tmp = l64781_readreg(state, 0x06); in get_frontend()
310 p->modulation = QPSK; in get_frontend()
313 p->modulation = QAM_16; in get_frontend()
316 p->modulation = QAM_64; in get_frontend()
323 p->hierarchy = HIERARCHY_NONE; in get_frontend()
326 p->hierarchy = HIERARCHY_1; in get_frontend()
329 p->hierarchy = HIERARCHY_2; in get_frontend()
332 p->hierarchy = HIERARCHY_4; in get_frontend()
339 tmp = l64781_readreg (state, 0x1d); in get_frontend()
340 p->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF; in get_frontend()
342 tmp = (int) (l64781_readreg (state, 0x08) | in get_frontend()
343 (l64781_readreg (state, 0x09) << 8) | in get_frontend()
344 (l64781_readreg (state, 0x0a) << 16)); in get_frontend()
345 p->frequency += tmp; in get_frontend()
352 struct l64781_state* state = fe->demodulator_priv; in l64781_read_status() local
353 int sync = l64781_readreg (state, 0x32); in l64781_read_status()
354 int gain = l64781_readreg (state, 0x0e); in l64781_read_status()
356 l64781_readreg (state, 0x00); /* clear interrupt registers... */ in l64781_read_status()
357 l64781_readreg (state, 0x01); /* dto. */ in l64781_read_status()
381 struct l64781_state* state = fe->demodulator_priv; in l64781_read_ber() local
385 *ber = l64781_readreg (state, 0x39) in l64781_read_ber()
386 | (l64781_readreg (state, 0x3a) << 8); in l64781_read_ber()
393 struct l64781_state* state = fe->demodulator_priv; in l64781_read_signal_strength() local
395 u8 gain = l64781_readreg (state, 0x0e); in l64781_read_signal_strength()
403 struct l64781_state* state = fe->demodulator_priv; in l64781_read_snr() local
405 u8 avg_quality = 0xff - l64781_readreg (state, 0x33); in l64781_read_snr()
413 struct l64781_state* state = fe->demodulator_priv; in l64781_read_ucblocks() local
415 *ucblocks = l64781_readreg (state, 0x37) in l64781_read_ucblocks()
416 | (l64781_readreg (state, 0x38) << 8); in l64781_read_ucblocks()
423 struct l64781_state* state = fe->demodulator_priv; in l64781_sleep() local
426 return l64781_writereg (state, 0x3e, 0x5a); in l64781_sleep()
431 struct l64781_state* state = fe->demodulator_priv; in l64781_init() local
433 reset_and_configure (state); in l64781_init()
436 l64781_writereg (state, 0x3e, 0xa5); in l64781_init()
439 l64781_writereg (state, 0x2a, 0x04); in l64781_init()
440 l64781_writereg (state, 0x2a, 0x00); in l64781_init()
444 l64781_writereg (state, 0x07, 0x8e); in l64781_init()
447 l64781_writereg (state, 0x0b, 0x81); in l64781_init()
450 l64781_writereg (state, 0x0c, 0x84); in l64781_init()
453 l64781_writereg (state, 0x0d, 0x8c); in l64781_init()
458 /*l64781_writereg (state, 0x19, 0x92);*/ in l64781_init()
461 l64781_writereg (state, 0x1e, 0x09); in l64781_init()
464 if (state->first) { in l64781_init()
465 state->first = 0; in l64781_init()
475 fesettings->min_delay_ms = 4000; in l64781_get_tune_settings()
476 fesettings->step_size = 0; in l64781_get_tune_settings()
477 fesettings->max_drift = 0; in l64781_get_tune_settings()
483 struct l64781_state* state = fe->demodulator_priv; in l64781_release() local
484 kfree(state); in l64781_release()
492 struct l64781_state* state = NULL; in l64781_attach() local
493 int reg0x3e = -1; in l64781_attach()
496 struct i2c_msg msg [] = { { .addr = config->demod_address, .flags = 0, .buf = b0, .len = 1 }, in l64781_attach()
497 { .addr = config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; in l64781_attach()
499 /* allocate memory for the internal state */ in l64781_attach()
500 state = kzalloc(sizeof(struct l64781_state), GFP_KERNEL); in l64781_attach()
501 if (state == NULL) goto error; in l64781_attach()
503 /* setup the state */ in l64781_attach()
504 state->config = config; in l64781_attach()
505 state->i2c = i2c; in l64781_attach()
506 state->first = 1; in l64781_attach()
512 if (reset_and_configure(state) < 0) { in l64781_attach()
518 if (i2c_transfer(state->i2c, msg, 2) != 2) { in l64781_attach()
524 reg0x3e = l64781_readreg(state, 0x3e); in l64781_attach()
533 l64781_writereg (state, 0x3e, 0x5a); in l64781_attach()
536 if (l64781_readreg(state, 0x1a) != 0) { in l64781_attach()
542 l64781_writereg (state, 0x3e, 0xa5); in l64781_attach()
545 if (l64781_readreg(state, 0x1a) != 0xa1) { in l64781_attach()
551 memcpy(&state->frontend.ops, &l64781_ops, sizeof(struct dvb_frontend_ops)); in l64781_attach()
552 state->frontend.demodulator_priv = state; in l64781_attach()
553 return &state->frontend; in l64781_attach()
557 l64781_writereg (state, 0x3e, reg0x3e); /* restore reg 0x3e */ in l64781_attach()
558 kfree(state); in l64781_attach()
565 .name = "LSI L64781 DVB-T",
592 MODULE_DESCRIPTION("LSI L64781 DVB-T Demodulator driver");