Lines Matching +full:0 +full:xf8
27 } while (0)
37 0x23, 0x05,
38 0x08, 0x03,
39 0x0c, 0x00,
40 0x21, 0x54,
41 0x25, 0x82,
42 0x27, 0x31,
43 0x30, 0x08,
44 0x31, 0x40,
45 0x32, 0x32,
46 0x33, 0x35,
47 0x35, 0xff,
48 0x3a, 0x00,
49 0x37, 0x10,
50 0x38, 0x10,
51 0x39, 0x02,
52 0x42, 0x60,
53 0x4a, 0x40,
54 0x4b, 0x04,
55 0x4d, 0x91,
56 0x5d, 0xc8,
57 0x50, 0x77,
58 0x51, 0x77,
59 0x52, 0x36,
60 0x53, 0x36,
61 0x56, 0x01,
62 0x63, 0x43,
63 0x64, 0x30,
64 0x65, 0x40,
65 0x68, 0x26,
66 0x69, 0x4c,
67 0x70, 0x20,
68 0x71, 0x70,
69 0x72, 0x04,
70 0x73, 0x00,
71 0x70, 0x40,
72 0x71, 0x70,
73 0x72, 0x04,
74 0x73, 0x00,
75 0x70, 0x60,
76 0x71, 0x70,
77 0x72, 0x04,
78 0x73, 0x00,
79 0x70, 0x80,
80 0x71, 0x70,
81 0x72, 0x04,
82 0x73, 0x00,
83 0x70, 0xa0,
84 0x71, 0x70,
85 0x72, 0x04,
86 0x73, 0x00,
87 0x70, 0x1f,
88 0x76, 0x00,
89 0x77, 0xd1,
90 0x78, 0x0c,
91 0x79, 0x80,
92 0x7f, 0x04,
93 0x7c, 0x00,
94 0x80, 0x86,
95 0x81, 0xa6,
96 0x85, 0x04,
97 0xcd, 0xf4,
98 0x90, 0x33,
99 0xa0, 0x44,
100 0xc0, 0x18,
101 0xc3, 0x10,
102 0xc4, 0x08,
103 0xc5, 0x80,
104 0xc6, 0x80,
105 0xc7, 0x0a,
106 0xc8, 0x1a,
107 0xc9, 0x80,
108 0xfe, 0x92,
109 0xe0, 0xf8,
110 0xe6, 0x8b,
111 0xd0, 0x40,
112 0xf8, 0x20,
113 0xfa, 0x0f,
114 0xfd, 0x20,
115 0xad, 0x20,
116 0xae, 0x07,
117 0xb8, 0x00,
122 0x23, 0x0f,
123 0x08, 0x07,
124 0x0c, 0x00,
125 0x21, 0x54,
126 0x25, 0x82,
127 0x27, 0x31,
128 0x30, 0x08,
129 0x31, 0x32,
130 0x32, 0x32,
131 0x33, 0x35,
132 0x35, 0xff,
133 0x3a, 0x00,
134 0x37, 0x10,
135 0x38, 0x10,
136 0x39, 0x02,
137 0x42, 0x60,
138 0x4a, 0x80,
139 0x4b, 0x04,
140 0x4d, 0x81,
141 0x5d, 0x88,
142 0x50, 0x36,
143 0x51, 0x36,
144 0x52, 0x36,
145 0x53, 0x36,
146 0x63, 0x60,
147 0x64, 0x10,
148 0x65, 0x10,
149 0x68, 0x04,
150 0x69, 0x29,
151 0x70, 0x20,
152 0x71, 0x70,
153 0x72, 0x04,
154 0x73, 0x00,
155 0x70, 0x40,
156 0x71, 0x70,
157 0x72, 0x04,
158 0x73, 0x00,
159 0x70, 0x60,
160 0x71, 0x70,
161 0x72, 0x04,
162 0x73, 0x00,
163 0x70, 0x80,
164 0x71, 0x70,
165 0x72, 0x04,
166 0x73, 0x00,
167 0x70, 0xa0,
168 0x71, 0x70,
169 0x72, 0x04,
170 0x73, 0x00,
171 0x70, 0x1f,
172 0xa0, 0x44,
173 0xc0, 0x08,
174 0xc1, 0x10,
175 0xc2, 0x08,
176 0xc3, 0x10,
177 0xc4, 0x08,
178 0xc5, 0xf0,
179 0xc6, 0xf0,
180 0xc7, 0x0a,
181 0xc8, 0x1a,
182 0xc9, 0x80,
183 0xca, 0x23,
184 0xcb, 0x24,
185 0xce, 0x74,
186 0x90, 0x03,
187 0x76, 0x80,
188 0x77, 0x42,
189 0x78, 0x0a,
190 0x79, 0x80,
191 0xad, 0x40,
192 0xae, 0x07,
193 0x7f, 0xd4,
194 0x7c, 0x00,
195 0x80, 0xa8,
196 0x81, 0xda,
197 0x7c, 0x01,
198 0x80, 0xda,
199 0x81, 0xec,
200 0x7c, 0x02,
201 0x80, 0xca,
202 0x81, 0xeb,
203 0x7c, 0x03,
204 0x80, 0xba,
205 0x81, 0xdb,
206 0x85, 0x08,
207 0x86, 0x00,
208 0x87, 0x02,
209 0x89, 0x80,
210 0x8b, 0x44,
211 0x8c, 0xaa,
212 0x8a, 0x10,
213 0xba, 0x00,
214 0xf5, 0x04,
215 0xfe, 0x44,
216 0xd2, 0x32,
217 0xb8, 0x00,
232 .flags = 0, .buf = buf, .len = 2 }; in ds3000_writereg()
235 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data); in ds3000_writereg()
239 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n", in ds3000_writereg()
244 return 0; in ds3000_writereg()
252 ds3000_writereg(state, 0x03, 0x12); in ds3000_i2c_gate_ctrl()
254 ds3000_writereg(state, 0x03, 0x02); in ds3000_i2c_gate_ctrl()
256 return 0; in ds3000_i2c_gate_ctrl()
263 int i, ret = 0; in ds3000_writeFW()
274 msg.flags = 0; in ds3000_writeFW()
278 for (i = 0; i < len; i += 32) { in ds3000_writeFW()
281 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len); in ds3000_writeFW()
285 printk(KERN_ERR "%s: write error(err == %i, reg == 0x%02x\n", in ds3000_writeFW()
291 ret = 0; in ds3000_writeFW()
303 u8 b1[] = { 0 }; in ds3000_readreg()
307 .flags = 0, in ds3000_readreg()
321 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret); in ds3000_readreg()
325 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]); in ds3000_readreg()
327 return b1[0]; in ds3000_readreg()
337 int ret = 0; in ds3000_firmware_ondemand()
341 ret = ds3000_readreg(state, 0xb2); in ds3000_firmware_ondemand()
342 if (ret < 0) in ds3000_firmware_ondemand()
365 ret == 0 ? "complete" : "failed"); in ds3000_firmware_ondemand()
374 int ret = 0; in ds3000_load_firmware()
379 fw->data[0], in ds3000_load_firmware()
385 ds3000_writereg(state, 0xb2, 0x01); in ds3000_load_firmware()
387 ret = ds3000_writeFW(state, 0xb0, fw->data, fw->size); in ds3000_load_firmware()
388 ds3000_writereg(state, 0xb2, 0x00); in ds3000_load_firmware()
401 data = ds3000_readreg(state, 0xa2); in ds3000_set_voltage()
402 data |= 0x03; /* bit0 V/H, bit1 off/on */ in ds3000_set_voltage()
406 data &= ~0x03; in ds3000_set_voltage()
409 data &= ~0x03; in ds3000_set_voltage()
410 data |= 0x01; in ds3000_set_voltage()
416 ds3000_writereg(state, 0xa2, data); in ds3000_set_voltage()
418 return 0; in ds3000_set_voltage()
427 *status = 0; in ds3000_read_status()
431 lock = ds3000_readreg(state, 0xd1); in ds3000_read_status()
432 if ((lock & 0x07) == 0x07) in ds3000_read_status()
439 lock = ds3000_readreg(state, 0x0d); in ds3000_read_status()
440 if ((lock & 0x8f) == 0x8f) in ds3000_read_status()
451 state->config->set_lock_led(fe, *status == 0 ? 0 : 1); in ds3000_read_status()
453 dprintk("%s: status = 0x%02x\n", __func__, lock); in ds3000_read_status()
455 return 0; in ds3000_read_status()
472 ds3000_writereg(state, 0xf9, 0x04); in ds3000_read_ber()
474 data = ds3000_readreg(state, 0xf8); in ds3000_read_ber()
476 if ((data & 0x10) == 0) { in ds3000_read_ber()
480 *ber = (ds3000_readreg(state, 0xf7) << 8) | in ds3000_read_ber()
481 ds3000_readreg(state, 0xf6); in ds3000_read_ber()
485 data |= 0x10; in ds3000_read_ber()
486 ds3000_writereg(state, 0xf8, data); in ds3000_read_ber()
487 ds3000_writereg(state, 0xf8, data); in ds3000_read_ber()
491 *ber = 0xffffffff; in ds3000_read_ber()
495 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) | in ds3000_read_ber()
496 (ds3000_readreg(state, 0xd6) << 8) | in ds3000_read_ber()
497 ds3000_readreg(state, 0xd5); in ds3000_read_ber()
499 ber_reading = (ds3000_readreg(state, 0xf8) << 8) | in ds3000_read_ber()
500 ds3000_readreg(state, 0xf7); in ds3000_read_ber()
503 ds3000_writereg(state, 0xd1, 0x01); in ds3000_read_ber()
505 ds3000_writereg(state, 0xf9, 0x01); in ds3000_read_ber()
507 ds3000_writereg(state, 0xf9, 0x00); in ds3000_read_ber()
509 ds3000_writereg(state, 0xd1, 0x00); in ds3000_read_ber()
514 *ber = 0xffffffff; in ds3000_read_ber()
520 return 0; in ds3000_read_ber()
529 return 0; in ds3000_read_signal_strength()
540 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03, in ds3000_read_snr()
541 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717, in ds3000_read_snr()
542 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505 in ds3000_read_snr()
545 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103, in ds3000_read_snr()
546 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5, in ds3000_read_snr()
547 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6, in ds3000_read_snr()
548 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888, in ds3000_read_snr()
549 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51, in ds3000_read_snr()
550 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68, in ds3000_read_snr()
551 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206, in ds3000_read_snr()
552 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a, in ds3000_read_snr()
553 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649, in ds3000_read_snr()
554 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813, in ds3000_read_snr()
555 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1, in ds3000_read_snr()
556 0x49e9, 0x4a20, 0x4a57 in ds3000_read_snr()
563 snr_reading = ds3000_readreg(state, 0xff); in ds3000_read_snr()
565 if (snr_reading == 0) in ds3000_read_snr()
566 *snr = 0x0000; in ds3000_read_snr()
575 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, in ds3000_read_snr()
579 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) + in ds3000_read_snr()
580 (ds3000_readreg(state, 0x8d) << 4); in ds3000_read_snr()
581 dvbs2_signal_reading = ds3000_readreg(state, 0x8e); in ds3000_read_snr()
583 if (tmp == 0) { in ds3000_read_snr()
584 *snr = 0x0000; in ds3000_read_snr()
585 return 0; in ds3000_read_snr()
587 if (dvbs2_noise_reading == 0) { in ds3000_read_snr()
588 snr_value = 0x0013; in ds3000_read_snr()
591 *snr = 0xffff; in ds3000_read_snr()
592 return 0; in ds3000_read_snr()
608 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, in ds3000_read_snr()
615 return 0; in ds3000_read_snr()
630 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) | in ds3000_read_ucblocks()
631 ds3000_readreg(state, 0xf4); in ds3000_read_ucblocks()
632 data = ds3000_readreg(state, 0xf8); in ds3000_read_ucblocks()
634 data &= ~0x20; in ds3000_read_ucblocks()
635 ds3000_writereg(state, 0xf8, data); in ds3000_read_ucblocks()
637 data |= 0x20; in ds3000_read_ucblocks()
638 ds3000_writereg(state, 0xf8, data); in ds3000_read_ucblocks()
641 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) | in ds3000_read_ucblocks()
642 ds3000_readreg(state, 0xe1); in ds3000_read_ucblocks()
653 return 0; in ds3000_read_ucblocks()
667 data = ds3000_readreg(state, 0xa2); in ds3000_set_tone()
668 data &= ~0xc0; in ds3000_set_tone()
669 ds3000_writereg(state, 0xa2, data); in ds3000_set_tone()
674 data = ds3000_readreg(state, 0xa1); in ds3000_set_tone()
675 data &= ~0x43; in ds3000_set_tone()
676 data |= 0x04; in ds3000_set_tone()
677 ds3000_writereg(state, 0xa1, data); in ds3000_set_tone()
681 data = ds3000_readreg(state, 0xa2); in ds3000_set_tone()
682 data |= 0x80; in ds3000_set_tone()
683 ds3000_writereg(state, 0xa2, data); in ds3000_set_tone()
687 return 0; in ds3000_set_tone()
699 for (i = 0 ; i < d->msg_len;) { in ds3000_send_diseqc_msg()
700 dprintk("0x%02x", d->msg[i]); in ds3000_send_diseqc_msg()
706 data = ds3000_readreg(state, 0xa2); in ds3000_send_diseqc_msg()
707 data &= ~0xc0; in ds3000_send_diseqc_msg()
708 ds3000_writereg(state, 0xa2, data); in ds3000_send_diseqc_msg()
711 for (i = 0; i < d->msg_len; i++) in ds3000_send_diseqc_msg()
712 ds3000_writereg(state, 0xa3 + i, d->msg[i]); in ds3000_send_diseqc_msg()
714 data = ds3000_readreg(state, 0xa1); in ds3000_send_diseqc_msg()
717 data &= ~0xf8; in ds3000_send_diseqc_msg()
720 data |= ((d->msg_len - 1) << 3) | 0x07; in ds3000_send_diseqc_msg()
721 ds3000_writereg(state, 0xa1, data); in ds3000_send_diseqc_msg()
724 for (i = 0; i < 15; i++) { in ds3000_send_diseqc_msg()
725 data = ds3000_readreg(state, 0xa1); in ds3000_send_diseqc_msg()
726 if ((data & 0x40) == 0) in ds3000_send_diseqc_msg()
733 data = ds3000_readreg(state, 0xa1); in ds3000_send_diseqc_msg()
734 data &= ~0x80; in ds3000_send_diseqc_msg()
735 data |= 0x40; in ds3000_send_diseqc_msg()
736 ds3000_writereg(state, 0xa1, data); in ds3000_send_diseqc_msg()
738 data = ds3000_readreg(state, 0xa2); in ds3000_send_diseqc_msg()
739 data &= ~0xc0; in ds3000_send_diseqc_msg()
740 data |= 0x80; in ds3000_send_diseqc_msg()
741 ds3000_writereg(state, 0xa2, data); in ds3000_send_diseqc_msg()
746 data = ds3000_readreg(state, 0xa2); in ds3000_send_diseqc_msg()
747 data &= ~0xc0; in ds3000_send_diseqc_msg()
748 data |= 0x80; in ds3000_send_diseqc_msg()
749 ds3000_writereg(state, 0xa2, data); in ds3000_send_diseqc_msg()
751 return 0; in ds3000_send_diseqc_msg()
764 data = ds3000_readreg(state, 0xa2); in ds3000_diseqc_send_burst()
765 data &= ~0xc0; in ds3000_diseqc_send_burst()
766 ds3000_writereg(state, 0xa2, data); in ds3000_diseqc_send_burst()
771 ds3000_writereg(state, 0xa1, 0x02); in ds3000_diseqc_send_burst()
774 ds3000_writereg(state, 0xa1, 0x01); in ds3000_diseqc_send_burst()
779 for (i = 0; i < 5; i++) { in ds3000_diseqc_send_burst()
780 data = ds3000_readreg(state, 0xa1); in ds3000_diseqc_send_burst()
781 if ((data & 0x40) == 0) in ds3000_diseqc_send_burst()
787 data = ds3000_readreg(state, 0xa1); in ds3000_diseqc_send_burst()
788 data &= ~0x80; in ds3000_diseqc_send_burst()
789 data |= 0x40; in ds3000_diseqc_send_burst()
790 ds3000_writereg(state, 0xa1, data); in ds3000_diseqc_send_burst()
792 data = ds3000_readreg(state, 0xa2); in ds3000_diseqc_send_burst()
793 data &= ~0xc0; in ds3000_diseqc_send_burst()
794 data |= 0x80; in ds3000_diseqc_send_burst()
795 ds3000_writereg(state, 0xa2, data); in ds3000_diseqc_send_burst()
800 data = ds3000_readreg(state, 0xa2); in ds3000_diseqc_send_burst()
801 data &= ~0xc0; in ds3000_diseqc_send_burst()
802 data |= 0x80; in ds3000_diseqc_send_burst()
803 ds3000_writereg(state, 0xa2, data); in ds3000_diseqc_send_burst()
805 return 0; in ds3000_diseqc_send_burst()
813 state->config->set_lock_led(fe, 0); in ds3000_release()
836 state->prevUCBS2 = 0; in ds3000_attach()
839 ret = ds3000_readreg(state, 0x00) & 0xfe; in ds3000_attach()
840 if (ret != 0xe0) { in ds3000_attach()
847 ds3000_readreg(state, 0x02), in ds3000_attach()
848 ds3000_readreg(state, 0x01)); in ds3000_attach()
874 if (tmp < 0) in ds3000_set_carrier_offset()
877 ds3000_writereg(state, 0x5f, tmp >> 8); in ds3000_set_carrier_offset()
878 ds3000_writereg(state, 0x5e, tmp & 0xff); in ds3000_set_carrier_offset()
880 return 0; in ds3000_set_carrier_offset()
897 state->config->set_ts_params(fe, 0); in ds3000_set_frontend()
903 ds3000_writereg(state, 0x07, 0x80); in ds3000_set_frontend()
904 ds3000_writereg(state, 0x07, 0x00); in ds3000_set_frontend()
906 ds3000_writereg(state, 0xb2, 0x01); in ds3000_set_frontend()
908 ds3000_writereg(state, 0x00, 0x01); in ds3000_set_frontend()
913 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2) in ds3000_set_frontend()
917 value = ds3000_readreg(state, 0xfe); in ds3000_set_frontend()
918 value &= 0xc0; in ds3000_set_frontend()
919 value |= 0x1b; in ds3000_set_frontend()
920 ds3000_writereg(state, 0xfe, value); in ds3000_set_frontend()
924 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2) in ds3000_set_frontend()
929 ds3000_writereg(state, 0xfe, 0x54); in ds3000_set_frontend()
931 ds3000_writereg(state, 0xfe, 0x98); in ds3000_set_frontend()
938 ds3000_writereg(state, 0x29, 0x80); in ds3000_set_frontend()
940 ds3000_writereg(state, 0x25, 0x8a); in ds3000_set_frontend()
954 if (value % 2 != 0) in ds3000_set_frontend()
956 ds3000_writereg(state, 0xc3, 0x0d); in ds3000_set_frontend()
957 ds3000_writereg(state, 0xc8, value); in ds3000_set_frontend()
958 ds3000_writereg(state, 0xc4, 0x10); in ds3000_set_frontend()
959 ds3000_writereg(state, 0xc7, 0x0e); in ds3000_set_frontend()
962 if (value % 2 != 0) in ds3000_set_frontend()
964 ds3000_writereg(state, 0xc3, 0x07); in ds3000_set_frontend()
965 ds3000_writereg(state, 0xc8, value); in ds3000_set_frontend()
966 ds3000_writereg(state, 0xc4, 0x09); in ds3000_set_frontend()
967 ds3000_writereg(state, 0xc7, 0x12); in ds3000_set_frontend()
970 ds3000_writereg(state, 0xc3, value); in ds3000_set_frontend()
971 ds3000_writereg(state, 0xc8, 0x0e); in ds3000_set_frontend()
972 ds3000_writereg(state, 0xc4, 0x07); in ds3000_set_frontend()
973 ds3000_writereg(state, 0xc7, 0x18); in ds3000_set_frontend()
976 ds3000_writereg(state, 0xc3, value); in ds3000_set_frontend()
977 ds3000_writereg(state, 0xc8, 0x0a); in ds3000_set_frontend()
978 ds3000_writereg(state, 0xc4, 0x05); in ds3000_set_frontend()
979 ds3000_writereg(state, 0xc7, 0x24); in ds3000_set_frontend()
985 ds3000_writereg(state, 0x61, value & 0x00ff); in ds3000_set_frontend()
986 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8); in ds3000_set_frontend()
989 ds3000_writereg(state, 0x56, 0x00); in ds3000_set_frontend()
992 ds3000_writereg(state, 0x76, 0x00); in ds3000_set_frontend()
994 /*ds3000_writereg(state, 0x08, 0x03); in ds3000_set_frontend()
995 ds3000_writereg(state, 0xfd, 0x22); in ds3000_set_frontend()
996 ds3000_writereg(state, 0x08, 0x07); in ds3000_set_frontend()
997 ds3000_writereg(state, 0xfd, 0x42); in ds3000_set_frontend()
998 ds3000_writereg(state, 0x08, 0x07);*/ in ds3000_set_frontend()
1004 ds3000_writereg(state, 0xfd, 0x80); in ds3000_set_frontend()
1007 ds3000_writereg(state, 0xfd, 0x01); in ds3000_set_frontend()
1013 ds3000_writereg(state, 0x00, 0x00); in ds3000_set_frontend()
1015 ds3000_writereg(state, 0xb2, 0x00); in ds3000_set_frontend()
1023 for (i = 0; i < 30 ; i++) { in ds3000_set_frontend()
1031 return 0; in ds3000_set_frontend()
1056 state->config->set_lock_led(fe, 0); in ds3000_get_algo()
1074 ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08)); in ds3000_initfe()
1079 if (ret != 0) { in ds3000_initfe()
1084 return 0; in ds3000_initfe()
1125 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");