Lines Matching +full:adc +full:- +full:res +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0-only
3 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
5 * Copyright (C) 2003-2007 Micronas
21 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
22 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
194 return -1; in i2c_write()
211 return -1; in i2c_read()
227 u8 adr = state->config.demod_address; in Read16()
232 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0) in Read16()
233 return -1; in Read16()
241 u8 adr = state->config.demod_address; in Read32()
247 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0) in Read32()
248 return -1; in Read32()
257 u8 adr = state->config.demod_address; in Write16()
263 if (i2c_write(state->i2c, adr, mm, 6) < 0) in Write16()
264 return -1; in Write16()
270 u8 adr = state->config.demod_address; in Write32()
277 if (i2c_write(state->i2c, adr, mm, 8) < 0) in Write32()
278 return -1; in Write32()
285 u8 adr = state->config.demod_address; in write_chunk()
293 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) { in write_chunk()
295 return -1; in write_chunk()
307 return -1; in WriteBlock()
310 BlockSize -= Chunk; in WriteBlock()
347 return WriteTable(state, state->m_ResetCEFR); in ResetCEFR()
352 return WriteTable(state, state->m_InitCP); in InitCP()
358 enum app_env AppEnv = state->app_env_default; in InitCE()
361 status = WriteTable(state, state->m_InitCE); in InitCE()
365 if (state->operation_mode == OM_DVBT_Diversity_Front || in InitCE()
366 state->operation_mode == OM_DVBT_Diversity_End) { in InitCE()
367 AppEnv = state->app_env_diversity; in InitCE()
377 } else if (AppEnv == APPENV_MOBILE && state->type_A) { in InitCE()
381 } else if (AppEnv == APPENV_MOBILE && !state->type_A) { in InitCE()
399 u16 ocModeLop = state->m_EcOcRegOcModeLop; in StopOC()
409 state->m_EcOcRegSncSncLvl = ocSyncLvl; in StopOC()
412 /* Flush FIFO (byte-boundary) at fixed rate */ in StopOC()
447 ocModeLop |= 0x2; /* Magically-out-of-sync */ in StopOC()
473 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); in StartOC()
476 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); in StartOC()
495 return WriteTable(state, state->m_InitEQ); in InitEQ()
500 return WriteTable(state, state->m_InitEC); in InitEC()
505 return WriteTable(state, state->m_InitSC); in InitSC()
510 return WriteTable(state, state->m_InitAtomicRead); in InitAtomicRead()
535 if (state->drxd_state != DRXD_STARTED) in DRX_GetLockStatus()
557 if (cfg->outputLevel > DRXD_FE_CTRL_MAX) in SetCfgIfAgc()
558 return -1; in SetCfgIfAgc()
560 if (cfg->ctrlMode == AGC_CTRL_USER) { in SetCfgIfAgc()
574 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel & in SetCfgIfAgc()
580 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { in SetCfgIfAgc()
581 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) || in SetCfgIfAgc()
582 ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) || in SetCfgIfAgc()
583 ((cfg->speed) > DRXD_FE_CTRL_MAX) || in SetCfgIfAgc()
584 ((cfg->settleLevel) > DRXD_FE_CTRL_MAX) in SetCfgIfAgc()
586 return -1; in SetCfgIfAgc()
606 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) & in SetCfgIfAgc()
614 slope = (u16) ((cfg->maxOutputLevel - in SetCfgIfAgc()
615 cfg->minOutputLevel) / 2); in SetCfgIfAgc()
616 offset = (u16) ((cfg->maxOutputLevel + in SetCfgIfAgc()
617 cfg->minOutputLevel) / 2 - 511); in SetCfgIfAgc()
641 u16 fineSpeed = (u16) (cfg->speed - in SetCfgIfAgc()
642 ((cfg->speed / in SetCfgIfAgc()
645 u16 invRurCount = (u16) (cfg->speed / in SetCfgIfAgc()
652 rurCount = maxRur - invRurCount; in SetCfgIfAgc()
693 return -1; in SetCfgIfAgc()
702 if (cfg->outputLevel > DRXD_FE_CTRL_MAX) in SetCfgRfAgc()
703 return -1; in SetCfgRfAgc()
705 if (cfg->ctrlMode == AGC_CTRL_USER) { in SetCfgRfAgc()
708 u16 level = (cfg->outputLevel); in SetCfgRfAgc()
720 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); in SetCfgRfAgc()
721 state->m_FeAgRegAgPwd |= in SetCfgRfAgc()
723 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in SetCfgRfAgc()
754 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { in SetCfgRfAgc()
761 (state->m_FeAgRegAgPwd) &= in SetCfgRfAgc()
763 (state->m_FeAgRegAgPwd) |= in SetCfgRfAgc()
765 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
780 level = (((cfg->settleLevel) >> 4) & in SetCfgRfAgc()
812 (state->m_FeAgRegAgPwd) &= in SetCfgRfAgc()
814 (state->m_FeAgRegAgPwd) |= in SetCfgRfAgc()
816 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
855 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) { in ReadIFAgc()
864 Vin - R3 - * -- Vout in ReadIFAgc()
870 u32 R1 = state->if_agc_cfg.R1; in ReadIFAgc()
871 u32 R2 = state->if_agc_cfg.R2; in ReadIFAgc()
872 u32 R3 = state->if_agc_cfg.R3; in ReadIFAgc()
882 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024; in ReadIFAgc()
894 if (request_firmware(&fw, fw_name, state->dev) < 0) { in load_firmware()
896 return -EIO; in load_firmware()
899 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL); in load_firmware()
900 if (!state->microcode) { in load_firmware()
902 return -ENOMEM; in load_firmware()
905 state->microcode_length = fw->size; in load_firmware()
964 status = -1; in HI_Command()
979 mutex_lock(&state->mutex); in HI_CfgCommand()
981 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); in HI_CfgCommand()
982 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); in HI_CfgCommand()
983 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); in HI_CfgCommand()
984 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); in HI_CfgCommand()
988 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) == in HI_CfgCommand()
994 mutex_unlock(&state->mutex); in HI_CfgCommand()
1000 state->hi_cfg_wakeup_key = (state->chip_adr); in InitHI()
1002 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; in InitHI()
1010 mutex_lock(&state->mutex); in HI_ResetCommand()
1015 mutex_unlock(&state->mutex); in HI_ResetCommand()
1022 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); in DRX_ConfigureI2CBridge()
1024 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; in DRX_ConfigureI2CBridge()
1026 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; in DRX_ConfigureI2CBridge()
1045 return -1;
1047 mutex_lock(&state->mutex);
1051 /* TODO use proper names forthese egisters */
1061 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1086 mutex_unlock(&state->mutex);
1097 return -1;
1114 if (state->type_A) { in EnableAndResetMB()
1129 if (state->osc_clock_freq == 0 || in InitCC()
1130 state->osc_clock_freq > 20000 || in InitCC()
1131 (state->osc_clock_freq % 4000) != 0) { in InitCC()
1132 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq); in InitCC()
1133 return -1; in InitCC()
1141 state->osc_clock_freq / 4000, 0); in InitCC()
1153 if (state->type_A) in ResetECOD()
1159 status = WriteTable(state, state->m_ResetECRAM); in ResetECOD()
1238 status = WriteTable(state, state->m_InitFE_1); in InitFE()
1242 if (state->type_A) { in InitFE()
1247 if (state->PGA) in InitFE()
1258 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); in InitFE()
1261 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in InitFE()
1265 status = WriteTable(state, state->m_InitFE_2); in InitFE()
1292 return -1; in SC_WaitForReady()
1310 status = -1; in SC_SendCommand()
1322 mutex_lock(&state->mutex); in SC_ProcStartCommand()
1326 status = -1; in SC_ProcStartCommand()
1336 mutex_unlock(&state->mutex); in SC_ProcStartCommand()
1345 mutex_lock(&state->mutex); in SC_SetPrefParamCommand()
1364 mutex_unlock(&state->mutex); in SC_SetPrefParamCommand()
1373 mutex_lock(&state->mutex);
1385 mutex_unlock(&state->mutex);
1402 if (state->operation_mode == OM_DVBT_Diversity_Front) { in ConfigureMPEGOutput()
1411 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; in ConfigureMPEGOutput()
1419 if (state->insert_rs_byte) { in ConfigureMPEGOutput()
1436 if (state->enable_parallel) in ConfigureMPEGOutput()
1495 state->type_A = 0; in SetDeviceTypeId()
1496 state->PGA = 0; in SetDeviceTypeId()
1497 state->diversity = 0; in SetDeviceTypeId()
1499 state->type_A = 1; in SetDeviceTypeId()
1500 printk(KERN_INFO "DRX3975D-A2\n"); in SetDeviceTypeId()
1503 printk(KERN_INFO "DRX397%dD-B1\n", deviceId); in SetDeviceTypeId()
1506 state->diversity = 1; in SetDeviceTypeId()
1510 state->PGA = 1; in SetDeviceTypeId()
1513 state->diversity = 1; in SetDeviceTypeId()
1519 status = -1; in SetDeviceTypeId()
1529 state->m_InitAtomicRead = DRXD_InitAtomicRead; in SetDeviceTypeId()
1530 state->m_InitSC = DRXD_InitSC; in SetDeviceTypeId()
1531 state->m_ResetECRAM = DRXD_ResetECRAM; in SetDeviceTypeId()
1532 if (state->type_A) { in SetDeviceTypeId()
1533 state->m_ResetCEFR = DRXD_ResetCEFR; in SetDeviceTypeId()
1534 state->m_InitFE_1 = DRXD_InitFEA2_1; in SetDeviceTypeId()
1535 state->m_InitFE_2 = DRXD_InitFEA2_2; in SetDeviceTypeId()
1536 state->m_InitCP = DRXD_InitCPA2; in SetDeviceTypeId()
1537 state->m_InitCE = DRXD_InitCEA2; in SetDeviceTypeId()
1538 state->m_InitEQ = DRXD_InitEQA2; in SetDeviceTypeId()
1539 state->m_InitEC = DRXD_InitECA2; in SetDeviceTypeId()
1541 return -EIO; in SetDeviceTypeId()
1543 state->m_ResetCEFR = NULL; in SetDeviceTypeId()
1544 state->m_InitFE_1 = DRXD_InitFEB1_1; in SetDeviceTypeId()
1545 state->m_InitFE_2 = DRXD_InitFEB1_2; in SetDeviceTypeId()
1546 state->m_InitCP = DRXD_InitCPB1; in SetDeviceTypeId()
1547 state->m_InitCE = DRXD_InitCEB1; in SetDeviceTypeId()
1548 state->m_InitEQ = DRXD_InitEQB1; in SetDeviceTypeId()
1549 state->m_InitEC = DRXD_InitECB1; in SetDeviceTypeId()
1551 return -EIO; in SetDeviceTypeId()
1553 if (state->diversity) { in SetDeviceTypeId()
1554 state->m_InitDiversityFront = DRXD_InitDiversityFront; in SetDeviceTypeId()
1555 state->m_InitDiversityEnd = DRXD_InitDiversityEnd; in SetDeviceTypeId()
1556 state->m_DisableDiversity = DRXD_DisableDiversity; in SetDeviceTypeId()
1557 state->m_StartDiversityFront = DRXD_StartDiversityFront; in SetDeviceTypeId()
1558 state->m_StartDiversityEnd = DRXD_StartDiversityEnd; in SetDeviceTypeId()
1559 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; in SetDeviceTypeId()
1560 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; in SetDeviceTypeId()
1562 state->m_InitDiversityFront = NULL; in SetDeviceTypeId()
1563 state->m_InitDiversityEnd = NULL; in SetDeviceTypeId()
1564 state->m_DisableDiversity = NULL; in SetDeviceTypeId()
1565 state->m_StartDiversityFront = NULL; in SetDeviceTypeId()
1566 state->m_StartDiversityEnd = NULL; in SetDeviceTypeId()
1567 state->m_DiversityDelay8MHZ = NULL; in SetDeviceTypeId()
1568 state->m_DiversityDelay6MHZ = NULL; in SetDeviceTypeId()
1597 if (state->type_A) { in CorrectSysClockDeviation()
1598 if ((nomincr - incr < -500) || (nomincr - incr > 500)) in CorrectSysClockDeviation()
1601 if ((nomincr - incr < -2000) || (nomincr - incr > 2000)) in CorrectSysClockDeviation()
1605 switch (state->props.bandwidth_hz) { in CorrectSysClockDeviation()
1616 return -1; in CorrectSysClockDeviation()
1629 oscClockDeviation = (u16) ((((s32) (sysClockFreq) - in CorrectSysClockDeviation()
1631 (state->expected_sys_clock_freq)) * in CorrectSysClockDeviation()
1634 (state->expected_sys_clock_freq)); in CorrectSysClockDeviation()
1636 Diff = oscClockDeviation - state->osc_clock_deviation; in CorrectSysClockDeviation()
1638 if (Diff >= -200 && Diff <= 200) { in CorrectSysClockDeviation()
1639 state->sys_clock_freq = (u16) sysClockFreq; in CorrectSysClockDeviation()
1640 if (oscClockDeviation != state->osc_clock_deviation) { in CorrectSysClockDeviation()
1641 if (state->config.osc_deviation) { in CorrectSysClockDeviation()
1642 state->config.osc_deviation(state->priv, in CorrectSysClockDeviation()
1645 state->osc_clock_deviation = in CorrectSysClockDeviation()
1654 proper re-locking */ in CorrectSysClockDeviation()
1655 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); in CorrectSysClockDeviation()
1658 state->cscd_state = CSCD_SAVED; in CorrectSysClockDeviation()
1669 if (state->drxd_state != DRXD_STARTED) in DRX_Stop()
1673 if (state->cscd_state != CSCD_SAVED) { in DRX_Stop()
1684 state->drxd_state = DRXD_STOPPED; in DRX_Stop()
1690 if (state->type_A) { in DRX_Stop()
1737 if (state->drxd_state != DRXD_STOPPED) {
1738 status = -1;
1742 if (oMode == state->operation_mode) {
1747 if (oMode != OM_Default && !state->diversity) {
1748 status = -1;
1754 status = WriteTable(state, state->m_InitDiversityFront);
1757 status = WriteTable(state, state->m_InitDiversityEnd);
1763 status = WriteTable(state, state->m_DisableDiversity);
1769 state->operation_mode = oMode;
1780 if (state->operation_mode == OM_DVBT_Diversity_Front) { in StartDiversity()
1781 status = WriteTable(state, state->m_StartDiversityFront); in StartDiversity()
1784 } else if (state->operation_mode == OM_DVBT_Diversity_End) { in StartDiversity()
1785 status = WriteTable(state, state->m_StartDiversityEnd); in StartDiversity()
1788 if (state->props.bandwidth_hz == 8000000) { in StartDiversity()
1789 status = WriteTable(state, state->m_DiversityDelay8MHZ); in StartDiversity()
1793 status = WriteTable(state, state->m_DiversityDelay6MHZ); in StartDiversity()
1818 int negativeShift = (state->tuner_mirrors == channelMirrored); in SetFrequencyShift()
1822 * Note: ADC mirroring (aliasing) is implictly handled by limiting in SetFrequencyShift()
1825 * that the ADC is mirroring. in SetFrequencyShift()
1826 * The masking is in fact the aliasing of the ADC) in SetFrequencyShift()
1831 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq + in SetFrequencyShift()
1833 1 << 28, state->sys_clock_freq); in SetFrequencyShift()
1835 state->fe_fs_add_incr &= 0x0FFFFFFFL; in SetFrequencyShift()
1837 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr); in SetFrequencyShift()
1841 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq, in SetFrequencyShift()
1842 1 << 28, state->sys_clock_freq); in SetFrequencyShift()
1844 state->org_fe_fs_add_incr &= 0x0FFFFFFFL; in SetFrequencyShift()
1846 state->org_fe_fs_add_incr = ((1L << 28) - in SetFrequencyShift()
1847 state->org_fe_fs_add_incr); in SetFrequencyShift()
1850 state->fe_fs_add_incr, 0); in SetFrequencyShift()
1863 if (noiseCal->cpOpt) { in SetCfgNoiseCalibration()
1867 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); in SetCfgNoiseCalibration()
1875 if (!state->type_A) { in SetCfgNoiseCalibration()
1876 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); in SetCfgNoiseCalibration()
1879 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); in SetCfgNoiseCalibration()
1890 struct dtv_frontend_properties *p = &state->props; in DRX_Start()
1914 off = (off - 500) / 1000; in DRX_Start()
1919 if (state->drxd_state != DRXD_STOPPED) in DRX_Start()
1920 return -1; in DRX_Start()
1924 if (state->type_A) { in DRX_Start()
1948 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRX_Start()
1951 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRX_Start()
1955 mirrorFreqSpect = (state->props.inversion == INVERSION_ON); in DRX_Start()
1957 switch (p->transmission_mode) { in DRX_Start()
1963 if (state->type_A) { in DRX_Start()
1974 if (state->type_A) { in DRX_Start()
1985 switch (p->guard_interval) { in DRX_Start()
2005 switch (p->hierarchy) { in DRX_Start()
2008 if (state->type_A) { in DRX_Start()
2038 if (state->type_A) { in DRX_Start()
2067 if (state->type_A) { in DRX_Start()
2099 if (state->type_A) { in DRX_Start()
2130 switch (p->modulation) { in DRX_Start()
2136 if (state->type_A) { in DRX_Start()
2169 if (state->type_A) { in DRX_Start()
2203 if (state->type_A) { in DRX_Start()
2252 switch (p->code_rate_HP) { in DRX_Start()
2255 if (state->type_A) in DRX_Start()
2263 if (state->type_A) in DRX_Start()
2268 if (state->type_A) in DRX_Start()
2273 if (state->type_A) in DRX_Start()
2278 if (state->type_A) in DRX_Start()
2292 switch (p->bandwidth_hz) { in DRX_Start()
2294 p->bandwidth_hz = 8000000; in DRX_Start()
2319 status = -EINVAL; in DRX_Start()
2336 if ((p->transmission_mode == TRANSMISSION_MODE_2K) && in DRX_Start()
2337 (p->guard_interval == GUARD_INTERVAL_1_32)) { in DRX_Start()
2349 status = SetCfgNoiseCalibration(state, &state->noise_cal); in DRX_Start()
2353 if (state->cscd_state == CSCD_INIT) { in DRX_Start()
2359 state->cscd_state = CSCD_SET; in DRX_Start()
2363 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) => in DRX_Start()
2364 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */ in DRX_Start()
2365 feIfIncr = MulDiv32(state->sys_clock_freq * 1000, in DRX_Start()
2366 (1ULL << 21), bandwidth) - (1 << 23); in DRX_Start()
2409 if (state->operation_mode != OM_Default) { in DRX_Start()
2415 state->drxd_state = DRXD_STARTED; in DRX_Start()
2441 u32 ulClock = state->config.clock; in CDRXD()
2451 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2452 state->if_agc_cfg.outputLevel = 0; in CDRXD()
2453 state->if_agc_cfg.settleLevel = 140; in CDRXD()
2454 state->if_agc_cfg.minOutputLevel = 0; in CDRXD()
2455 state->if_agc_cfg.maxOutputLevel = 1023; in CDRXD()
2456 state->if_agc_cfg.speed = 904; in CDRXD()
2459 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; in CDRXD()
2460 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel); in CDRXD()
2468 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2469 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel); in CDRXD()
2470 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel); in CDRXD()
2471 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel); in CDRXD()
2472 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed); in CDRXD()
2475 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1); in CDRXD()
2476 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2); in CDRXD()
2477 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3); in CDRXD()
2479 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1); in CDRXD()
2480 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2); in CDRXD()
2481 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3); in CDRXD()
2483 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2486 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; in CDRXD()
2487 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel); in CDRXD()
2495 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2496 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel); in CDRXD()
2497 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel); in CDRXD()
2498 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel); in CDRXD()
2499 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); in CDRXD()
2503 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; in CDRXD()
2506 state->app_env_default = (enum app_env) in CDRXD()
2509 state->app_env_diversity = (enum app_env) in CDRXD()
2514 state->noise_cal.cpOpt = 0; in CDRXD()
2515 state->noise_cal.cpNexpOfs = 40; in CDRXD()
2516 state->noise_cal.tdCal2k = -40; in CDRXD()
2517 state->noise_cal.tdCal8k = -24; in CDRXD()
2520 state->noise_cal.cpOpt = 1; in CDRXD()
2521 state->noise_cal.cpNexpOfs = 0; in CDRXD()
2522 state->noise_cal.tdCal2k = -21; in CDRXD()
2523 state->noise_cal.tdCal8k = -24; in CDRXD()
2525 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop); in CDRXD()
2527 state->chip_adr = (state->config.demod_address << 1) | 1; in CDRXD()
2530 state->m_HiI2cPatch = DRXD_HiI2cPatch_1; in CDRXD()
2533 state->m_HiI2cPatch = DRXD_HiI2cPatch_3; in CDRXD()
2536 state->m_HiI2cPatch = NULL; in CDRXD()
2540 state->intermediate_freq = (u16) (IntermediateFrequency / 1000); in CDRXD()
2542 state->expected_sys_clock_freq = 48000; in CDRXD()
2544 state->sys_clock_freq = 48000; in CDRXD()
2545 state->osc_clock_freq = (u16) ulClock; in CDRXD()
2546 state->osc_clock_deviation = 0; in CDRXD()
2547 state->cscd_state = CSCD_INIT; in CDRXD()
2548 state->drxd_state = DRXD_UNINITIALIZED; in CDRXD()
2550 state->PGA = 0; in CDRXD()
2551 state->type_A = 0; in CDRXD()
2552 state->tuner_mirrors = 0; in CDRXD()
2555 state->insert_rs_byte = state->config.insert_rs_byte; in CDRXD()
2556 state->enable_parallel = (ulSerialMode != 1); in CDRXD()
2561 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) * in CDRXD()
2565 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) * in CDRXD()
2568 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; in CDRXD()
2569 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */ in CDRXD()
2570 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; in CDRXD()
2579 if (state->init_done) in DRXD_init()
2582 CDRXD(state, state->config.IF ? state->config.IF : 36000000); in DRXD_init()
2585 state->operation_mode = OM_Default; in DRXD_init()
2592 if (!state->type_A && state->m_HiI2cPatch) { in DRXD_init()
2593 status = WriteTable(state, state->m_HiI2cPatch); in DRXD_init()
2598 if (state->type_A) { in DRXD_init()
2617 state->osc_clock_deviation = 0; in DRXD_init()
2619 if (state->config.osc_deviation) in DRXD_init()
2620 state->osc_clock_deviation = in DRXD_init()
2621 state->config.osc_deviation(state->priv, 0, 0); in DRXD_init()
2625 s32 devA = (s32) (state->osc_clock_deviation) * in DRXD_init()
2626 (s32) (state->expected_sys_clock_freq); in DRXD_init()
2633 devB = (-2); in DRXD_init()
2635 /* add +1 or -1 */ in DRXD_init()
2639 state->sys_clock_freq = in DRXD_init()
2640 (u16) ((state->expected_sys_clock_freq) + in DRXD_init()
2653 if (state->type_A) { in DRXD_init()
2663 status = DownloadMicrocode(state, state->microcode, state->microcode_length); in DRXD_init()
2668 if (state->PGA) { in DRXD_init()
2669 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; in DRXD_init()
2672 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; in DRXD_init()
2675 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; in DRXD_init()
2699 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRXD_init()
2702 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRXD_init()
2706 state->cscd_state = CSCD_INIT; in DRXD_init()
2730 state->drxd_state = DRXD_STOPPED; in DRXD_init()
2731 state->init_done = 1; in DRXD_init()
2757 struct drxd_state *state = fe->demodulator_priv; in drxd_read_signal_strength()
2759 int res; in drxd_read_signal_strength() local
2761 res = ReadIFAgc(state, &value); in drxd_read_signal_strength()
2762 if (res < 0) in drxd_read_signal_strength()
2765 *strength = 0xffff - (value << 4); in drxd_read_signal_strength()
2771 struct drxd_state *state = fe->demodulator_priv; in drxd_read_status()
2794 struct drxd_state *state = fe->demodulator_priv; in drxd_init()
2801 struct drxd_state *state = fe->demodulator_priv; in drxd_config_i2c()
2803 if (state->config.disable_i2c_gate_ctrl == 1) in drxd_config_i2c()
2812 sets->min_delay_ms = 10000; in drxd_get_tune_settings()
2813 sets->max_drift = 0; in drxd_get_tune_settings()
2814 sets->step_size = 0; in drxd_get_tune_settings()
2838 struct drxd_state *state = fe->demodulator_priv; in drxd_sleep()
2851 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drxd_set_frontend()
2852 struct drxd_state *state = fe->demodulator_priv; in drxd_set_frontend()
2855 state->props = *p; in drxd_set_frontend()
2858 if (fe->ops.tuner_ops.set_params) { in drxd_set_frontend()
2859 fe->ops.tuner_ops.set_params(fe); in drxd_set_frontend()
2860 if (fe->ops.i2c_gate_ctrl) in drxd_set_frontend()
2861 fe->ops.i2c_gate_ctrl(fe, 0); in drxd_set_frontend()
2871 struct drxd_state *state = fe->demodulator_priv; in drxd_release()
2879 .name = "Micronas DRXD DVB-T",
2917 state->ops = drxd_ops; in drxd_attach()
2918 state->dev = dev; in drxd_attach()
2919 state->config = *config; in drxd_attach()
2920 state->i2c = i2c; in drxd_attach()
2921 state->priv = priv; in drxd_attach()
2923 mutex_init(&state->mutex); in drxd_attach()
2928 state->frontend.ops = drxd_ops; in drxd_attach()
2929 state->frontend.demodulator_priv = state; in drxd_attach()
2932 CDRXD(state, state->config.IF ? state->config.IF : 36000000); in drxd_attach()
2935 return &state->frontend; in drxd_attach()