Lines Matching +full:ts +full:- +full:4800
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2006-2007 Micronas
35 0x26, 0x00, /* 0 -> ring.rdy; */
36 0x60, 0x04, /* r0rami.dt -> ring.xba; */
37 0x61, 0x04, /* r0rami.dt -> ring.xad; */
38 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */
40 0x64, 0x04, /* r0rami.dt -> ring.len; */
41 0x65, 0x04, /* r0rami.dt -> ring.ctl; */
42 0x26, 0x00, /* 0 -> ring.rdy; */
43 0x38, 0x00, /* 0 -> jumps.ad; */
56 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */
57 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
58 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
59 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
60 0x23, 0x00, /* &data -> ring.iad; */
61 0x24, 0x00, /* 0 -> ring.len; */
62 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
63 0x26, 0x00, /* 0 -> ring.rdy; */
64 0x42, 0x00, /* &data+1 -> w0ram.ad; */
65 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
66 0x63, 0x00, /* &data+1 -> ring.iad; */
67 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
68 0x26, 0x00, /* 0 -> ring.rdy; */
69 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
70 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
71 0x26, 0x00, /* 0 -> ring.rdy; */
72 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
73 0x23, 0x00, /* &data -> ring.iad; */
74 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
75 0x26, 0x00, /* 0 -> ring.rdy; */
76 0x42, 0x00, /* &data+1 -> w0ram.ad; */
77 0x0F, 0x04, /* r0ram.dt -> and.op; */
78 0x1C, 0x06, /* reg0.dt -> and.tr; */
79 0xCF, 0x04, /* and.rs -> add.op; */
80 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
81 0xD0, 0x04, /* add.rs -> add.tr; */
82 0xC8, 0x04, /* add.rs -> reg0.dt; */
83 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
84 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
85 0x01, 0x00, /* 0 -> w0rami.dt; */
86 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
87 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
88 0x01, 0x00, /* 0 -> w0rami.dt; */
89 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
90 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
91 0x01, 0x00, /* 0 -> w0rami.dt; */
92 0x01, 0x00, /* 0 -> w0rami.dt; */
93 0x01, 0x00, /* 0 -> w0rami.dt; */
94 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
95 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
96 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
97 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
98 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
117 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */
118 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
119 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
120 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
121 0x23, 0x00, /* &data -> ring.iad; */
122 0x24, 0x00, /* 0 -> ring.len; */
123 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
124 0x26, 0x00, /* 0 -> ring.rdy; */
125 0x42, 0x00, /* &data+1 -> w0ram.ad; */
126 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
127 0x63, 0x00, /* &data+1 -> ring.iad; */
128 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
129 0x26, 0x00, /* 0 -> ring.rdy; */
130 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
131 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
132 0x26, 0x00, /* 0 -> ring.rdy; */
133 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
134 0x23, 0x00, /* &data -> ring.iad; */
135 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
136 0x26, 0x00, /* 0 -> ring.rdy; */
137 0x42, 0x00, /* &data+1 -> w0ram.ad; */
138 0x0F, 0x04, /* r0ram.dt -> and.op; */
139 0x1C, 0x06, /* reg0.dt -> and.tr; */
140 0xCF, 0x04, /* and.rs -> add.op; */
141 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
142 0xD0, 0x04, /* add.rs -> add.tr; */
143 0xC8, 0x04, /* add.rs -> reg0.dt; */
144 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
145 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
146 0x01, 0x00, /* 0 -> w0rami.dt; */
147 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
148 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
149 0x01, 0x00, /* 0 -> w0rami.dt; */
150 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
151 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
152 0x01, 0x00, /* 0 -> w0rami.dt; */
153 0x01, 0x00, /* 0 -> w0rami.dt; */
154 0x01, 0x00, /* 0 -> w0rami.dt; */
155 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
156 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
157 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
158 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
159 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
325 /* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
326 /* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
366 …/* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005…
367 /* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
372 /* RF-AGC setup */
486 WR16(EQ_REG_SN_OFFSET__A, (u16) (-7)),
751 WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
752 WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
754 WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
755 WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
758 WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
759 WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
761 WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
762 WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
781 /* End demod *********** combining RF in and diversity in, MPEG TS out **** */
799 WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
800 WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
802 WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
803 WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
806 WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
807 WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
809 WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
810 WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
878 /* End demod, combining RF in and diversity in, MPEG TS out */
891 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50),
892 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50),
893 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50),
894 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 800 - 50),
895 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50),
896 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50),
897 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4800 - 50),
898 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 4000 - 50),
904 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50),
905 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50),
906 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 900 - 50),
907 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 600 - 50),
908 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50),
909 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50),
910 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4500 - 50),
911 WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 3500 - 50),