Lines Matching +full:dac +full:- +full:current +full:- +full:limit +full:- +full:low
2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
52 /*-----------------------------------------------------------------------------
54 ----------------------------------------------------------------------------*/
75 #define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw"
201 /*-----------------------------------------------------------------------------
203 ----------------------------------------------------------------------------*/
205 /*-----------------------------------------------------------------------------
207 ----------------------------------------------------------------------------*/
209 #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
438 #define AUD_VOLUME_DB_MIN -60
486 * x -> lowbyte(x), highbyte(x)
527 /*-----------------------------------------------------------------------------
529 ----------------------------------------------------------------------------*/
580 DRX_STANDARD_UNKNOWN, /* current standard */
626 {-5,
634 {-50,
650 {-160,
662 DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */
775 { /* ATV RF-AGC */
783 4000 /* cut-off current */
785 { /* ATV IF-AGC */
830 (151875 - 0), /* system clock frequency in kHz */
858 0, /* current scan index */
880 { /* current channel (all 0) */
883 DRX_STANDARD_UNKNOWN, /* current standard */
976 /*-----------------------------------------------------------------------------
978 ----------------------------------------------------------------------------*/
995 * struct drxu_code_block_hdr - Structure of the microcode block headers
1010 /*-----------------------------------------------------------------------------
1012 ----------------------------------------------------------------------------*/
1047 * This function is used to avoid floating-point calculations as they may
1050 * frac28 performs an unsigned 28/28 bits division to 32-bit fixed point
1052 * N and D can hold numbers up to width: 28-bits.
1055 * Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999
1057 * N: 0...(1<<28)-1 = 268435454
1058 * D: 0...(1<<28)-1
1059 * Q: 0...(1<<32)-1
1067 R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */ in frac28()
1154 /* computing y in log(x/y) = log(x) - log(y) */ in log1_times100()
1155 if ((x & (((u32) (-1)) << (scale + 1))) == 0) { in log1_times100()
1156 for (k = scale; k > 0; k--) { in log1_times100()
1163 if ((x & (((u32) (-1)) << (scale + 1))) == 0) in log1_times100()
1169 Now x has binary point between bit[scale] and bit[scale-1] in log1_times100()
1176 x &= ((((u32) 1) << scale) - 1); in log1_times100()
1178 i = (u8) (x >> (scale - index_width)); in log1_times100()
1179 /* compute delta (x-a) */ in log1_times100()
1180 d = x & ((((u32) 1) << (scale - index_width)) - 1); in log1_times100()
1183 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width)); in log1_times100()
1198 * \param N nominator 16-bits.
1199 * \param D denominator 32-bits.
1259 -conversion to short address format
1260 -access to audio block
1314 state = r_dev_addr->user_data; in drxbsp_i2c_write_read()
1315 msg[0].addr = r_dev_addr->i2c_addr >> 1; in drxbsp_i2c_write_read()
1322 state = w_dev_addr->user_data; in drxbsp_i2c_write_read()
1323 msg[0].addr = w_dev_addr->i2c_addr >> 1; in drxbsp_i2c_write_read()
1330 state = w_dev_addr->user_data; in drxbsp_i2c_write_read()
1331 msg[0].addr = w_dev_addr->i2c_addr >> 1; in drxbsp_i2c_write_read()
1335 msg[1].addr = r_dev_addr->i2c_addr >> 1; in drxbsp_i2c_write_read()
1342 if (state->i2c == NULL) { in drxbsp_i2c_write_read()
1346 if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { in drxbsp_i2c_write_read()
1348 return -EREMOTEIO; in drxbsp_i2c_write_read()
1355 state = w_dev_addr->user_data; in drxbsp_i2c_write_read()
1357 if (state->i2c == NULL) in drxbsp_i2c_write_read()
1360 msg[0].addr = w_dev_addr->i2c_addr; in drxbsp_i2c_write_read()
1364 msg[1].addr = r_dev_addr->i2c_addr; in drxbsp_i2c_write_read()
1371 w_dev_addr->i2c_addr, state->i2c, w_count, r_count); in drxbsp_i2c_write_read()
1373 if (i2c_transfer(state->i2c, msg, 2) != 2) { in drxbsp_i2c_write_read()
1375 return -EREMOTEIO; in drxbsp_i2c_write_read()
1386 * struct i2c_device_addr *dev_addr, -- address of I2C device
1387 * u32 addr, -- address of chip register/memory
1388 * u16 datasize, -- number of bytes to read
1389 * u8 *data, -- data to receive
1390 * u32 flags) -- special device flags
1402 * - 0 if reading was successful
1404 * - -EIO if anything went wrong
1420 return -EINVAL; in drxdap_fasi_read_block()
1422 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + in drxdap_fasi_read_block()
1430 return -EINVAL; in drxdap_fasi_read_block()
1487 datasize -= todo; in drxdap_fasi_read_block()
1497 * struct i2c_device_addr *dev_addr, -- address of I2C device
1498 * u32 addr, -- address of chip register/memory
1499 * u16 *data, -- data to receive
1500 * u32 flags) -- special device flags
1502 * Read one 16-bit register or memory location. The data received back is
1506 * - 0 if reading was successful
1508 * - -EIO if anything went wrong
1520 return -EINVAL; in drxdap_fasi_read_reg16()
1530 * struct i2c_device_addr *dev_addr, -- address of I2C device
1531 * u32 addr, -- address of chip register/memory
1532 * u32 *data, -- data to receive
1533 * u32 flags) -- special device flags
1535 * Read one 32-bit register or memory location. The data received back is
1539 * - 0 if reading was successful
1541 * - -EIO if anything went wrong
1553 return -EINVAL; in drxdap_fasi_read_reg32()
1565 * struct i2c_device_addr *dev_addr, -- address of I2C device
1566 * u32 addr, -- address of chip register/memory
1567 * u16 datasize, -- number of bytes to read
1568 * u8 *data, -- data to receive
1569 * u32 flags) -- special device flags
1579 * - 0 if writing was successful
1580 * - -EIO if anything went wrong
1590 int st = -EIO; in drxdap_fasi_write_block()
1597 return -EINVAL; in drxdap_fasi_write_block()
1599 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + in drxdap_fasi_write_block()
1607 return -EINVAL; in drxdap_fasi_write_block()
1616 block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1; in drxdap_fasi_write_block()
1661 (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1); in drxdap_fasi_write_block()
1663 (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1; in drxdap_fasi_write_block()
1691 datasize -= todo; in drxdap_fasi_write_block()
1702 * struct i2c_device_addr *dev_addr, -- address of I2C device
1703 * u32 addr, -- address of chip register/memory
1704 * u16 data, -- data to send
1705 * u32 flags) -- special device flags
1707 * Write one 16-bit register or memory location. The data being written is
1711 * - 0 if writing was successful
1712 * - -EIO if anything went wrong
1731 * struct i2c_device_addr *dev_addr, -- address of I2C device
1732 * u32 waddr, -- address of chip register/memory
1733 * u32 raddr, -- chip address to read back from
1734 * u16 wdata, -- data to send
1735 * u16 *rdata) -- data to receive back
1737 * Write 16-bit data, then read back the original contents of that location.
1747 * - 0 if reading was successful
1749 * - -EIO if anything went wrong
1758 int rc = -EIO; in drxdap_fasi_read_modify_write_reg16()
1762 return -EINVAL; in drxdap_fasi_read_modify_write_reg16()
1775 * struct i2c_device_addr *dev_addr, -- address of I2C device
1776 * u32 addr, -- address of chip register/memory
1777 * u32 data, -- data to send
1778 * u32 flags) -- special device flags
1780 * Write one 32-bit register or memory location. The data being written is
1784 * - 0 if writing was successful
1785 * - -EIO if anything went wrong
1815 * \retval -EIO Timeout, I2C error, illegal bank
1834 return -EINVAL; in drxj_dap_rm_write_reg16short()
1892 * \retval -EIO Timeout, I2C error, illegal bank
1904 int stat = -EIO; in drxj_dap_read_aud_reg16()
1908 stat = -EINVAL; in drxj_dap_read_aud_reg16()
1928 delta_timer = current_timer - start_timer; in drxj_dap_read_aud_reg16()
1930 stat = -EIO; in drxj_dap_read_aud_reg16()
1953 delta_timer = current_timer - start_timer; in drxj_dap_read_aud_reg16()
1955 stat = -EIO; in drxj_dap_read_aud_reg16()
1976 int stat = -EIO; in drxj_dap_read_reg16()
1980 return -EINVAL; in drxj_dap_read_reg16()
1999 * \retval -EIO Timeout, I2C error, illegal bank
2007 int stat = -EIO; in drxj_dap_write_aud_reg16()
2011 stat = -EINVAL; in drxj_dap_write_aud_reg16()
2032 delta_timer = current_timer - start_timer; in drxj_dap_write_aud_reg16()
2034 stat = -EIO; in drxj_dap_write_aud_reg16()
2054 int stat = -EIO; in drxj_dap_write_reg16()
2058 return -EINVAL; in drxj_dap_write_reg16()
2089 * \retval -EIO Timeout, I2C error, illegal bank
2106 return -EINVAL; in drxj_dap_atomic_read_write_block()
2115 hi_cmd.param3 = (u16) ((datasize / 2) - 1); in drxj_dap_atomic_read_write_block()
2180 return -EINVAL; in drxj_dap_atomic_read_reg32()
2221 * enable/disable should not need re-configuration of the HI.
2231 ext_attr = (struct drxj_data *) demod->my_ext_attr; in hi_cfg_command()
2235 hi_cmd.param2 = ext_attr->hi_cfg_timing_div; in hi_cfg_command()
2236 hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay; in hi_cfg_command()
2237 hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key; in hi_cfg_command()
2238 hi_cmd.param5 = ext_attr->hi_cfg_ctrl; in hi_cfg_command()
2239 hi_cmd.param6 = ext_attr->hi_cfg_transmit; in hi_cfg_command()
2241 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); in hi_cfg_command()
2248 ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); in hi_cfg_command()
2276 switch (cmd->cmd) { in hi_command()
2280 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0); in hi_command()
2285 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0); in hi_command()
2290 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0); in hi_command()
2295 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0); in hi_command()
2302 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0); in hi_command()
2307 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0); in hi_command()
2318 return -EINVAL; in hi_command()
2322 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0); in hi_command()
2328 if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET) in hi_command()
2332 powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) && in hi_command()
2333 (((cmd-> in hi_command()
2341 rc = -ETIMEDOUT; in hi_command()
2373 * \retval -EIO Failure.
2387 ext_attr = (struct drxj_data *) demod->my_ext_attr; in init_hi()
2388 common_attr = (struct drx_common_attr *) demod->my_common_attr; in init_hi()
2389 dev_addr = demod->my_i2c_dev_addr; in init_hi()
2400 ext_attr->hi_cfg_timing_div = in init_hi()
2401 (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000; in init_hi()
2403 if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) in init_hi()
2404 ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; in init_hi()
2408 ext_attr->hi_cfg_bridge_delay = in init_hi()
2409 (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) / in init_hi()
2412 if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) in init_hi()
2413 ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; in init_hi()
2415 ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) << in init_hi()
2420 ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY; in init_hi()
2422 ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE); in init_hi()
2424 ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE; in init_hi()
2454 * \retval -EIO Failure
2457 * * common_attr->osc_clock_freq
2458 * * ext_attr->has_lna
2459 * * ext_attr->has_ntsc
2460 * * ext_attr->has_btsc
2461 * * ext_attr->has_oob
2474 common_attr = (struct drx_common_attr *) demod->my_common_attr; in get_device_capabilities()
2475 ext_attr = (struct drxj_data *) demod->my_ext_attr; in get_device_capabilities()
2476 dev_addr = demod->my_i2c_dev_addr; in get_device_capabilities()
2500 common_attr->osc_clock_freq = 27000; in get_device_capabilities()
2504 common_attr->osc_clock_freq = 20250; in get_device_capabilities()
2508 common_attr->osc_clock_freq = 4000; in get_device_capabilities()
2511 return -EIO; in get_device_capabilities()
2523 ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF); in get_device_capabilities()
2544 ext_attr->has_lna = true; in get_device_capabilities()
2545 ext_attr->has_ntsc = false; in get_device_capabilities()
2546 ext_attr->has_btsc = false; in get_device_capabilities()
2547 ext_attr->has_oob = false; in get_device_capabilities()
2548 ext_attr->has_smatx = true; in get_device_capabilities()
2549 ext_attr->has_smarx = false; in get_device_capabilities()
2550 ext_attr->has_gpio = false; in get_device_capabilities()
2551 ext_attr->has_irqn = false; in get_device_capabilities()
2554 ext_attr->has_lna = false; in get_device_capabilities()
2555 ext_attr->has_ntsc = false; in get_device_capabilities()
2556 ext_attr->has_btsc = false; in get_device_capabilities()
2557 ext_attr->has_oob = false; in get_device_capabilities()
2558 ext_attr->has_smatx = true; in get_device_capabilities()
2559 ext_attr->has_smarx = false; in get_device_capabilities()
2560 ext_attr->has_gpio = false; in get_device_capabilities()
2561 ext_attr->has_irqn = false; in get_device_capabilities()
2564 ext_attr->has_lna = true; in get_device_capabilities()
2565 ext_attr->has_ntsc = true; in get_device_capabilities()
2566 ext_attr->has_btsc = false; in get_device_capabilities()
2567 ext_attr->has_oob = false; in get_device_capabilities()
2568 ext_attr->has_smatx = true; in get_device_capabilities()
2569 ext_attr->has_smarx = true; in get_device_capabilities()
2570 ext_attr->has_gpio = true; in get_device_capabilities()
2571 ext_attr->has_irqn = false; in get_device_capabilities()
2574 ext_attr->has_lna = false; in get_device_capabilities()
2575 ext_attr->has_ntsc = true; in get_device_capabilities()
2576 ext_attr->has_btsc = false; in get_device_capabilities()
2577 ext_attr->has_oob = false; in get_device_capabilities()
2578 ext_attr->has_smatx = true; in get_device_capabilities()
2579 ext_attr->has_smarx = true; in get_device_capabilities()
2580 ext_attr->has_gpio = true; in get_device_capabilities()
2581 ext_attr->has_irqn = false; in get_device_capabilities()
2584 ext_attr->has_lna = true; in get_device_capabilities()
2585 ext_attr->has_ntsc = true; in get_device_capabilities()
2586 ext_attr->has_btsc = true; in get_device_capabilities()
2587 ext_attr->has_oob = false; in get_device_capabilities()
2588 ext_attr->has_smatx = true; in get_device_capabilities()
2589 ext_attr->has_smarx = true; in get_device_capabilities()
2590 ext_attr->has_gpio = true; in get_device_capabilities()
2591 ext_attr->has_irqn = false; in get_device_capabilities()
2594 ext_attr->has_lna = false; in get_device_capabilities()
2595 ext_attr->has_ntsc = true; in get_device_capabilities()
2596 ext_attr->has_btsc = true; in get_device_capabilities()
2597 ext_attr->has_oob = false; in get_device_capabilities()
2598 ext_attr->has_smatx = true; in get_device_capabilities()
2599 ext_attr->has_smarx = true; in get_device_capabilities()
2600 ext_attr->has_gpio = true; in get_device_capabilities()
2601 ext_attr->has_irqn = false; in get_device_capabilities()
2604 ext_attr->has_lna = true; in get_device_capabilities()
2605 ext_attr->has_ntsc = false; in get_device_capabilities()
2606 ext_attr->has_btsc = false; in get_device_capabilities()
2607 ext_attr->has_oob = true; in get_device_capabilities()
2608 ext_attr->has_smatx = true; in get_device_capabilities()
2609 ext_attr->has_smarx = true; in get_device_capabilities()
2610 ext_attr->has_gpio = true; in get_device_capabilities()
2611 ext_attr->has_irqn = true; in get_device_capabilities()
2614 ext_attr->has_lna = false; in get_device_capabilities()
2615 ext_attr->has_ntsc = true; in get_device_capabilities()
2616 ext_attr->has_btsc = true; in get_device_capabilities()
2617 ext_attr->has_oob = true; in get_device_capabilities()
2618 ext_attr->has_smatx = true; in get_device_capabilities()
2619 ext_attr->has_smarx = true; in get_device_capabilities()
2620 ext_attr->has_gpio = true; in get_device_capabilities()
2621 ext_attr->has_irqn = true; in get_device_capabilities()
2624 ext_attr->has_lna = true; in get_device_capabilities()
2625 ext_attr->has_ntsc = true; in get_device_capabilities()
2626 ext_attr->has_btsc = true; in get_device_capabilities()
2627 ext_attr->has_oob = true; in get_device_capabilities()
2628 ext_attr->has_smatx = true; in get_device_capabilities()
2629 ext_attr->has_smarx = true; in get_device_capabilities()
2630 ext_attr->has_gpio = true; in get_device_capabilities()
2631 ext_attr->has_irqn = true; in get_device_capabilities()
2634 ext_attr->has_lna = false; in get_device_capabilities()
2635 ext_attr->has_ntsc = true; in get_device_capabilities()
2636 ext_attr->has_btsc = true; in get_device_capabilities()
2637 ext_attr->has_oob = true; in get_device_capabilities()
2638 ext_attr->has_smatx = true; in get_device_capabilities()
2639 ext_attr->has_smarx = true; in get_device_capabilities()
2640 ext_attr->has_gpio = true; in get_device_capabilities()
2641 ext_attr->has_irqn = true; in get_device_capabilities()
2645 return -EIO; in get_device_capabilities()
2660 * \retval -EIO Failure, I2C or max retries reached
2675 dev_addr = demod->my_i2c_dev_addr; in power_up_device()
2677 wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id; in power_up_device()
2678 wake_up_addr.user_data = dev_addr->user_data; in power_up_device()
2700 return -EIO; in power_up_device()
2705 /*----------------------------------------------------------------------------*/
2706 /* MPEG Output Configuration Functions - begin */
2707 /*----------------------------------------------------------------------------*/
2741 return -EINVAL; in ctrl_set_cfg_mpeg_output()
2743 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_cfg_mpeg_output()
2744 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_cfg_mpeg_output()
2745 common_attr = (struct drx_common_attr *) demod->my_common_attr; in ctrl_set_cfg_mpeg_output()
2747 if (cfg_data->enable_mpeg_output == true) { in ctrl_set_cfg_mpeg_output()
2748 /* quick and dirty patch to set MPEG in case current std is not in ctrl_set_cfg_mpeg_output()
2750 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
2765 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
2797 /* Low Water Mark for synchronization */ in ctrl_set_cfg_mpeg_output()
2812 switch (ext_attr->constellation) { in ctrl_set_cfg_mpeg_output()
2829 return -EIO; in ctrl_set_cfg_mpeg_output()
2830 } /* ext_attr->constellation */ in ctrl_set_cfg_mpeg_output()
2834 (ext_attr->curr_symbol_rate / 8) * nr_bits * 188; in ctrl_set_cfg_mpeg_output()
2862 if (cfg_data->static_clk == true) { in ctrl_set_cfg_mpeg_output()
2890 /* Check insertion of the Reed-Solomon parity bytes */ in ctrl_set_cfg_mpeg_output()
2901 if (cfg_data->insert_rs_byte == true) { in ctrl_set_cfg_mpeg_output()
2906 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
2912 switch (ext_attr->constellation) { in ctrl_set_cfg_mpeg_output()
2920 return -EIO; in ctrl_set_cfg_mpeg_output()
2925 /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */ in ctrl_set_cfg_mpeg_output()
2929 (u32) (common_attr->sys_clock_freq / 8))) / in ctrl_set_cfg_mpeg_output()
2933 return -EIO; in ctrl_set_cfg_mpeg_output()
2934 } /* ext_attr->standard */ in ctrl_set_cfg_mpeg_output()
2941 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
2947 switch (ext_attr->constellation) { in ctrl_set_cfg_mpeg_output()
2955 return -EIO; in ctrl_set_cfg_mpeg_output()
2960 /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */ in ctrl_set_cfg_mpeg_output()
2964 (u32) (common_attr->sys_clock_freq / 8))) / in ctrl_set_cfg_mpeg_output()
2968 return -EIO; in ctrl_set_cfg_mpeg_output()
2969 } /* ext_attr->standard */ in ctrl_set_cfg_mpeg_output()
2972 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> clear ipr_mode[0] */ in ctrl_set_cfg_mpeg_output()
2974 } else { /* MPEG data output is serial -> set ipr_mode[0] */ in ctrl_set_cfg_mpeg_output()
2979 if (cfg_data->invert_data == true) in ctrl_set_cfg_mpeg_output()
2984 if (cfg_data->invert_err == true) in ctrl_set_cfg_mpeg_output()
2989 if (cfg_data->invert_str == true) in ctrl_set_cfg_mpeg_output()
2994 if (cfg_data->invert_val == true) in ctrl_set_cfg_mpeg_output()
2999 if (cfg_data->invert_clk == true) in ctrl_set_cfg_mpeg_output()
3005 if (cfg_data->static_clk == true) { /* Static mode */ in ctrl_set_cfg_mpeg_output()
3013 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
3016 if (cfg_data->insert_rs_byte == true) in ctrl_set_cfg_mpeg_output()
3022 if (cfg_data->insert_rs_byte == true) { in ctrl_set_cfg_mpeg_output()
3026 if (ext_attr->curr_symbol_rate >= in ctrl_set_cfg_mpeg_output()
3036 if (cfg_data->insert_rs_byte == true) in ctrl_set_cfg_mpeg_output()
3041 if (cfg_data->insert_rs_byte == true) in ctrl_set_cfg_mpeg_output()
3045 return -EIO; in ctrl_set_cfg_mpeg_output()
3048 common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period + in ctrl_set_cfg_mpeg_output()
3051 frac28(bit_rate, common_attr->sys_clock_freq * 1000); in ctrl_set_cfg_mpeg_output()
3078 if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) in ctrl_set_cfg_mpeg_output()
3079 fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1; in ctrl_set_cfg_mpeg_output()
3158 …if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> set MD1 to MD7 to outp… in ctrl_set_cfg_mpeg_output()
3203 } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ in ctrl_set_cfg_mpeg_output()
3334 /* save values for restore after re-acquire */ in ctrl_set_cfg_mpeg_output()
3335 common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output; in ctrl_set_cfg_mpeg_output()
3342 /*----------------------------------------------------------------------------*/
3345 /*----------------------------------------------------------------------------*/
3346 /* MPEG Output Configuration Functions - end */
3347 /*----------------------------------------------------------------------------*/
3349 /*----------------------------------------------------------------------------*/
3350 /* miscellaneous configurations - begin */
3351 /*----------------------------------------------------------------------------*/
3371 dev_addr = demod->my_i2c_dev_addr; in set_mpegtei_handling()
3372 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_mpegtei_handling()
3396 if (ext_attr->disable_te_ihandling) { in set_mpegtei_handling()
3425 /*----------------------------------------------------------------------------*/
3428 * \brief Set MPEG output bit-endian settings.
3442 dev_addr = demod->my_i2c_dev_addr; in bit_reverse_mpeg_output()
3443 ext_attr = (struct drxj_data *) demod->my_ext_attr; in bit_reverse_mpeg_output()
3454 if (ext_attr->bit_reverse_mpeg_outout) in bit_reverse_mpeg_output()
3468 /*----------------------------------------------------------------------------*/
3486 dev_addr = demod->my_i2c_dev_addr; in set_mpeg_start_width()
3487 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_mpeg_start_width()
3488 common_attr = demod->my_common_attr; in set_mpeg_start_width()
3490 if ((common_attr->mpeg_cfg.static_clk == true) in set_mpeg_start_width()
3491 && (common_attr->mpeg_cfg.enable_parallel == false)) { in set_mpeg_start_width()
3498 if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC) in set_mpeg_start_width()
3512 /*----------------------------------------------------------------------------*/
3513 /* miscellaneous configurations - end */
3514 /*----------------------------------------------------------------------------*/
3516 /*----------------------------------------------------------------------------*/
3517 /* UIO Configuration Functions - begin */
3518 /*----------------------------------------------------------------------------*/
3532 return -EINVAL; in ctrl_set_uio_cfg()
3534 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_uio_cfg()
3537 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in ctrl_set_uio_cfg()
3542 switch (uio_cfg->uio) { in ctrl_set_uio_cfg()
3545 /* DRX_UIO1: SMA_TX UIO-1 */ in ctrl_set_uio_cfg()
3546 if (!ext_attr->has_smatx) in ctrl_set_uio_cfg()
3547 return -EIO; in ctrl_set_uio_cfg()
3548 switch (uio_cfg->mode) { in ctrl_set_uio_cfg()
3552 ext_attr->uio_sma_tx_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3555 ext_attr->uio_sma_tx_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3556 /* pad configuration register is set 0 - input mode */ in ctrl_set_uio_cfg()
3557 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3564 return -EINVAL; in ctrl_set_uio_cfg()
3565 } /* switch ( uio_cfg->mode ) */ in ctrl_set_uio_cfg()
3569 /* DRX_UIO2: SMA_RX UIO-2 */ in ctrl_set_uio_cfg()
3570 if (!ext_attr->has_smarx) in ctrl_set_uio_cfg()
3571 return -EIO; in ctrl_set_uio_cfg()
3572 switch (uio_cfg->mode) { in ctrl_set_uio_cfg()
3575 ext_attr->uio_sma_rx_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3578 ext_attr->uio_sma_rx_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3579 /* pad configuration register is set 0 - input mode */ in ctrl_set_uio_cfg()
3580 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3587 return -EINVAL; in ctrl_set_uio_cfg()
3588 } /* switch ( uio_cfg->mode ) */ in ctrl_set_uio_cfg()
3592 /* DRX_UIO3: GPIO UIO-3 */ in ctrl_set_uio_cfg()
3593 if (!ext_attr->has_gpio) in ctrl_set_uio_cfg()
3594 return -EIO; in ctrl_set_uio_cfg()
3595 switch (uio_cfg->mode) { in ctrl_set_uio_cfg()
3598 ext_attr->uio_gpio_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3601 ext_attr->uio_gpio_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3602 /* pad configuration register is set 0 - input mode */ in ctrl_set_uio_cfg()
3603 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3610 return -EINVAL; in ctrl_set_uio_cfg()
3611 } /* switch ( uio_cfg->mode ) */ in ctrl_set_uio_cfg()
3615 /* DRX_UIO4: IRQN UIO-4 */ in ctrl_set_uio_cfg()
3616 if (!ext_attr->has_irqn) in ctrl_set_uio_cfg()
3617 return -EIO; in ctrl_set_uio_cfg()
3618 switch (uio_cfg->mode) { in ctrl_set_uio_cfg()
3620 ext_attr->uio_irqn_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3623 /* pad configuration register is set 0 - input mode */ in ctrl_set_uio_cfg()
3624 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3629 ext_attr->uio_irqn_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3633 return -EINVAL; in ctrl_set_uio_cfg()
3634 } /* switch ( uio_cfg->mode ) */ in ctrl_set_uio_cfg()
3638 return -EINVAL; in ctrl_set_uio_cfg()
3639 } /* switch ( uio_cfg->uio ) */ in ctrl_set_uio_cfg()
3642 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_uio_cfg()
3669 return -EINVAL; in ctrl_uio_write()
3671 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_uio_write()
3674 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in ctrl_uio_write()
3679 switch (uio_data->uio) { in ctrl_uio_write()
3682 /* DRX_UIO1: SMA_TX UIO-1 */ in ctrl_uio_write()
3683 if (!ext_attr->has_smatx) in ctrl_uio_write()
3684 return -EIO; in ctrl_uio_write()
3685 if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) in ctrl_uio_write()
3686 && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) { in ctrl_uio_write()
3687 return -EIO; in ctrl_uio_write()
3695 /* write to io pad configuration register - output mode */ in ctrl_uio_write()
3696 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3703 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3708 if (!uio_data->value) in ctrl_uio_write()
3709 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ in ctrl_uio_write()
3711 value |= 0x8000; /* write one to 15th bit - 1st UIO */ in ctrl_uio_write()
3714 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3722 /* DRX_UIO2: SMA_RX UIO-2 */ in ctrl_uio_write()
3723 if (!ext_attr->has_smarx) in ctrl_uio_write()
3724 return -EIO; in ctrl_uio_write()
3725 if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) in ctrl_uio_write()
3726 return -EIO; in ctrl_uio_write()
3734 /* write to io pad configuration register - output mode */ in ctrl_uio_write()
3735 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3742 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3747 if (!uio_data->value) in ctrl_uio_write()
3748 value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ in ctrl_uio_write()
3750 value |= 0x4000; /* write one to 14th bit - 2nd UIO */ in ctrl_uio_write()
3753 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3761 /* DRX_UIO3: ASEL UIO-3 */ in ctrl_uio_write()
3762 if (!ext_attr->has_gpio) in ctrl_uio_write()
3763 return -EIO; in ctrl_uio_write()
3764 if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) in ctrl_uio_write()
3765 return -EIO; in ctrl_uio_write()
3773 /* write to io pad configuration register - output mode */ in ctrl_uio_write()
3774 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3781 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0); in ctrl_uio_write()
3786 if (!uio_data->value) in ctrl_uio_write()
3787 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ in ctrl_uio_write()
3789 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ in ctrl_uio_write()
3792 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); in ctrl_uio_write()
3800 /* DRX_UIO4: IRQN UIO-4 */ in ctrl_uio_write()
3801 if (!ext_attr->has_irqn) in ctrl_uio_write()
3802 return -EIO; in ctrl_uio_write()
3804 if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) in ctrl_uio_write()
3805 return -EIO; in ctrl_uio_write()
3813 /* write to io pad configuration register - output mode */ in ctrl_uio_write()
3814 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3821 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3826 if (uio_data->value == false) in ctrl_uio_write()
3827 value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ in ctrl_uio_write()
3829 value |= 0x1000; /* write one to 12th bit - 4th UIO */ in ctrl_uio_write()
3832 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3840 return -EINVAL; in ctrl_uio_write()
3841 } /* switch ( uio_data->uio ) */ in ctrl_uio_write()
3844 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_uio_write()
3855 /*---------------------------------------------------------------------------*/
3856 /* UIO Configuration Functions - end */
3857 /*---------------------------------------------------------------------------*/
3859 /*----------------------------------------------------------------------------*/
3860 /* I2C Bridge Functions - begin */
3861 /*----------------------------------------------------------------------------*/
3878 return -EINVAL; in ctrl_i2c_bridge()
3887 return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); in ctrl_i2c_bridge()
3890 /*----------------------------------------------------------------------------*/
3891 /* I2C Bridge Functions - end */
3892 /*----------------------------------------------------------------------------*/
3894 /*----------------------------------------------------------------------------*/
3895 /* Smart antenna Functions - begin */
3896 /*----------------------------------------------------------------------------*/
3912 dev_addr = demod->my_i2c_dev_addr; in smart_ant_init()
3913 ext_attr = (struct drxj_data *) demod->my_ext_attr; in smart_ant_init()
3916 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in smart_ant_init()
3927 if (ext_attr->smart_ant_inverted) { in smart_ant_init()
3947 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0); in smart_ant_init()
3952 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0); in smart_ant_init()
3959 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in smart_ant_init()
3978 return -EINVAL; in scu_command()
3987 return -EIO; in scu_command()
3989 switch (cmd->parameter_len) { in scu_command()
3991 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0); in scu_command()
3998 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0); in scu_command()
4005 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0); in scu_command()
4012 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0); in scu_command()
4019 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0); in scu_command()
4030 return -EIO; in scu_command()
4032 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); in scu_command()
4052 return -EIO; in scu_command()
4055 if ((cmd->result_len > 0) && (cmd->result != NULL)) { in scu_command()
4058 switch (cmd->result_len) { in scu_command()
4060 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0); in scu_command()
4067 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0); in scu_command()
4074 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0); in scu_command()
4081 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0); in scu_command()
4092 return -EIO; in scu_command()
4096 err = cmd->result[0]; in scu_command()
4104 return -EINVAL; in scu_command()
4108 return -EIO; in scu_command()
4128 * \retval -EIO Timeout, I2C error, illegal bank
4131 #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
4133 …evice_addr *dev_addr, u32 addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */ in drxj_dap_scu_atomic_read_write_block()
4143 return -EINVAL; in drxj_dap_scu_atomic_read_write_block()
4205 return -EINVAL; in drxj_dap_scu_atomic_read_reg16()
4239 /* -------------------------------------------------------------------------- */
4246 * \retval -EIO Failure: I2C error
4255 dev_addr = demod->my_i2c_dev_addr; in adc_sync_measurement()
4305 * \retval -EIO Failure: I2C error or failure to synchronize
4318 dev_addr = demod->my_i2c_dev_addr; in adc_synchronization()
4352 return -EIO; in adc_synchronization()
4399 dev_addr = demod->my_i2c_dev_addr; in init_agc()
4400 common_attr = (struct drx_common_attr *) demod->my_common_attr; in init_agc()
4401 ext_attr = (struct drxj_data *) demod->my_ext_attr; in init_agc()
4403 switch (ext_attr->standard) { in init_agc()
4406 clp_dir_to = (u16) (-9); in init_agc()
4408 sns_dir_to = (u16) (-9); in init_agc()
4409 ki_innergain_min = (u16) (-32768); in init_agc()
4481 p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg); in init_agc()
4482 p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg); in init_agc()
4490 clp_dir_to = (u16) (-5); in init_agc()
4492 sns_dir_to = (u16) (-3); in init_agc()
4549 p_agc_if_settings = &(ext_attr->qam_if_agc_cfg); in init_agc()
4550 p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg); in init_agc()
4551 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); in init_agc()
4571 return -EINVAL; in init_agc()
4575 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0); in init_agc()
4580 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0); in init_agc()
4599 } /* set to p_agc_settings->top before */ in init_agc()
4706 agc_rf = 0x800 + p_agc_rf_settings->cut_off_current; in init_agc()
4707 if (common_attr->tuner_rf_agc_pol == true) in init_agc()
4708 agc_rf = 0x87ff - agc_rf; in init_agc()
4711 if (common_attr->tuner_if_agc_pol == true) in init_agc()
4712 agc_rf = 0x87ff - agc_rf; in init_agc()
4756 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_frequency()
4757 struct drxj_data *ext_attr = demod->my_ext_attr; in set_frequency()
4762 s32 rf_freq_residual = -1 * tuner_freq_offset; in set_frequency()
4773 rf_mirror = ext_attr->mirror == DRX_MIRROR_YES; in set_frequency()
4774 tuner_mirror = !demod->my_common_attr->mirror_freq_spect; in set_frequency()
4779 switch (ext_attr->standard) { in set_frequency()
4801 return -EINVAL; in set_frequency()
4803 intermediate_freq = demod->my_common_attr->intermediate_freq; in set_frequency()
4804 sampling_frequency = demod->my_common_attr->sys_clock_freq / 3; in set_frequency()
4808 if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift; in set_frequency()
4811 adc_freq = sampling_frequency - if_freq_actual; in set_frequency()
4834 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; in set_frequency()
4835 ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image); in set_frequency()
4849 * \retval -EINVAL sig_strength is NULL.
4850 * \retval -EIO Erroneous data, sig_strength contains invalid data.
4862 ext_attr = (struct drxj_data *) demod->my_ext_attr; in get_acc_pkt_err()
4863 dev_addr = demod->my_i2c_dev_addr; in get_acc_pkt_err()
4870 if (ext_attr->reset_pkt_err_acc) { in get_acc_pkt_err()
4873 ext_attr->reset_pkt_err_acc = false; in get_acc_pkt_err()
4877 pkt_err += 0xffff - last_pkt_err; in get_acc_pkt_err()
4880 pkt_err += (data - last_pkt_err); in get_acc_pkt_err()
4912 common_attr = (struct drx_common_attr *) demod->my_common_attr; in set_agc_rf()
4913 dev_addr = demod->my_i2c_dev_addr; in set_agc_rf()
4914 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_agc_rf()
4925 if ((ext_attr->standard == agc_settings->standard) || in set_agc_rf()
4926 (DRXJ_ISQAMSTD(ext_attr->standard) && in set_agc_rf()
4927 DRXJ_ISQAMSTD(agc_settings->standard)) || in set_agc_rf()
4928 (DRXJ_ISATVSTD(ext_attr->standard) && in set_agc_rf()
4929 DRXJ_ISATVSTD(agc_settings->standard))) { in set_agc_rf()
4932 switch (agc_settings->ctrl_mode) { in set_agc_rf()
4935 /* Enable RF AGC DAC */ in set_agc_rf()
4955 if (ext_attr->standard == DRX_STANDARD_8VSB) in set_agc_rf()
4957 else if (DRXJ_ISQAMSTD(ext_attr->standard)) in set_agc_rf()
4962 if (common_attr->tuner_rf_agc_pol) in set_agc_rf()
4979 …rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAG… in set_agc_rf()
4985 if (agc_settings->standard == DRX_STANDARD_8VSB) in set_agc_rf()
4986 p_agc_settings = &(ext_attr->vsb_if_agc_cfg); in set_agc_rf()
4987 else if (DRXJ_ISQAMSTD(agc_settings->standard)) in set_agc_rf()
4988 p_agc_settings = &(ext_attr->qam_if_agc_cfg); in set_agc_rf()
4989 else if (DRXJ_ISATVSTD(agc_settings->standard)) in set_agc_rf()
4990 p_agc_settings = &(ext_attr->atv_if_agc_cfg); in set_agc_rf()
4992 return -EINVAL; in set_agc_rf()
4994 /* Set TOP, only if IF-AGC is in AUTO mode */ in set_agc_rf()
4995 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { in set_agc_rf()
4996 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0); in set_agc_rf()
5001 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0); in set_agc_rf()
5008 /* Cut-Off current */ in set_agc_rf()
5009 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0); in set_agc_rf()
5017 /* Enable RF AGC DAC */ in set_agc_rf()
5037 if (common_attr->tuner_rf_agc_pol) in set_agc_rf()
5048 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0); in set_agc_rf()
5056 /* Disable RF AGC DAC */ in set_agc_rf()
5083 return -EINVAL; in set_agc_rf()
5084 } /* switch ( agcsettings->ctrl_mode ) */ in set_agc_rf()
5088 switch (agc_settings->standard) { in set_agc_rf()
5090 ext_attr->vsb_rf_agc_cfg = *agc_settings; in set_agc_rf()
5096 ext_attr->qam_rf_agc_cfg = *agc_settings; in set_agc_rf()
5100 return -EIO; in set_agc_rf()
5126 common_attr = (struct drx_common_attr *) demod->my_common_attr; in set_agc_if()
5127 dev_addr = demod->my_i2c_dev_addr; in set_agc_if()
5128 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_agc_if()
5139 if ((ext_attr->standard == agc_settings->standard) || in set_agc_if()
5140 (DRXJ_ISQAMSTD(ext_attr->standard) && in set_agc_if()
5141 DRXJ_ISQAMSTD(agc_settings->standard)) || in set_agc_if()
5142 (DRXJ_ISATVSTD(ext_attr->standard) && in set_agc_if()
5143 DRXJ_ISATVSTD(agc_settings->standard))) { in set_agc_if()
5146 switch (agc_settings->ctrl_mode) { in set_agc_if()
5148 /* Enable IF AGC DAC */ in set_agc_if()
5169 if (ext_attr->standard == DRX_STANDARD_8VSB) in set_agc_if()
5171 else if (DRXJ_ISQAMSTD(ext_attr->standard)) in set_agc_if()
5176 if (common_attr->tuner_if_agc_pol) in set_agc_if()
5193 …rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IA… in set_agc_if()
5199 if (agc_settings->standard == DRX_STANDARD_8VSB) in set_agc_if()
5200 p_agc_settings = &(ext_attr->vsb_rf_agc_cfg); in set_agc_if()
5201 else if (DRXJ_ISQAMSTD(agc_settings->standard)) in set_agc_if()
5202 p_agc_settings = &(ext_attr->qam_rf_agc_cfg); in set_agc_if()
5203 else if (DRXJ_ISATVSTD(agc_settings->standard)) in set_agc_if()
5204 p_agc_settings = &(ext_attr->atv_rf_agc_cfg); in set_agc_if()
5206 return -EINVAL; in set_agc_if()
5209 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { in set_agc_if()
5210 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0); in set_agc_if()
5215 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0); in set_agc_if()
5236 /* Enable IF AGC DAC */ in set_agc_if()
5257 if (common_attr->tuner_if_agc_pol) in set_agc_if()
5268 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0); in set_agc_if()
5277 /* Disable If AGC DAC */ in set_agc_if()
5305 return -EINVAL; in set_agc_if()
5306 } /* switch ( agcsettings->ctrl_mode ) */ in set_agc_if()
5308 /* always set the top to support configurations without if-loop */ in set_agc_if()
5309 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0); in set_agc_if()
5317 switch (agc_settings->standard) { in set_agc_if()
5319 ext_attr->vsb_if_agc_cfg = *agc_settings; in set_agc_if()
5325 ext_attr->qam_if_agc_cfg = *agc_settings; in set_agc_if()
5329 return -EIO; in set_agc_if()
5350 dev_addr = demod->my_i2c_dev_addr; in set_iqm_af()
5392 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in power_down_vsb()
5680 dev_addr = demod->my_i2c_dev_addr; in set_vsb_leak_n_gain()
5714 DRXJ_16TO8(-2), /* re0 */ in set_vsb()
5717 DRXJ_16TO8(-4), /* re3 */ in set_vsb()
5720 DRXJ_16TO8(-3), /* re6 */ in set_vsb()
5721 DRXJ_16TO8(-3), /* re7 */ in set_vsb()
5724 DRXJ_16TO8(-9), /* re10 */ in set_vsb()
5727 DRXJ_16TO8(-9), /* re13 */ in set_vsb()
5728 DRXJ_16TO8(-15), /* re14 */ in set_vsb()
5731 DRXJ_16TO8(-29), /* re17 */ in set_vsb()
5732 DRXJ_16TO8(-22), /* re18 */ in set_vsb()
5735 DRXJ_16TO8(-70), /* re21 */ in set_vsb()
5736 DRXJ_16TO8(-28), /* re22 */ in set_vsb()
5739 DRXJ_16TO8(-201), /* re25 */ in set_vsb()
5740 DRXJ_16TO8(-31), /* re26 */ in set_vsb()
5744 dev_addr = demod->my_i2c_dev_addr; in set_vsb()
5745 common_attr = (struct drx_common_attr *) demod->my_common_attr; in set_vsb()
5746 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_vsb()
5813 ext_attr->iqm_rc_rate_ofs = 0x00AD0D79; in set_vsb()
5814 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); in set_vsb()
6029 /* B-Input to ADC, PGA+filter in standby */ in set_vsb()
6030 if (!ext_attr->has_lna) { in set_vsb()
6055 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false); in set_vsb()
6060 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false); in set_vsb()
6070 vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg; in set_vsb()
6077 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg)); in set_vsb()
6104 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); in set_vsb()
6232 return -EIO; in get_vsb_post_rs_pck_err()
6276 return -EIO; in get_vs_bpost_viterbi_ber()
6279 (bit_errors_exp - 3) : bit_errors_exp); in get_vs_bpost_viterbi_ber()
6301 return -EIO; in get_vs_bpre_viterbi_ber()
6325 (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52)); in get_vsbmer()
6359 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in power_down_qam()
6361 struct drx_common_attr *common_attr = demod->my_common_attr; in power_down_qam()
6431 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); in power_down_qam()
6451 * \param constellation current constellation.
6458 * TODO: overriding the ext_attr->fec_bits_desired by constellation dependent
6482 dev_addr = demod->my_i2c_dev_addr; in set_qam_measurement()
6483 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_qam_measurement()
6485 fec_bits_desired = ext_attr->fec_bits_desired; in set_qam_measurement()
6486 fec_rs_prescale = ext_attr->fec_rs_prescale; in set_qam_measurement()
6505 return -EINVAL; in set_qam_measurement()
6508 /* Parameters for Reed-Solomon Decoder */ in set_qam_measurement()
6511 /* result is within 32 bit arithmetic -> */ in set_qam_measurement()
6515 switch (ext_attr->standard) { in set_qam_measurement()
6524 return -EINVAL; in set_qam_measurement()
6527 ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */ in set_qam_measurement()
6531 return -EIO; in set_qam_measurement()
6534 if (ext_attr->standard != DRX_STANDARD_ITU_B) in set_qam_measurement()
6537 /* limit to max 16 bit value (I2C register width) if needed */ in set_qam_measurement()
6542 switch (ext_attr->standard) { in set_qam_measurement()
6557 return -EINVAL; in set_qam_measurement()
6561 return -EINVAL; in set_qam_measurement()
6579 ext_attr->fec_rs_period = (u16) fec_rs_period; in set_qam_measurement()
6580 ext_attr->fec_rs_prescale = fec_rs_prescale; in set_qam_measurement()
6597 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam_measurement()
6602 /* result is within 32 bit arithmetic -> */ in set_qam_measurement()
6606 fec_vd_plen = ext_attr->fec_vd_plen; in set_qam_measurement()
6607 qam_vd_prescale = ext_attr->qam_vd_prescale; in set_qam_measurement()
6624 return -EINVAL; in set_qam_measurement()
6628 return -EIO; in set_qam_measurement()
6631 /* limit to max 16 bit value (I2C register width) if needed */ in set_qam_measurement()
6648 ext_attr->qam_vd_period = (u16) qam_vd_period; in set_qam_measurement()
6649 ext_attr->qam_vd_prescale = qam_vd_prescale; in set_qam_measurement()
6667 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam16()
6764 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0); in set_qam16()
6769 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0); in set_qam16()
6774 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0); in set_qam16()
6902 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam32()
6989 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0); in set_qam32()
6994 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0); in set_qam32()
6999 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0); in set_qam32()
7004 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0); in set_qam32()
7009 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0); in set_qam32()
7137 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam64()
7140 /* this is hw reset value. no necessary to re-write */ in set_qam64()
7235 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0); in set_qam64()
7240 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0); in set_qam64()
7245 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0); in set_qam64()
7373 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam128()
7470 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0); in set_qam128()
7480 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0); in set_qam128()
7608 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam256()
7715 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0); in set_qam256()
7867 DRXJ_16TO8(-1), /* re0 */ in set_qam()
7870 DRXJ_16TO8(-1), /* re3 */ in set_qam()
7871 DRXJ_16TO8(-1), /* re4 */ in set_qam()
7874 DRXJ_16TO8(-2), /* re7 */ in set_qam()
7877 DRXJ_16TO8(-1), /* re10 */ in set_qam()
7878 DRXJ_16TO8(-3), /* re11 */ in set_qam()
7881 DRXJ_16TO8(-8), /* re14 */ in set_qam()
7884 DRXJ_16TO8(-13), /* re17 */ in set_qam()
7885 DRXJ_16TO8(-19), /* re18 */ in set_qam()
7888 DRXJ_16TO8(-53), /* re21 */ in set_qam()
7889 DRXJ_16TO8(-31), /* re22 */ in set_qam()
7892 DRXJ_16TO8(-190), /* re25 */ in set_qam()
7893 DRXJ_16TO8(-40), /* re26 */ in set_qam()
7898 DRXJ_16TO8(-2), /* re1 */ in set_qam()
7901 DRXJ_16TO8(-2), /* re4 */ in set_qam()
7904 DRXJ_16TO8(-2), /* re7 */ in set_qam()
7905 DRXJ_16TO8(-4), /* re8 */ in set_qam()
7908 DRXJ_16TO8(-6), /* re11 */ in set_qam()
7911 DRXJ_16TO8(-5), /* re14 */ in set_qam()
7912 DRXJ_16TO8(-3), /* re15 */ in set_qam()
7914 DRXJ_16TO8(-4), /* re17 */ in set_qam()
7915 DRXJ_16TO8(-19), /* re18 */ in set_qam()
7918 DRXJ_16TO8(-45), /* re21 */ in set_qam()
7919 DRXJ_16TO8(-36), /* re22 */ in set_qam()
7922 DRXJ_16TO8(-185), /* re25 */ in set_qam()
7923 DRXJ_16TO8(-46), /* re26 */ in set_qam()
7927 DRXJ_16TO8(-2), /* re0 */ in set_qam()
7930 DRXJ_16TO8(-4), /* re3 */ in set_qam()
7933 DRXJ_16TO8(-2), /* re6 */ in set_qam()
7934 DRXJ_16TO8(-4), /* re7 */ in set_qam()
7937 DRXJ_16TO8(-8), /* re10 */ in set_qam()
7940 DRXJ_16TO8(-8), /* re13 */ in set_qam()
7941 DRXJ_16TO8(-15), /* re14 */ in set_qam()
7944 DRXJ_16TO8(-27), /* re17 */ in set_qam()
7945 DRXJ_16TO8(-22), /* re18 */ in set_qam()
7948 DRXJ_16TO8(-69), /* re21 */ in set_qam()
7949 DRXJ_16TO8(-28), /* re22 */ in set_qam()
7952 DRXJ_16TO8(-201), /* re25 */ in set_qam()
7953 DRXJ_16TO8(-32), /* re26 */ in set_qam()
7957 DRXJ_16TO8(-3), /* re0 */ in set_qam()
7960 DRXJ_16TO8(-4), /* re3 */ in set_qam()
7963 DRXJ_16TO8(-1), /* re6 */ in set_qam()
7964 DRXJ_16TO8(-4), /* re7 */ in set_qam()
7967 DRXJ_16TO8(-5), /* re10 */ in set_qam()
7970 DRXJ_16TO8(-4), /* re13 */ in set_qam()
7971 DRXJ_16TO8(-12), /* re14 */ in set_qam()
7974 DRXJ_16TO8(-21), /* re17 */ in set_qam()
7975 DRXJ_16TO8(-20), /* re18 */ in set_qam()
7978 DRXJ_16TO8(-62), /* re21 */ in set_qam()
7979 DRXJ_16TO8(-28), /* re22 */ in set_qam()
7982 DRXJ_16TO8(-197), /* re25 */ in set_qam()
7983 DRXJ_16TO8(-33), /* re26 */ in set_qam()
7987 dev_addr = demod->my_i2c_dev_addr; in set_qam()
7988 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_qam()
7989 common_attr = (struct drx_common_attr *) demod->my_common_attr; in set_qam()
7992 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam()
7993 switch (channel->constellation) { in set_qam()
7998 channel->symbolrate = 5360537; in set_qam()
8004 channel->symbolrate = 5056941; in set_qam()
8008 return -EINVAL; in set_qam()
8011 adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; in set_qam()
8012 if (channel->symbolrate == 0) { in set_qam()
8014 return -EIO; in set_qam()
8017 (adc_frequency / channel->symbolrate) * (1 << 21) + in set_qam()
8019 ((adc_frequency % channel->symbolrate), in set_qam()
8020 channel->symbolrate) >> 7) - (1 << 23); in set_qam()
8023 (channel->symbolrate + in set_qam()
8032 if (ext_attr->standard == DRX_STANDARD_ITU_A) { in set_qam()
8034 set_param_parameters[0] = channel->constellation; /* constellation */ in set_qam()
8036 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam()
8038 set_param_parameters[0] = channel->constellation; /* constellation */ in set_qam()
8039 set_param_parameters[1] = channel->interleavemode; /* interleave mode */ in set_qam()
8040 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { in set_qam()
8042 set_param_parameters[0] = channel->constellation; /* constellation */ in set_qam()
8045 return -EINVAL; in set_qam()
8108 -set env in set_qam()
8109 -set params (resets IQM,QAM,FEC HW; initializes some SCU variables ) in set_qam()
8140 ext_attr->iqm_rc_rate_ofs = iqm_rc_rate; in set_qam()
8141 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate); in set_qam()
8150 /* TODO: remove re-writes of HW reset values */ in set_qam()
8174 if (!ext_attr->has_lna) { in set_qam()
8255 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam()
8272 switch (channel->constellation) { in set_qam()
8311 return -EIO; in set_qam()
8442 /* No more resets of the IQM, current standard correctly set => in set_qam()
8461 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false); in set_qam()
8466 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false); in set_qam()
8476 qam_pga_cfg.gain = ext_attr->qam_pga_cfg; in set_qam()
8483 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg)); in set_qam()
8491 if (ext_attr->standard == DRX_STANDARD_ITU_A) { in set_qam()
8502 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam()
8503 switch (channel->constellation) { in set_qam()
8529 return -EIO; in set_qam()
8531 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { in set_qam()
8545 switch (channel->constellation) { in set_qam()
8582 return -EIO; in set_qam()
8614 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); in set_qam()
8667 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in qam_flip_spec()
8668 struct drxj_data *ext_attr = demod->my_ext_attr; in qam_flip_spec()
8713 ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs; in qam_flip_spec()
8715 iqm_fs_rate_ofs -= 2 * ofsofs; in qam_flip_spec()
8758 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; in qam_flip_spec()
8759 ext_attr->pos_image = !ext_attr->pos_image; in qam_flip_spec()
8786 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0); in qam_flip_spec()
8799 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0); in qam_flip_spec()
8862 struct drxj_data *ext_attr = demod->my_ext_attr; in qam64auto()
8863 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in qam64auto()
8864 struct drx39xxj_state *state = dev_addr->user_data; in qam64auto()
8865 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; in qam64auto()
8892 if (p->cnr.stat[0].svalue > 20800) { in qam64auto()
8902 ((jiffies_to_msecs(jiffies) - d_locked_time) > in qam64auto()
8904 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8909 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); in qam64auto()
8920 if (channel->mirror == DRX_MIRROR_AUTO) { in qam64auto()
8922 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8927 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0); in qam64auto()
8933 ext_attr->mirror = DRX_MIRROR_YES; in qam64auto()
8947 jiffies_to_msecs(jiffies) - in qam64auto()
8948 DRXJ_QAM_MAX_WAITTIME - timeout_ofs; in qam64auto()
8954 ((jiffies_to_msecs(jiffies) - d_locked_time) > in qam64auto()
8961 if (p->cnr.stat[0].svalue > 20800) { in qam64auto()
8962 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8967 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); in qam64auto()
8974 jiffies_to_msecs(jiffies) - in qam64auto()
8975 DRXJ_QAM_MAX_WAITTIME - timeout_ofs; in qam64auto()
8986 ((jiffies_to_msecs(jiffies) - start_time) < in qam64auto()
9010 struct drxj_data *ext_attr = demod->my_ext_attr; in qam256auto()
9011 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in qam256auto()
9012 struct drx39xxj_state *state = dev_addr->user_data; in qam256auto()
9013 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; in qam256auto()
9038 if (p->cnr.stat[0].svalue > 26800) { in qam256auto()
9047 if ((channel->mirror == DRX_MIRROR_AUTO) && in qam256auto()
9048 ((jiffies_to_msecs(jiffies) - d_locked_time) > in qam256auto()
9050 ext_attr->mirror = DRX_MIRROR_YES; in qam256auto()
9059 timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2; in qam256auto()
9072 ((jiffies_to_msecs(jiffies) - start_time) < in qam256auto()
9097 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_qam_channel()
9100 switch (channel->constellation) { in set_qam_channel()
9104 return -EINVAL; in set_qam_channel()
9107 if (ext_attr->standard != DRX_STANDARD_ITU_B) in set_qam_channel()
9108 return -EINVAL; in set_qam_channel()
9110 ext_attr->constellation = channel->constellation; in set_qam_channel()
9111 if (channel->mirror == DRX_MIRROR_AUTO) in set_qam_channel()
9112 ext_attr->mirror = DRX_MIRROR_NO; in set_qam_channel()
9114 ext_attr->mirror = channel->mirror; in set_qam_channel()
9122 if (channel->constellation == DRX_CONSTELLATION_QAM64) in set_qam_channel()
9134 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam_channel()
9140 channel->constellation = DRX_CONSTELLATION_QAM256; in set_qam_channel()
9141 ext_attr->constellation = DRX_CONSTELLATION_QAM256; in set_qam_channel()
9142 if (channel->mirror == DRX_MIRROR_AUTO) in set_qam_channel()
9143 ext_attr->mirror = DRX_MIRROR_NO; in set_qam_channel()
9145 ext_attr->mirror = channel->mirror; in set_qam_channel()
9160 channel->constellation = DRX_CONSTELLATION_AUTO; in set_qam_channel()
9165 channel->constellation = DRX_CONSTELLATION_QAM64; in set_qam_channel()
9166 ext_attr->constellation = DRX_CONSTELLATION_QAM64; in set_qam_channel()
9167 if (channel->mirror == DRX_MIRROR_AUTO) in set_qam_channel()
9168 ext_attr->mirror = DRX_MIRROR_NO; in set_qam_channel()
9170 ext_attr->mirror = channel->mirror; in set_qam_channel()
9172 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9179 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9186 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9200 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9215 channel->constellation = DRX_CONSTELLATION_AUTO; in set_qam_channel()
9216 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { in set_qam_channel()
9219 channel->constellation = DRX_CONSTELLATION_QAM64; in set_qam_channel()
9220 ext_attr->constellation = DRX_CONSTELLATION_QAM64; in set_qam_channel()
9223 if (channel->mirror == DRX_MIRROR_AUTO) in set_qam_channel()
9224 ext_attr->mirror = DRX_MIRROR_NO; in set_qam_channel()
9226 ext_attr->mirror = channel->mirror; in set_qam_channel()
9227 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9234 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9241 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9255 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9268 channel->constellation = DRX_CONSTELLATION_AUTO; in set_qam_channel()
9270 return -EINVAL; in set_qam_channel()
9274 return -EINVAL; in set_qam_channel()
9281 channel->constellation = DRX_CONSTELLATION_AUTO; in set_qam_channel()
9306 return -EINVAL; in get_qamrs_err_count()
9341 /* These register values are fetched in non-atomic fashion */ in get_qamrs_err_count()
9344 rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M; in get_qamrs_err_count()
9345 rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M; in get_qamrs_err_count()
9346 rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M; in get_qamrs_err_count()
9347 rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M; in get_qamrs_err_count()
9348 rs_errors->nr_snc_par_fail_count = in get_qamrs_err_count()
9362 * \param u16-t Pointer to signal strength data; range 0, .. , 100.
9365 * \retval -EINVAL sig_strength is NULL.
9366 * \retval -EIO Erroneous data, sig_strength contains invalid data.
9375 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in get_sig_strength()
9408 return -EIO; in get_sig_strength()
9411 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max - in get_sig_strength()
9418 return -EIO; in get_sig_strength()
9421 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns); in get_sig_strength()
9425 return -EIO; in get_sig_strength()
9445 * \retval -EINVAL sig_quality is NULL.
9446 * \retval -EIO Erroneous data, sig_quality contains invalid data.
9448 * Pre-condition: Device must be started and in lock.
9453 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in ctrl_get_qam_sig_quality()
9454 struct drxj_data *ext_attr = demod->my_ext_attr; in ctrl_get_qam_sig_quality()
9455 struct drx39xxj_state *state = dev_addr->user_data; in ctrl_get_qam_sig_quality()
9456 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; in ctrl_get_qam_sig_quality()
9458 enum drx_modulation constellation = ext_attr->constellation; in ctrl_get_qam_sig_quality()
9485 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9508 fec_rs_period = ext_attr->fec_rs_period; in ctrl_get_qam_sig_quality()
9509 fec_rs_prescale = ext_attr->fec_rs_prescale; in ctrl_get_qam_sig_quality()
9510 rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen; in ctrl_get_qam_sig_quality()
9511 qam_vd_period = ext_attr->qam_vd_period; in ctrl_get_qam_sig_quality()
9512 qam_vd_prescale = ext_attr->qam_vd_prescale; in ctrl_get_qam_sig_quality()
9513 vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen; in ctrl_get_qam_sig_quality()
9533 rc = -EIO; in ctrl_get_qam_sig_quality()
9537 /* ------------------------------ */ in ctrl_get_qam_sig_quality()
9539 /* ------------------------------ */ in ctrl_get_qam_sig_quality()
9546 qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power); in ctrl_get_qam_sig_quality()
9548 /* ----------------------------------------- */ in ctrl_get_qam_sig_quality()
9550 /* ----------------------------------------- */ in ctrl_get_qam_sig_quality()
9570 qam_vd_ser = m << ((e > 2) ? (e - 3) : e); in ctrl_get_qam_sig_quality()
9572 /* --------------------------------------- */ in ctrl_get_qam_sig_quality()
9574 /* --------------------------------------- */ in ctrl_get_qam_sig_quality()
9575 /* pre RS BER is good if it is below 3.5e-4 */ in ctrl_get_qam_sig_quality()
9582 /* pre Reed-Solomon bit error count */ in ctrl_get_qam_sig_quality()
9616 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9617 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9618 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9619 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9620 p->block_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9621 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; in ctrl_get_qam_sig_quality()
9623 p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100; in ctrl_get_qam_sig_quality()
9624 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in ctrl_get_qam_sig_quality()
9625 p->pre_bit_error.stat[0].uvalue += qam_vd_ser; in ctrl_get_qam_sig_quality()
9626 p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8; in ctrl_get_qam_sig_quality()
9628 p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber; in ctrl_get_qam_sig_quality()
9629 p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e; in ctrl_get_qam_sig_quality()
9632 p->post_bit_error.stat[0].uvalue += qam_post_rs_ber; in ctrl_get_qam_sig_quality()
9633 p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e; in ctrl_get_qam_sig_quality()
9635 p->block_error.stat[0].uvalue += pkt_errs; in ctrl_get_qam_sig_quality()
9638 rc = get_acc_pkt_err(demod, &sig_quality->packet_error); in ctrl_get_qam_sig_quality()
9647 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9648 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9649 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9650 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9651 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9652 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9677 (3) Video AGC (used to amplify the output signal in case input to low)
9678 (4) SIF AGC (used to amplify the output signal in case input to low)
9687 (3) SIF AGC (used to amplify the output signal in case input to low)
9723 /* -------------------------------------------------------------------------- */
9739 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in power_down_atv()
9838 dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; in power_down_aud()
9839 ext_attr = (struct drxj_data *) demod->my_ext_attr; in power_down_aud()
9847 ext_attr->aud_data.audio_is_active = false; in power_down_aud()
9863 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_orx_nsu_aox()
9905 #define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*s…
9906 #define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqr…
9907 …ne IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full rais…
9932 …{DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_… in ctrl_set_oob()
9933 …{DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B … in ctrl_set_oob()
9934 …{DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B … in ctrl_set_oob()
9935 …{DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B =… in ctrl_set_oob()
9939 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_oob()
9940 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_oob()
9941 mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob; in ctrl_set_oob()
9967 ext_attr->oob_power_on = false; in ctrl_set_oob()
9971 freq = oob_param->frequency; in ctrl_set_oob()
9973 return -EIO; in ctrl_set_oob()
9974 freq = (freq - 50000) / 50; in ctrl_set_oob()
9979 u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg; in ctrl_set_oob()
9981 index = (u16) ((freq - 400) / 200); in ctrl_set_oob()
9982 remainder = (u16) ((freq - 400) % 200); in ctrl_set_oob()
9984 trk_filtercfg[index] - (trk_filtercfg[index] - in ctrl_set_oob()
10028 /* 1-data rate;2-frequency */ in ctrl_set_oob()
10029 switch (oob_param->standard) { in ctrl_set_oob()
10033 ((oob_param->spectrum_inverted == true) && in ctrl_set_oob()
10038 ((oob_param->spectrum_inverted == false) && in ctrl_set_oob()
10051 ((oob_param->spectrum_inverted == true) && in ctrl_set_oob()
10056 ((oob_param->spectrum_inverted == false) && in ctrl_set_oob()
10070 ((oob_param->spectrum_inverted == true) && in ctrl_set_oob()
10075 ((oob_param->spectrum_inverted == false) && in ctrl_set_oob()
10143 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); in ctrl_set_oob()
10183 /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ in ctrl_set_oob()
10189 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10199 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10210 /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ in ctrl_set_oob()
10216 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10226 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10237 /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ in ctrl_set_oob()
10243 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10253 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10264 /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ in ctrl_set_oob()
10270 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10280 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10291 /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ in ctrl_set_oob()
10297 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10307 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10318 /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ in ctrl_set_oob()
10324 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10334 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); in ctrl_set_oob()
10345 /* PRE-Filter coefficients (PFI) */ in ctrl_set_oob()
10357 /* NYQUIST-Filter coefficients (NYQ) */ in ctrl_set_oob()
10399 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); in ctrl_set_oob()
10405 ext_attr->oob_power_on = true; in ctrl_set_oob()
10450 return -EINVAL; in ctrl_set_channel()
10452 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_channel()
10453 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_channel()
10454 standard = ext_attr->standard; in ctrl_set_channel()
10467 return -EINVAL; in ctrl_set_channel()
10474 switch (channel->bandwidth) { in ctrl_set_channel()
10477 channel->bandwidth = DRX_BANDWIDTH_6MHZ; in ctrl_set_channel()
10482 return -EINVAL; in ctrl_set_channel()
10487 -check symbolrate and constellation in ctrl_set_channel()
10488 -derive bandwidth from symbolrate (input bandwidth is ignored) in ctrl_set_channel()
10506 if (channel->symbolrate < min_symbol_rate || in ctrl_set_channel()
10507 channel->symbolrate > max_symbol_rate) { in ctrl_set_channel()
10508 return -EINVAL; in ctrl_set_channel()
10511 switch (channel->constellation) { in ctrl_set_channel()
10517 bandwidth_temp = channel->symbolrate * bw_rolloff_factor; in ctrl_set_channel()
10524 channel->bandwidth = DRX_BANDWIDTH_6MHZ; in ctrl_set_channel()
10527 channel->bandwidth = DRX_BANDWIDTH_7MHZ; in ctrl_set_channel()
10529 channel->bandwidth = DRX_BANDWIDTH_8MHZ; in ctrl_set_channel()
10533 return -EINVAL; in ctrl_set_channel()
10538 -check constellation in ctrl_set_channel()
10541 switch (channel->constellation) { in ctrl_set_channel()
10547 return -EINVAL; in ctrl_set_channel()
10550 switch (channel->interleavemode) { in ctrl_set_channel()
10572 return -EINVAL; in ctrl_set_channel()
10576 if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) { in ctrl_set_channel()
10580 switch (channel->bandwidth) { in ctrl_set_channel()
10592 return -EINVAL; in ctrl_set_channel()
10613 if (channel->mirror == DRX_MIRROR_AUTO) in ctrl_set_channel()
10614 ext_attr->mirror = DRX_MIRROR_NO; in ctrl_set_channel()
10616 ext_attr->mirror = channel->mirror; in ctrl_set_channel()
10641 return -EIO; in ctrl_set_channel()
10645 ext_attr->reset_pkt_err_acc = true; in ctrl_set_channel()
10663 * \retval -EINVAL sig_quality is NULL.
10664 * \retval -EIO Erroneous data, sig_quality contains invalid data.
10671 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in ctrl_sig_quality()
10672 struct drxj_data *ext_attr = demod->my_ext_attr; in ctrl_sig_quality()
10673 struct drx39xxj_state *state = dev_addr->user_data; in ctrl_sig_quality()
10674 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; in ctrl_sig_quality()
10675 enum drx_standard standard = ext_attr->standard; in ctrl_sig_quality()
10683 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10685 p->strength.stat[0].scale = FE_SCALE_RELATIVE; in ctrl_sig_quality()
10686 p->strength.stat[0].uvalue = 65535UL * strength/ 100; in ctrl_sig_quality()
10699 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10700 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10701 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10702 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10703 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10704 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10705 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10710 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10712 p->block_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10713 p->block_error.stat[0].uvalue += err; in ctrl_sig_quality()
10714 p->block_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10715 p->block_count.stat[0].uvalue += pkt; in ctrl_sig_quality()
10718 /* PostViterbi is compute in steps of 10^(-6) */ in ctrl_sig_quality()
10721 pr_err("error %d getting pre-ber\n", rc); in ctrl_sig_quality()
10722 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10724 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10725 p->pre_bit_error.stat[0].uvalue += ber; in ctrl_sig_quality()
10726 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10727 p->pre_bit_count.stat[0].uvalue += cnt; in ctrl_sig_quality()
10732 pr_err("error %d getting post-ber\n", rc); in ctrl_sig_quality()
10733 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10735 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10736 p->post_bit_error.stat[0].uvalue += ber; in ctrl_sig_quality()
10737 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10738 p->post_bit_count.stat[0].uvalue += cnt; in ctrl_sig_quality()
10743 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10745 p->cnr.stat[0].svalue = mer * 100; in ctrl_sig_quality()
10746 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; in ctrl_sig_quality()
10762 return -EIO; in ctrl_sig_quality()
10798 return -EINVAL; in ctrl_lock_status()
10800 dev_addr = demod->my_i2c_dev_addr; in ctrl_lock_status()
10801 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_lock_status()
10802 standard = ext_attr->standard; in ctrl_lock_status()
10823 return -EIO; in ctrl_lock_status()
10879 return -EINVAL; in ctrl_set_standard()
10881 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_standard()
10882 prev_standard = ext_attr->standard; in ctrl_set_standard()
10911 rc = -EINVAL; in ctrl_set_standard()
10919 ext_attr->standard = *standard; in ctrl_set_standard()
10928 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); in ctrl_set_standard()
10944 ext_attr->standard = DRX_STANDARD_UNKNOWN; in ctrl_set_standard()
10945 return -EINVAL; in ctrl_set_standard()
10951 ext_attr->standard = DRX_STANDARD_UNKNOWN; in ctrl_set_standard()
10960 if (ext_attr->has_lna) { in drxj_reset_mode()
10963 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; in drxj_reset_mode()
10964 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; in drxj_reset_mode()
10965 ext_attr->qam_pga_cfg = 140 + (11 * 13); in drxj_reset_mode()
10967 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; in drxj_reset_mode()
10968 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; in drxj_reset_mode()
10969 ext_attr->vsb_pga_cfg = 140 + (11 * 13); in drxj_reset_mode()
10973 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; in drxj_reset_mode()
10974 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; in drxj_reset_mode()
10975 ext_attr->qam_if_agc_cfg.min_output_level = 0; in drxj_reset_mode()
10976 ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF; in drxj_reset_mode()
10977 ext_attr->qam_if_agc_cfg.speed = 3; in drxj_reset_mode()
10978 ext_attr->qam_if_agc_cfg.top = 1297; in drxj_reset_mode()
10979 ext_attr->qam_pga_cfg = 140; in drxj_reset_mode()
10981 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; in drxj_reset_mode()
10982 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; in drxj_reset_mode()
10983 ext_attr->vsb_if_agc_cfg.min_output_level = 0; in drxj_reset_mode()
10984 ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF; in drxj_reset_mode()
10985 ext_attr->vsb_if_agc_cfg.speed = 3; in drxj_reset_mode()
10986 ext_attr->vsb_if_agc_cfg.top = 1024; in drxj_reset_mode()
10987 ext_attr->vsb_pga_cfg = 140; in drxj_reset_mode()
10992 ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B; in drxj_reset_mode()
10993 ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; in drxj_reset_mode()
10994 ext_attr->qam_rf_agc_cfg.min_output_level = 0; in drxj_reset_mode()
10995 ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF; in drxj_reset_mode()
10996 ext_attr->qam_rf_agc_cfg.speed = 3; in drxj_reset_mode()
10997 ext_attr->qam_rf_agc_cfg.top = 9500; in drxj_reset_mode()
10998 ext_attr->qam_rf_agc_cfg.cut_off_current = 4000; in drxj_reset_mode()
10999 ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B; in drxj_reset_mode()
11000 ext_attr->qam_pre_saw_cfg.reference = 0x07; in drxj_reset_mode()
11001 ext_attr->qam_pre_saw_cfg.use_pre_saw = true; in drxj_reset_mode()
11004 ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB; in drxj_reset_mode()
11005 ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; in drxj_reset_mode()
11006 ext_attr->vsb_rf_agc_cfg.min_output_level = 0; in drxj_reset_mode()
11007 ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF; in drxj_reset_mode()
11008 ext_attr->vsb_rf_agc_cfg.speed = 3; in drxj_reset_mode()
11009 ext_attr->vsb_rf_agc_cfg.top = 9500; in drxj_reset_mode()
11010 ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000; in drxj_reset_mode()
11011 ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB; in drxj_reset_mode()
11012 ext_attr->vsb_pre_saw_cfg.reference = 0x07; in drxj_reset_mode()
11013 ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; in drxj_reset_mode()
11023 * \retval -EIO I2C error or other failure
11024 * \retval -EINVAL Invalid mode argument.
11037 common_attr = (struct drx_common_attr *) demod->my_common_attr; in ctrl_power_mode()
11038 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_power_mode()
11039 dev_addr = demod->my_i2c_dev_addr; in ctrl_power_mode()
11043 return -EINVAL; in ctrl_power_mode()
11046 if (common_attr->current_power_mode == *mode) in ctrl_power_mode()
11065 return -EINVAL; in ctrl_power_mode()
11069 if ((common_attr->current_power_mode != DRX_POWER_UP)) { in ctrl_power_mode()
11085 /* Set pins with possible pull-ups connected to them in input mode */ in ctrl_power_mode()
11094 switch (ext_attr->standard) { in ctrl_power_mode()
11118 rc = power_down_atv(demod, ext_attr->standard, true); in ctrl_power_mode()
11129 return -EIO; in ctrl_power_mode()
11131 ext_attr->standard = DRX_STANDARD_UNKNOWN; in ctrl_power_mode()
11154 ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in ctrl_power_mode()
11163 common_attr->current_power_mode = *mode; in ctrl_power_mode()
11176 * \brief Set Pre-saw reference.
11192 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_cfg_pre_saw()
11193 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_cfg_pre_saw()
11196 if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M) in ctrl_set_cfg_pre_saw()
11198 return -EINVAL; in ctrl_set_cfg_pre_saw()
11202 if ((ext_attr->standard == pre_saw->standard) || in ctrl_set_cfg_pre_saw()
11203 (DRXJ_ISQAMSTD(ext_attr->standard) && in ctrl_set_cfg_pre_saw()
11204 DRXJ_ISQAMSTD(pre_saw->standard)) || in ctrl_set_cfg_pre_saw()
11205 (DRXJ_ISATVSTD(ext_attr->standard) && in ctrl_set_cfg_pre_saw()
11206 DRXJ_ISATVSTD(pre_saw->standard))) { in ctrl_set_cfg_pre_saw()
11207 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0); in ctrl_set_cfg_pre_saw()
11214 /* Store pre-saw settings */ in ctrl_set_cfg_pre_saw()
11215 switch (pre_saw->standard) { in ctrl_set_cfg_pre_saw()
11217 ext_attr->vsb_pre_saw_cfg = *pre_saw; in ctrl_set_cfg_pre_saw()
11223 ext_attr->qam_pre_saw_cfg = *pre_saw; in ctrl_set_cfg_pre_saw()
11227 return -EINVAL; in ctrl_set_cfg_pre_saw()
11258 return -EINVAL; in ctrl_set_cfg_afe_gain()
11260 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_cfg_afe_gain()
11261 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_cfg_afe_gain()
11263 switch (afe_gain->standard) { in ctrl_set_cfg_afe_gain()
11273 return -EINVAL; in ctrl_set_cfg_afe_gain()
11279 if (afe_gain->gain >= 329) in ctrl_set_cfg_afe_gain()
11281 else if (afe_gain->gain <= 147) in ctrl_set_cfg_afe_gain()
11284 gain = (afe_gain->gain - 140 + 6) / 13; in ctrl_set_cfg_afe_gain()
11287 if (ext_attr->standard == afe_gain->standard) { in ctrl_set_cfg_afe_gain()
11296 switch (afe_gain->standard) { in ctrl_set_cfg_afe_gain()
11298 ext_attr->vsb_pga_cfg = gain * 13 + 140; in ctrl_set_cfg_afe_gain()
11304 ext_attr->qam_pga_cfg = gain * 13 + 140; in ctrl_set_cfg_afe_gain()
11308 return -EIO; in ctrl_set_cfg_afe_gain()
11350 (demod->my_common_attr == NULL) || in drxj_open()
11351 (demod->my_ext_attr == NULL) || in drxj_open()
11352 (demod->my_i2c_dev_addr == NULL) || in drxj_open()
11353 (demod->my_common_attr->is_opened)) { in drxj_open()
11354 return -EINVAL; in drxj_open()
11358 if (demod->my_ext_attr == NULL) in drxj_open()
11359 return -EINVAL; in drxj_open()
11361 dev_addr = demod->my_i2c_dev_addr; in drxj_open()
11362 ext_attr = (struct drxj_data *) demod->my_ext_attr; in drxj_open()
11363 common_attr = (struct drx_common_attr *) demod->my_common_attr; in drxj_open()
11371 rc = -EINVAL; in drxj_open()
11384 * Soft reset of sys- and osc-clockdomain in drxj_open()
11388 * Btw, this is coherent with DRX-K, where we send reset codes in drxj_open()
11389 * for modulation (OFTM, in DRX-k), SYS and OSC clock domains. in drxj_open()
11429 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); in drxj_open()
11451 if (common_attr->microcode_file != NULL) { in drxj_open()
11454 common_attr->is_opened = true; in drxj_open()
11455 ucode_info.mc_file = common_attr->microcode_file; in drxj_open()
11457 if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) { in drxj_open()
11459 rc = -EINVAL; in drxj_open()
11468 if (common_attr->verify_microcode == true) { in drxj_open()
11476 common_attr->is_opened = false; in drxj_open()
11487 common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT; in drxj_open()
11488 common_attr->scan_desired_lock = DRX_LOCKED; in drxj_open()
11491 ext_attr->standard = DRX_STANDARD_UNKNOWN; in drxj_open()
11536 ext_attr->aud_data = drxj_default_aud_data_g; in drxj_open()
11538 demod->my_common_attr->is_opened = true; in drxj_open()
11542 common_attr->is_opened = false; in drxj_open()
11555 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in drxj_close()
11559 if ((demod->my_common_attr == NULL) || in drxj_close()
11560 (demod->my_ext_attr == NULL) || in drxj_close()
11561 (demod->my_i2c_dev_addr == NULL) || in drxj_close()
11562 (!demod->my_common_attr->is_opened)) { in drxj_close()
11563 return -EINVAL; in drxj_close()
11599 * drx_u_code_compute_crc - Compute CRC of block of microcode data.
11627 * drx_check_firmware - checks if the loaded firmware is valid
11709 return -EINVAL; in drx_check_firmware()
11713 * drx_ctrl_u_code - Handle microcode upload or verify.
11720 * - In case of UCODE_UPLOAD: code is successfully uploaded.
11721 * - In case of UCODE_VERIFY: image on device is equal to
11723 * -EIO:
11724 * - In case of UCODE_UPLOAD: I2C error.
11725 * - In case of UCODE_VERIFY: I2C error or image on device
11727 * -EINVAL:
11728 * - Invalid arguments.
11729 * - Provided image is corrupt
11735 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in drx_ctrl_u_code()
11747 if (!mc_info || !mc_info->mc_file) in drx_ctrl_u_code()
11748 return -EINVAL; in drx_ctrl_u_code()
11750 mc_file = mc_info->mc_file; in drx_ctrl_u_code()
11752 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); in drx_ctrl_u_code()
11758 if (fw->size < 2 * sizeof(u16)) { in drx_ctrl_u_code()
11759 rc = -EINVAL; in drx_ctrl_u_code()
11764 pr_info("Firmware %s, size %zu\n", mc_file, fw->size); in drx_ctrl_u_code()
11766 mc_data_init = fw->data; in drx_ctrl_u_code()
11767 size = fw->size; in drx_ctrl_u_code()
11777 rc = -EINVAL; in drx_ctrl_u_code()
11807 (mc_data - mc_data_init), block_hdr.addr, in drx_ctrl_u_code()
11811 - data larger than 64Kb in drx_ctrl_u_code()
11812 - if CRC enabled check CRC in drx_ctrl_u_code()
11819 rc = -EINVAL; in drx_ctrl_u_code()
11836 rc = -EIO; in drx_ctrl_u_code()
11838 mc_data - mc_data_init); in drx_ctrl_u_code()
11862 mc_data - mc_data_init); in drx_ctrl_u_code()
11863 rc = -EIO; in drx_ctrl_u_code()
11872 mc_data - mc_data_init); in drx_ctrl_u_code()
11873 rc = -EIO; in drx_ctrl_u_code()
11879 bytes_left -=((u32) bytes_to_comp); in drx_ctrl_u_code()
11884 rc = -EINVAL; in drx_ctrl_u_code()
11908 /* Configure user-I/O #3: enable read/write */ in drxj_set_lna_state()
11934 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_set_powerstate()
11935 struct drx_demod_instance *demod = state->demod; in drx39xxj_set_powerstate()
11955 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_read_status()
11956 struct drx_demod_instance *demod = state->demod; in drx39xxj_read_status()
12003 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_read_ber()
12005 if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { in drx39xxj_read_ber()
12010 if (!p->pre_bit_count.stat[0].uvalue) { in drx39xxj_read_ber()
12011 if (!p->pre_bit_error.stat[0].uvalue) in drx39xxj_read_ber()
12016 *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue, in drx39xxj_read_ber()
12017 p->pre_bit_count.stat[0].uvalue); in drx39xxj_read_ber()
12025 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_read_signal_strength()
12027 if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { in drx39xxj_read_signal_strength()
12032 *strength = p->strength.stat[0].uvalue; in drx39xxj_read_signal_strength()
12038 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_read_snr()
12041 if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { in drx39xxj_read_snr()
12046 tmp64 = p->cnr.stat[0].svalue; in drx39xxj_read_snr()
12054 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_read_ucblocks()
12056 if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { in drx39xxj_read_ucblocks()
12061 *ucb = p->block_error.stat[0].uvalue; in drx39xxj_read_ucblocks()
12070 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_set_frontend()
12071 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_set_frontend()
12072 struct drx_demod_instance *demod = state->demod; in drx39xxj_set_frontend()
12098 if (fe->ops.tuner_ops.set_params) { in drx39xxj_set_frontend()
12101 if (fe->ops.i2c_gate_ctrl) in drx39xxj_set_frontend()
12102 fe->ops.i2c_gate_ctrl(fe, 1); in drx39xxj_set_frontend()
12105 fe->ops.tuner_ops.set_params(fe); in drx39xxj_set_frontend()
12108 if (fe->ops.tuner_ops.get_if_frequency) { in drx39xxj_set_frontend()
12109 fe->ops.tuner_ops.get_if_frequency(fe, &int_freq); in drx39xxj_set_frontend()
12110 demod->my_common_attr->intermediate_freq = int_freq / 1000; in drx39xxj_set_frontend()
12113 if (fe->ops.i2c_gate_ctrl) in drx39xxj_set_frontend()
12114 fe->ops.i2c_gate_ctrl(fe, 0); in drx39xxj_set_frontend()
12117 switch (p->delivery_system) { in drx39xxj_set_frontend()
12124 switch (p->modulation) { in drx39xxj_set_frontend()
12137 return -EINVAL; in drx39xxj_set_frontend()
12144 return -EINVAL; in drx39xxj_set_frontend()
12149 channel.frequency = p->frequency / 1000; in drx39xxj_set_frontend()
12157 return -EINVAL; in drx39xxj_set_frontend()
12163 p->strength.stat[0].scale = FE_SCALE_RELATIVE; in drx39xxj_set_frontend()
12170 /* power-down the demodulator */ in drx39xxj_sleep()
12176 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_i2c_gate_ctrl()
12177 struct drx_demod_instance *demod = state->demod; in drx39xxj_i2c_gate_ctrl()
12183 state->i2c_gate_open); in drx39xxj_i2c_gate_ctrl()
12191 if (state->i2c_gate_open == enable) { in drx39xxj_i2c_gate_ctrl()
12202 state->i2c_gate_open = enable; in drx39xxj_i2c_gate_ctrl()
12209 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_init()
12210 struct drx_demod_instance *demod = state->demod; in drx39xxj_init()
12213 if (fe->exit == DVB_FE_DEVICE_RESUME) { in drx39xxj_init()
12215 demod->my_common_attr->is_opened = false; in drx39xxj_init()
12227 struct dtv_frontend_properties *c = &fe->dtv_property_cache; in drx39xxj_set_lna()
12228 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_set_lna()
12229 struct drx_demod_instance *demod = state->demod; in drx39xxj_set_lna()
12230 struct drxj_data *ext_attr = demod->my_ext_attr; in drx39xxj_set_lna()
12232 if (c->lna) { in drx39xxj_set_lna()
12233 if (!ext_attr->has_lna) { in drx39xxj_set_lna()
12235 return -EINVAL; in drx39xxj_set_lna()
12240 return drxj_set_lna_state(demod, c->lna); in drx39xxj_set_lna()
12246 tune->min_delay_ms = 1000; in drx39xxj_get_tune_settings()
12252 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_release()
12253 struct drx_demod_instance *demod = state->demod; in drx39xxj_release()
12256 if (fe->exit != DVB_FE_DEVICE_REMOVED) in drx39xxj_release()
12259 kfree(demod->my_ext_attr); in drx39xxj_release()
12260 kfree(demod->my_common_attr); in drx39xxj_release()
12261 kfree(demod->my_i2c_dev_addr); in drx39xxj_release()
12304 state->i2c = i2c; in drx39xxj_attach()
12305 state->demod = demod; in drx39xxj_attach()
12308 demod->my_i2c_dev_addr = demod_addr; in drx39xxj_attach()
12309 demod->my_common_attr = demod_comm_attr; in drx39xxj_attach()
12310 demod->my_i2c_dev_addr->user_data = state; in drx39xxj_attach()
12311 demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE; in drx39xxj_attach()
12312 demod->my_common_attr->verify_microcode = true; in drx39xxj_attach()
12313 demod->my_common_attr->intermediate_freq = 5000; in drx39xxj_attach()
12314 demod->my_common_attr->current_power_mode = DRX_POWER_DOWN; in drx39xxj_attach()
12315 demod->my_ext_attr = demod_ext_attr; in drx39xxj_attach()
12316 ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; in drx39xxj_attach()
12317 demod->i2c = i2c; in drx39xxj_attach()
12326 memcpy(&state->frontend.ops, &drx39xxj_ops, in drx39xxj_attach()
12329 state->frontend.demodulator_priv = state; in drx39xxj_attach()
12331 /* Initialize stats - needed for DVBv5 stats to work */ in drx39xxj_attach()
12332 p = &state->frontend.dtv_property_cache; in drx39xxj_attach()
12333 p->strength.len = 1; in drx39xxj_attach()
12334 p->pre_bit_count.len = 1; in drx39xxj_attach()
12335 p->pre_bit_error.len = 1; in drx39xxj_attach()
12336 p->post_bit_count.len = 1; in drx39xxj_attach()
12337 p->post_bit_error.len = 1; in drx39xxj_attach()
12338 p->block_count.len = 1; in drx39xxj_attach()
12339 p->block_error.len = 1; in drx39xxj_attach()
12340 p->cnr.len = 1; in drx39xxj_attach()
12342 p->strength.stat[0].scale = FE_SCALE_RELATIVE; in drx39xxj_attach()
12343 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12344 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12345 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12346 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12347 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12348 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12349 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12351 return &state->frontend; in drx39xxj_attach()