Lines Matching +full:ave +full:- +full:ctrl
2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
49 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
52 /*-----------------------------------------------------------------------------
54 ----------------------------------------------------------------------------*/
75 #define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw"
201 /*-----------------------------------------------------------------------------
203 ----------------------------------------------------------------------------*/
205 /*-----------------------------------------------------------------------------
207 ----------------------------------------------------------------------------*/
209 #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
438 #define AUD_VOLUME_DB_MIN -60
486 * x -> lowbyte(x), highbyte(x)
527 /*-----------------------------------------------------------------------------
529 ----------------------------------------------------------------------------*/
626 {-5,
634 {-50,
650 {-160,
775 { /* ATV RF-AGC */
783 4000 /* cut-off current */
785 { /* ATV IF-AGC */
830 (151875 - 0), /* system clock frequency in kHz */
976 /*-----------------------------------------------------------------------------
978 ----------------------------------------------------------------------------*/
995 * struct drxu_code_block_hdr - Structure of the microcode block headers
1010 /*-----------------------------------------------------------------------------
1012 ----------------------------------------------------------------------------*/
1047 * This function is used to avoid floating-point calculations as they may
1050 * frac28 performs an unsigned 28/28 bits division to 32-bit fixed point
1052 * N and D can hold numbers up to width: 28-bits.
1055 * Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999
1057 * N: 0...(1<<28)-1 = 268435454
1058 * D: 0...(1<<28)-1
1059 * Q: 0...(1<<32)-1
1067 R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */
1154 /* computing y in log(x/y) = log(x) - log(y) */
1155 if ((x & (((u32) (-1)) << (scale + 1))) == 0) {
1156 for (k = scale; k > 0; k--) {
1163 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
1169 Now x has binary point between bit[scale] and bit[scale-1]
1176 x &= ((((u32) 1) << scale) - 1);
1178 i = (u8) (x >> (scale - index_width));
1179 /* compute delta (x-a) */
1180 d = x & ((((u32) 1) << (scale - index_width)) - 1);
1183 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width));
1198 * \param N nominator 16-bits.
1199 * \param D denominator 32-bits.
1259 -conversion to short address format
1260 -access to audio block
1314 state = r_dev_addr->user_data;
1315 msg[0].addr = r_dev_addr->i2c_addr >> 1;
1322 state = w_dev_addr->user_data;
1323 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1330 state = w_dev_addr->user_data;
1331 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1335 msg[1].addr = r_dev_addr->i2c_addr >> 1;
1342 if (state->i2c == NULL) {
1346 if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
1348 return -EREMOTEIO;
1355 state = w_dev_addr->user_data;
1357 if (state->i2c == NULL)
1360 msg[0].addr = w_dev_addr->i2c_addr;
1364 msg[1].addr = r_dev_addr->i2c_addr;
1371 w_dev_addr->i2c_addr, state->i2c, w_count, r_count);
1373 if (i2c_transfer(state->i2c, msg, 2) != 2) {
1375 return -EREMOTEIO;
1386 * struct i2c_device_addr *dev_addr, -- address of I2C device
1387 * u32 addr, -- address of chip register/memory
1388 * u16 datasize, -- number of bytes to read
1389 * u8 *data, -- data to receive
1390 * u32 flags) -- special device flags
1402 * - 0 if reading was successful
1404 * - -EIO if anything went wrong
1420 return -EINVAL;
1422 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1430 return -EINVAL;
1487 datasize -= todo;
1497 * struct i2c_device_addr *dev_addr, -- address of I2C device
1498 * u32 addr, -- address of chip register/memory
1499 * u16 *data, -- data to receive
1500 * u32 flags) -- special device flags
1502 * Read one 16-bit register or memory location. The data received back is
1506 * - 0 if reading was successful
1508 * - -EIO if anything went wrong
1520 return -EINVAL;
1530 * struct i2c_device_addr *dev_addr, -- address of I2C device
1531 * u32 addr, -- address of chip register/memory
1532 * u32 *data, -- data to receive
1533 * u32 flags) -- special device flags
1535 * Read one 32-bit register or memory location. The data received back is
1539 * - 0 if reading was successful
1541 * - -EIO if anything went wrong
1553 return -EINVAL;
1565 * struct i2c_device_addr *dev_addr, -- address of I2C device
1566 * u32 addr, -- address of chip register/memory
1567 * u16 datasize, -- number of bytes to read
1568 * u8 *data, -- data to receive
1569 * u32 flags) -- special device flags
1579 * - 0 if writing was successful
1580 * - -EIO if anything went wrong
1590 int st = -EIO;
1597 return -EINVAL;
1599 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1607 return -EINVAL;
1616 block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1;
1661 (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1);
1663 (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1;
1691 datasize -= todo;
1702 * struct i2c_device_addr *dev_addr, -- address of I2C device
1703 * u32 addr, -- address of chip register/memory
1704 * u16 data, -- data to send
1705 * u32 flags) -- special device flags
1707 * Write one 16-bit register or memory location. The data being written is
1711 * - 0 if writing was successful
1712 * - -EIO if anything went wrong
1731 * struct i2c_device_addr *dev_addr, -- address of I2C device
1732 * u32 waddr, -- address of chip register/memory
1733 * u32 raddr, -- chip address to read back from
1734 * u16 wdata, -- data to send
1735 * u16 *rdata) -- data to receive back
1737 * Write 16-bit data, then read back the original contents of that location.
1747 * - 0 if reading was successful
1749 * - -EIO if anything went wrong
1758 int rc = -EIO;
1762 return -EINVAL;
1775 * struct i2c_device_addr *dev_addr, -- address of I2C device
1776 * u32 addr, -- address of chip register/memory
1777 * u32 data, -- data to send
1778 * u32 flags) -- special device flags
1780 * Write one 32-bit register or memory location. The data being written is
1784 * - 0 if writing was successful
1785 * - -EIO if anything went wrong
1815 * \retval -EIO Timeout, I2C error, illegal bank
1834 return -EINVAL;
1892 * \retval -EIO Timeout, I2C error, illegal bank
1904 int stat = -EIO;
1908 stat = -EINVAL;
1928 delta_timer = current_timer - start_timer;
1930 stat = -EIO;
1953 delta_timer = current_timer - start_timer;
1955 stat = -EIO;
1976 int stat = -EIO;
1980 return -EINVAL;
1999 * \retval -EIO Timeout, I2C error, illegal bank
2007 int stat = -EIO;
2011 stat = -EINVAL;
2032 delta_timer = current_timer - start_timer;
2034 stat = -EIO;
2054 int stat = -EIO;
2058 return -EINVAL;
2089 * \retval -EIO Timeout, I2C error, illegal bank
2106 return -EINVAL;
2115 hi_cmd.param3 = (u16) ((datasize / 2) - 1);
2180 return -EINVAL;
2221 * enable/disable should not need re-configuration of the HI.
2231 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2235 hi_cmd.param2 = ext_attr->hi_cfg_timing_div;
2236 hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay;
2237 hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key;
2238 hi_cmd.param5 = ext_attr->hi_cfg_ctrl;
2239 hi_cmd.param6 = ext_attr->hi_cfg_transmit;
2241 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
2248 ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2276 switch (cmd->cmd) {
2280 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0);
2285 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0);
2290 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0);
2295 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0);
2302 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
2307 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0);
2318 return -EINVAL;
2322 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0);
2328 if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET)
2332 powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
2333 (((cmd->
2341 rc = -ETIMEDOUT;
2373 * \retval -EIO Failure.
2387 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2388 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2389 dev_addr = demod->my_i2c_dev_addr;
2400 ext_attr->hi_cfg_timing_div =
2401 (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000;
2403 if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
2404 ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
2408 ext_attr->hi_cfg_bridge_delay =
2409 (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) /
2412 if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M)
2413 ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
2415 ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) <<
2420 ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY;
2421 /* port/bridge/power down ctrl */
2422 ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE);
2424 ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE;
2454 * \retval -EIO Failure
2457 * * common_attr->osc_clock_freq
2458 * * ext_attr->has_lna
2459 * * ext_attr->has_ntsc
2460 * * ext_attr->has_btsc
2461 * * ext_attr->has_oob
2474 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2475 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2476 dev_addr = demod->my_i2c_dev_addr;
2500 common_attr->osc_clock_freq = 27000;
2504 common_attr->osc_clock_freq = 20250;
2508 common_attr->osc_clock_freq = 4000;
2511 return -EIO;
2523 ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF);
2544 ext_attr->has_lna = true;
2545 ext_attr->has_ntsc = false;
2546 ext_attr->has_btsc = false;
2547 ext_attr->has_oob = false;
2548 ext_attr->has_smatx = true;
2549 ext_attr->has_smarx = false;
2550 ext_attr->has_gpio = false;
2551 ext_attr->has_irqn = false;
2554 ext_attr->has_lna = false;
2555 ext_attr->has_ntsc = false;
2556 ext_attr->has_btsc = false;
2557 ext_attr->has_oob = false;
2558 ext_attr->has_smatx = true;
2559 ext_attr->has_smarx = false;
2560 ext_attr->has_gpio = false;
2561 ext_attr->has_irqn = false;
2564 ext_attr->has_lna = true;
2565 ext_attr->has_ntsc = true;
2566 ext_attr->has_btsc = false;
2567 ext_attr->has_oob = false;
2568 ext_attr->has_smatx = true;
2569 ext_attr->has_smarx = true;
2570 ext_attr->has_gpio = true;
2571 ext_attr->has_irqn = false;
2574 ext_attr->has_lna = false;
2575 ext_attr->has_ntsc = true;
2576 ext_attr->has_btsc = false;
2577 ext_attr->has_oob = false;
2578 ext_attr->has_smatx = true;
2579 ext_attr->has_smarx = true;
2580 ext_attr->has_gpio = true;
2581 ext_attr->has_irqn = false;
2584 ext_attr->has_lna = true;
2585 ext_attr->has_ntsc = true;
2586 ext_attr->has_btsc = true;
2587 ext_attr->has_oob = false;
2588 ext_attr->has_smatx = true;
2589 ext_attr->has_smarx = true;
2590 ext_attr->has_gpio = true;
2591 ext_attr->has_irqn = false;
2594 ext_attr->has_lna = false;
2595 ext_attr->has_ntsc = true;
2596 ext_attr->has_btsc = true;
2597 ext_attr->has_oob = false;
2598 ext_attr->has_smatx = true;
2599 ext_attr->has_smarx = true;
2600 ext_attr->has_gpio = true;
2601 ext_attr->has_irqn = false;
2604 ext_attr->has_lna = true;
2605 ext_attr->has_ntsc = false;
2606 ext_attr->has_btsc = false;
2607 ext_attr->has_oob = true;
2608 ext_attr->has_smatx = true;
2609 ext_attr->has_smarx = true;
2610 ext_attr->has_gpio = true;
2611 ext_attr->has_irqn = true;
2614 ext_attr->has_lna = false;
2615 ext_attr->has_ntsc = true;
2616 ext_attr->has_btsc = true;
2617 ext_attr->has_oob = true;
2618 ext_attr->has_smatx = true;
2619 ext_attr->has_smarx = true;
2620 ext_attr->has_gpio = true;
2621 ext_attr->has_irqn = true;
2624 ext_attr->has_lna = true;
2625 ext_attr->has_ntsc = true;
2626 ext_attr->has_btsc = true;
2627 ext_attr->has_oob = true;
2628 ext_attr->has_smatx = true;
2629 ext_attr->has_smarx = true;
2630 ext_attr->has_gpio = true;
2631 ext_attr->has_irqn = true;
2634 ext_attr->has_lna = false;
2635 ext_attr->has_ntsc = true;
2636 ext_attr->has_btsc = true;
2637 ext_attr->has_oob = true;
2638 ext_attr->has_smatx = true;
2639 ext_attr->has_smarx = true;
2640 ext_attr->has_gpio = true;
2641 ext_attr->has_irqn = true;
2645 return -EIO;
2660 * \retval -EIO Failure, I2C or max retries reached
2675 dev_addr = demod->my_i2c_dev_addr;
2677 wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id;
2678 wake_up_addr.user_data = dev_addr->user_data;
2700 return -EIO;
2705 /*----------------------------------------------------------------------------*/
2706 /* MPEG Output Configuration Functions - begin */
2707 /*----------------------------------------------------------------------------*/
2741 return -EINVAL;
2743 dev_addr = demod->my_i2c_dev_addr;
2744 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2745 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2747 if (cfg_data->enable_mpeg_output == true) {
2750 switch (ext_attr->standard) {
2765 switch (ext_attr->standard) {
2812 switch (ext_attr->constellation) {
2829 return -EIO;
2830 } /* ext_attr->constellation */
2834 (ext_attr->curr_symbol_rate / 8) * nr_bits * 188;
2862 if (cfg_data->static_clk == true) {
2890 /* Check insertion of the Reed-Solomon parity bytes */
2901 if (cfg_data->insert_rs_byte == true) {
2906 switch (ext_attr->standard) {
2912 switch (ext_attr->constellation) {
2920 return -EIO;
2925 /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */
2929 (u32) (common_attr->sys_clock_freq / 8))) /
2933 return -EIO;
2934 } /* ext_attr->standard */
2941 switch (ext_attr->standard) {
2947 switch (ext_attr->constellation) {
2955 return -EIO;
2960 /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */
2964 (u32) (common_attr->sys_clock_freq / 8))) /
2968 return -EIO;
2969 } /* ext_attr->standard */
2972 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> clear ipr_mode[0] */
2974 } else { /* MPEG data output is serial -> set ipr_mode[0] */
2979 if (cfg_data->invert_data == true)
2984 if (cfg_data->invert_err == true)
2989 if (cfg_data->invert_str == true)
2994 if (cfg_data->invert_val == true)
2999 if (cfg_data->invert_clk == true)
3005 if (cfg_data->static_clk == true) { /* Static mode */
3013 switch (ext_attr->standard) {
3016 if (cfg_data->insert_rs_byte == true)
3022 if (cfg_data->insert_rs_byte == true) {
3026 if (ext_attr->curr_symbol_rate >=
3036 if (cfg_data->insert_rs_byte == true)
3041 if (cfg_data->insert_rs_byte == true)
3045 return -EIO;
3048 common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period +
3051 frac28(bit_rate, common_attr->sys_clock_freq * 1000);
3078 if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO)
3079 fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1;
3158 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> set MD1 to MD7 to output mode */
3203 } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */
3334 /* save values for restore after re-acquire */
3335 common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output;
3342 /*----------------------------------------------------------------------------*/
3345 /*----------------------------------------------------------------------------*/
3346 /* MPEG Output Configuration Functions - end */
3347 /*----------------------------------------------------------------------------*/
3349 /*----------------------------------------------------------------------------*/
3350 /* miscellaneous configurations - begin */
3351 /*----------------------------------------------------------------------------*/
3371 dev_addr = demod->my_i2c_dev_addr;
3372 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3396 if (ext_attr->disable_te_ihandling) {
3425 /*----------------------------------------------------------------------------*/
3428 * \brief Set MPEG output bit-endian settings.
3442 dev_addr = demod->my_i2c_dev_addr;
3443 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3454 if (ext_attr->bit_reverse_mpeg_outout)
3468 /*----------------------------------------------------------------------------*/
3486 dev_addr = demod->my_i2c_dev_addr;
3487 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3488 common_attr = demod->my_common_attr;
3490 if ((common_attr->mpeg_cfg.static_clk == true)
3491 && (common_attr->mpeg_cfg.enable_parallel == false)) {
3498 if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC)
3512 /*----------------------------------------------------------------------------*/
3513 /* miscellaneous configurations - end */
3514 /*----------------------------------------------------------------------------*/
3516 /*----------------------------------------------------------------------------*/
3517 /* UIO Configuration Functions - begin */
3518 /*----------------------------------------------------------------------------*/
3532 return -EINVAL;
3534 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3537 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3542 switch (uio_cfg->uio) {
3545 /* DRX_UIO1: SMA_TX UIO-1 */
3546 if (!ext_attr->has_smatx)
3547 return -EIO;
3548 switch (uio_cfg->mode) {
3552 ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3555 ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3556 /* pad configuration register is set 0 - input mode */
3557 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0);
3564 return -EINVAL;
3565 } /* switch ( uio_cfg->mode ) */
3569 /* DRX_UIO2: SMA_RX UIO-2 */
3570 if (!ext_attr->has_smarx)
3571 return -EIO;
3572 switch (uio_cfg->mode) {
3575 ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3578 ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3579 /* pad configuration register is set 0 - input mode */
3580 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0);
3587 return -EINVAL;
3588 } /* switch ( uio_cfg->mode ) */
3592 /* DRX_UIO3: GPIO UIO-3 */
3593 if (!ext_attr->has_gpio)
3594 return -EIO;
3595 switch (uio_cfg->mode) {
3598 ext_attr->uio_gpio_mode = uio_cfg->mode;
3601 ext_attr->uio_gpio_mode = uio_cfg->mode;
3602 /* pad configuration register is set 0 - input mode */
3603 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0);
3610 return -EINVAL;
3611 } /* switch ( uio_cfg->mode ) */
3615 /* DRX_UIO4: IRQN UIO-4 */
3616 if (!ext_attr->has_irqn)
3617 return -EIO;
3618 switch (uio_cfg->mode) {
3620 ext_attr->uio_irqn_mode = uio_cfg->mode;
3623 /* pad configuration register is set 0 - input mode */
3624 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0);
3629 ext_attr->uio_irqn_mode = uio_cfg->mode;
3633 return -EINVAL;
3634 } /* switch ( uio_cfg->mode ) */
3638 return -EINVAL;
3639 } /* switch ( uio_cfg->uio ) */
3642 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3669 return -EINVAL;
3671 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3674 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3679 switch (uio_data->uio) {
3682 /* DRX_UIO1: SMA_TX UIO-1 */
3683 if (!ext_attr->has_smatx)
3684 return -EIO;
3685 if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE)
3686 && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) {
3687 return -EIO;
3695 /* write to io pad configuration register - output mode */
3696 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
3703 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3708 if (!uio_data->value)
3709 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
3711 value |= 0x8000; /* write one to 15th bit - 1st UIO */
3714 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3722 /* DRX_UIO2: SMA_RX UIO-2 */
3723 if (!ext_attr->has_smarx)
3724 return -EIO;
3725 if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE)
3726 return -EIO;
3734 /* write to io pad configuration register - output mode */
3735 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
3742 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3747 if (!uio_data->value)
3748 value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */
3750 value |= 0x4000; /* write one to 14th bit - 2nd UIO */
3753 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3761 /* DRX_UIO3: ASEL UIO-3 */
3762 if (!ext_attr->has_gpio)
3763 return -EIO;
3764 if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE)
3765 return -EIO;
3773 /* write to io pad configuration register - output mode */
3774 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);
3781 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0);
3786 if (!uio_data->value)
3787 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
3789 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
3792 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0);
3800 /* DRX_UIO4: IRQN UIO-4 */
3801 if (!ext_attr->has_irqn)
3802 return -EIO;
3804 if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE)
3805 return -EIO;
3813 /* write to io pad configuration register - output mode */
3814 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);
3821 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3826 if (uio_data->value == false)
3827 value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */
3829 value |= 0x1000; /* write one to 12th bit - 4th UIO */
3832 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3840 return -EINVAL;
3841 } /* switch ( uio_data->uio ) */
3844 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3855 /*---------------------------------------------------------------------------*/
3856 /* UIO Configuration Functions - end */
3857 /*---------------------------------------------------------------------------*/
3859 /*----------------------------------------------------------------------------*/
3860 /* I2C Bridge Functions - begin */
3861 /*----------------------------------------------------------------------------*/
3878 return -EINVAL;
3887 return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
3890 /*----------------------------------------------------------------------------*/
3891 /* I2C Bridge Functions - end */
3892 /*----------------------------------------------------------------------------*/
3894 /*----------------------------------------------------------------------------*/
3895 /* Smart antenna Functions - begin */
3896 /*----------------------------------------------------------------------------*/
3912 dev_addr = demod->my_i2c_dev_addr;
3913 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3916 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3927 if (ext_attr->smart_ant_inverted) {
3947 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);
3952 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);
3959 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3978 return -EINVAL;
3987 return -EIO;
3989 switch (cmd->parameter_len) {
3991 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0);
3998 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
4005 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
4012 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
4019 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
4030 return -EIO;
4032 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0);
4052 return -EIO;
4055 if ((cmd->result_len > 0) && (cmd->result != NULL)) {
4058 switch (cmd->result_len) {
4060 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0);
4067 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
4074 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
4081 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
4092 return -EIO;
4096 err = cmd->result[0];
4104 return -EINVAL;
4108 return -EIO;
4128 * \retval -EIO Timeout, I2C error, illegal bank
4131 #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
4143 return -EINVAL;
4205 return -EINVAL;
4239 /* -------------------------------------------------------------------------- */
4246 * \retval -EIO Failure: I2C error
4255 dev_addr = demod->my_i2c_dev_addr;
4305 * \retval -EIO Failure: I2C error or failure to synchronize
4318 dev_addr = demod->my_i2c_dev_addr;
4352 return -EIO;
4399 dev_addr = demod->my_i2c_dev_addr;
4400 common_attr = (struct drx_common_attr *) demod->my_common_attr;
4401 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4403 switch (ext_attr->standard) {
4406 clp_dir_to = (u16) (-9);
4408 sns_dir_to = (u16) (-9);
4409 ki_innergain_min = (u16) (-32768);
4481 p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg);
4482 p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg);
4490 clp_dir_to = (u16) (-5);
4492 sns_dir_to = (u16) (-3);
4549 p_agc_if_settings = &(ext_attr->qam_if_agc_cfg);
4550 p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg);
4551 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);
4571 return -EINVAL;
4575 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);
4580 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);
4599 } /* set to p_agc_settings->top before */
4706 agc_rf = 0x800 + p_agc_rf_settings->cut_off_current;
4707 if (common_attr->tuner_rf_agc_pol == true)
4708 agc_rf = 0x87ff - agc_rf;
4711 if (common_attr->tuner_if_agc_pol == true)
4712 agc_rf = 0x87ff - agc_rf;
4756 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
4757 struct drxj_data *ext_attr = demod->my_ext_attr;
4762 s32 rf_freq_residual = -1 * tuner_freq_offset;
4773 rf_mirror = ext_attr->mirror == DRX_MIRROR_YES;
4774 tuner_mirror = !demod->my_common_attr->mirror_freq_spect;
4779 switch (ext_attr->standard) {
4801 return -EINVAL;
4803 intermediate_freq = demod->my_common_attr->intermediate_freq;
4804 sampling_frequency = demod->my_common_attr->sys_clock_freq / 3;
4808 if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift;
4811 adc_freq = sampling_frequency - if_freq_actual;
4834 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
4835 ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image);
4849 * \retval -EINVAL sig_strength is NULL.
4850 * \retval -EIO Erroneous data, sig_strength contains invalid data.
4862 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4863 dev_addr = demod->my_i2c_dev_addr;
4870 if (ext_attr->reset_pkt_err_acc) {
4873 ext_attr->reset_pkt_err_acc = false;
4877 pkt_err += 0xffff - last_pkt_err;
4880 pkt_err += (data - last_pkt_err);
4912 common_attr = (struct drx_common_attr *) demod->my_common_attr;
4913 dev_addr = demod->my_i2c_dev_addr;
4914 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4925 if ((ext_attr->standard == agc_settings->standard) ||
4926 (DRXJ_ISQAMSTD(ext_attr->standard) &&
4927 DRXJ_ISQAMSTD(agc_settings->standard)) ||
4928 (DRXJ_ISATVSTD(ext_attr->standard) &&
4929 DRXJ_ISATVSTD(agc_settings->standard))) {
4932 switch (agc_settings->ctrl_mode) {
4955 if (ext_attr->standard == DRX_STANDARD_8VSB)
4957 else if (DRXJ_ISQAMSTD(ext_attr->standard))
4962 if (common_attr->tuner_rf_agc_pol)
4979 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0);
4985 if (agc_settings->standard == DRX_STANDARD_8VSB)
4986 p_agc_settings = &(ext_attr->vsb_if_agc_cfg);
4987 else if (DRXJ_ISQAMSTD(agc_settings->standard))
4988 p_agc_settings = &(ext_attr->qam_if_agc_cfg);
4989 else if (DRXJ_ISATVSTD(agc_settings->standard))
4990 p_agc_settings = &(ext_attr->atv_if_agc_cfg);
4992 return -EINVAL;
4994 /* Set TOP, only if IF-AGC is in AUTO mode */
4995 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
4996 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0);
5001 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0);
5008 /* Cut-Off current */
5009 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0);
5037 if (common_attr->tuner_rf_agc_pol)
5048 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0);
5083 return -EINVAL;
5084 } /* switch ( agcsettings->ctrl_mode ) */
5088 switch (agc_settings->standard) {
5090 ext_attr->vsb_rf_agc_cfg = *agc_settings;
5096 ext_attr->qam_rf_agc_cfg = *agc_settings;
5100 return -EIO;
5126 common_attr = (struct drx_common_attr *) demod->my_common_attr;
5127 dev_addr = demod->my_i2c_dev_addr;
5128 ext_attr = (struct drxj_data *) demod->my_ext_attr;
5139 if ((ext_attr->standard == agc_settings->standard) ||
5140 (DRXJ_ISQAMSTD(ext_attr->standard) &&
5141 DRXJ_ISQAMSTD(agc_settings->standard)) ||
5142 (DRXJ_ISATVSTD(ext_attr->standard) &&
5143 DRXJ_ISATVSTD(agc_settings->standard))) {
5146 switch (agc_settings->ctrl_mode) {
5169 if (ext_attr->standard == DRX_STANDARD_8VSB)
5171 else if (DRXJ_ISQAMSTD(ext_attr->standard))
5176 if (common_attr->tuner_if_agc_pol)
5193 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0);
5199 if (agc_settings->standard == DRX_STANDARD_8VSB)
5200 p_agc_settings = &(ext_attr->vsb_rf_agc_cfg);
5201 else if (DRXJ_ISQAMSTD(agc_settings->standard))
5202 p_agc_settings = &(ext_attr->qam_rf_agc_cfg);
5203 else if (DRXJ_ISATVSTD(agc_settings->standard))
5204 p_agc_settings = &(ext_attr->atv_rf_agc_cfg);
5206 return -EINVAL;
5209 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
5210 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0);
5215 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0);
5257 if (common_attr->tuner_if_agc_pol)
5268 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0);
5305 return -EINVAL;
5306 } /* switch ( agcsettings->ctrl_mode ) */
5308 /* always set the top to support configurations without if-loop */
5309 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0);
5317 switch (agc_settings->standard) {
5319 ext_attr->vsb_if_agc_cfg = *agc_settings;
5325 ext_attr->qam_if_agc_cfg = *agc_settings;
5329 return -EIO;
5350 dev_addr = demod->my_i2c_dev_addr;
5392 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
5680 dev_addr = demod->my_i2c_dev_addr;
5714 DRXJ_16TO8(-2), /* re0 */
5717 DRXJ_16TO8(-4), /* re3 */
5720 DRXJ_16TO8(-3), /* re6 */
5721 DRXJ_16TO8(-3), /* re7 */
5724 DRXJ_16TO8(-9), /* re10 */
5727 DRXJ_16TO8(-9), /* re13 */
5728 DRXJ_16TO8(-15), /* re14 */
5731 DRXJ_16TO8(-29), /* re17 */
5732 DRXJ_16TO8(-22), /* re18 */
5735 DRXJ_16TO8(-70), /* re21 */
5736 DRXJ_16TO8(-28), /* re22 */
5739 DRXJ_16TO8(-201), /* re25 */
5740 DRXJ_16TO8(-31), /* re26 */
5744 dev_addr = demod->my_i2c_dev_addr;
5745 common_attr = (struct drx_common_attr *) demod->my_common_attr;
5746 ext_attr = (struct drxj_data *) demod->my_ext_attr;
5813 ext_attr->iqm_rc_rate_ofs = 0x00AD0D79;
5814 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);
6029 /* B-Input to ADC, PGA+filter in standby */
6030 if (!ext_attr->has_lna) {
6055 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);
6060 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);
6070 vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg;
6077 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));
6104 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6232 return -EIO;
6276 return -EIO;
6279 (bit_errors_exp - 3) : bit_errors_exp);
6301 return -EIO;
6325 (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52));
6359 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6361 struct drx_common_attr *common_attr = demod->my_common_attr;
6431 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6458 * TODO: overriding the ext_attr->fec_bits_desired by constellation dependent
6482 dev_addr = demod->my_i2c_dev_addr;
6483 ext_attr = (struct drxj_data *) demod->my_ext_attr;
6485 fec_bits_desired = ext_attr->fec_bits_desired;
6486 fec_rs_prescale = ext_attr->fec_rs_prescale;
6505 return -EINVAL;
6508 /* Parameters for Reed-Solomon Decoder */
6511 /* result is within 32 bit arithmetic -> */
6515 switch (ext_attr->standard) {
6524 return -EINVAL;
6527 ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */
6531 return -EIO;
6534 if (ext_attr->standard != DRX_STANDARD_ITU_B)
6542 switch (ext_attr->standard) {
6557 return -EINVAL;
6561 return -EINVAL;
6579 ext_attr->fec_rs_period = (u16) fec_rs_period;
6580 ext_attr->fec_rs_prescale = fec_rs_prescale;
6597 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
6602 /* result is within 32 bit arithmetic -> */
6606 fec_vd_plen = ext_attr->fec_vd_plen;
6607 qam_vd_prescale = ext_attr->qam_vd_prescale;
6624 return -EINVAL;
6628 return -EIO;
6648 ext_attr->qam_vd_period = (u16) qam_vd_period;
6649 ext_attr->qam_vd_prescale = qam_vd_prescale;
6667 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6764 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0);
6769 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0);
6774 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0);
6902 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6989 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0);
6994 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0);
6999 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0);
7004 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0);
7009 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0);
7137 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7140 /* this is hw reset value. no necessary to re-write */
7235 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);
7240 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);
7245 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);
7373 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7470 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0);
7480 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0);
7608 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7715 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0);
7867 DRXJ_16TO8(-1), /* re0 */
7870 DRXJ_16TO8(-1), /* re3 */
7871 DRXJ_16TO8(-1), /* re4 */
7874 DRXJ_16TO8(-2), /* re7 */
7877 DRXJ_16TO8(-1), /* re10 */
7878 DRXJ_16TO8(-3), /* re11 */
7881 DRXJ_16TO8(-8), /* re14 */
7884 DRXJ_16TO8(-13), /* re17 */
7885 DRXJ_16TO8(-19), /* re18 */
7888 DRXJ_16TO8(-53), /* re21 */
7889 DRXJ_16TO8(-31), /* re22 */
7892 DRXJ_16TO8(-190), /* re25 */
7893 DRXJ_16TO8(-40), /* re26 */
7898 DRXJ_16TO8(-2), /* re1 */
7901 DRXJ_16TO8(-2), /* re4 */
7904 DRXJ_16TO8(-2), /* re7 */
7905 DRXJ_16TO8(-4), /* re8 */
7908 DRXJ_16TO8(-6), /* re11 */
7911 DRXJ_16TO8(-5), /* re14 */
7912 DRXJ_16TO8(-3), /* re15 */
7914 DRXJ_16TO8(-4), /* re17 */
7915 DRXJ_16TO8(-19), /* re18 */
7918 DRXJ_16TO8(-45), /* re21 */
7919 DRXJ_16TO8(-36), /* re22 */
7922 DRXJ_16TO8(-185), /* re25 */
7923 DRXJ_16TO8(-46), /* re26 */
7927 DRXJ_16TO8(-2), /* re0 */
7930 DRXJ_16TO8(-4), /* re3 */
7933 DRXJ_16TO8(-2), /* re6 */
7934 DRXJ_16TO8(-4), /* re7 */
7937 DRXJ_16TO8(-8), /* re10 */
7940 DRXJ_16TO8(-8), /* re13 */
7941 DRXJ_16TO8(-15), /* re14 */
7944 DRXJ_16TO8(-27), /* re17 */
7945 DRXJ_16TO8(-22), /* re18 */
7948 DRXJ_16TO8(-69), /* re21 */
7949 DRXJ_16TO8(-28), /* re22 */
7952 DRXJ_16TO8(-201), /* re25 */
7953 DRXJ_16TO8(-32), /* re26 */
7957 DRXJ_16TO8(-3), /* re0 */
7960 DRXJ_16TO8(-4), /* re3 */
7963 DRXJ_16TO8(-1), /* re6 */
7964 DRXJ_16TO8(-4), /* re7 */
7967 DRXJ_16TO8(-5), /* re10 */
7970 DRXJ_16TO8(-4), /* re13 */
7971 DRXJ_16TO8(-12), /* re14 */
7974 DRXJ_16TO8(-21), /* re17 */
7975 DRXJ_16TO8(-20), /* re18 */
7978 DRXJ_16TO8(-62), /* re21 */
7979 DRXJ_16TO8(-28), /* re22 */
7982 DRXJ_16TO8(-197), /* re25 */
7983 DRXJ_16TO8(-33), /* re26 */
7987 dev_addr = demod->my_i2c_dev_addr;
7988 ext_attr = (struct drxj_data *) demod->my_ext_attr;
7989 common_attr = (struct drx_common_attr *) demod->my_common_attr;
7992 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
7993 switch (channel->constellation) {
7998 channel->symbolrate = 5360537;
8004 channel->symbolrate = 5056941;
8008 return -EINVAL;
8011 adc_frequency = (common_attr->sys_clock_freq * 1000) / 3;
8012 if (channel->symbolrate == 0) {
8014 return -EIO;
8017 (adc_frequency / channel->symbolrate) * (1 << 21) +
8019 ((adc_frequency % channel->symbolrate),
8020 channel->symbolrate) >> 7) - (1 << 23);
8023 (channel->symbolrate +
8032 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8034 set_param_parameters[0] = channel->constellation; /* constellation */
8036 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8038 set_param_parameters[0] = channel->constellation; /* constellation */
8039 set_param_parameters[1] = channel->interleavemode; /* interleave mode */
8040 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8042 set_param_parameters[0] = channel->constellation; /* constellation */
8045 return -EINVAL;
8108 -set env
8109 -set params (resets IQM,QAM,FEC HW; initializes some SCU variables )
8140 ext_attr->iqm_rc_rate_ofs = iqm_rc_rate;
8141 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate);
8150 /* TODO: remove re-writes of HW reset values */
8174 if (!ext_attr->has_lna) {
8255 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8272 switch (channel->constellation) {
8311 return -EIO;
8461 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);
8466 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);
8476 qam_pga_cfg.gain = ext_attr->qam_pga_cfg;
8483 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));
8491 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8502 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8503 switch (channel->constellation) {
8529 return -EIO;
8531 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8545 switch (channel->constellation) {
8582 return -EIO;
8614 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
8667 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8668 struct drxj_data *ext_attr = demod->my_ext_attr;
8713 ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs;
8715 iqm_fs_rate_ofs -= 2 * ofsofs;
8758 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
8759 ext_attr->pos_image = !ext_attr->pos_image;
8786 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8799 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8862 struct drxj_data *ext_attr = demod->my_ext_attr;
8863 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8864 struct drx39xxj_state *state = dev_addr->user_data;
8865 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
8892 if (p->cnr.stat[0].svalue > 20800) {
8902 ((jiffies_to_msecs(jiffies) - d_locked_time) >
8904 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8909 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8920 if (channel->mirror == DRX_MIRROR_AUTO) {
8922 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8927 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);
8933 ext_attr->mirror = DRX_MIRROR_YES;
8947 jiffies_to_msecs(jiffies) -
8948 DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8954 ((jiffies_to_msecs(jiffies) - d_locked_time) >
8961 if (p->cnr.stat[0].svalue > 20800) {
8962 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8967 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8974 jiffies_to_msecs(jiffies) -
8975 DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8986 ((jiffies_to_msecs(jiffies) - start_time) <
9010 struct drxj_data *ext_attr = demod->my_ext_attr;
9011 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9012 struct drx39xxj_state *state = dev_addr->user_data;
9013 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9038 if (p->cnr.stat[0].svalue > 26800) {
9047 if ((channel->mirror == DRX_MIRROR_AUTO) &&
9048 ((jiffies_to_msecs(jiffies) - d_locked_time) >
9050 ext_attr->mirror = DRX_MIRROR_YES;
9059 timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2;
9072 ((jiffies_to_msecs(jiffies) - start_time) <
9097 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9100 switch (channel->constellation) {
9104 return -EINVAL;
9107 if (ext_attr->standard != DRX_STANDARD_ITU_B)
9108 return -EINVAL;
9110 ext_attr->constellation = channel->constellation;
9111 if (channel->mirror == DRX_MIRROR_AUTO)
9112 ext_attr->mirror = DRX_MIRROR_NO;
9114 ext_attr->mirror = channel->mirror;
9122 if (channel->constellation == DRX_CONSTELLATION_QAM64)
9134 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9140 channel->constellation = DRX_CONSTELLATION_QAM256;
9141 ext_attr->constellation = DRX_CONSTELLATION_QAM256;
9142 if (channel->mirror == DRX_MIRROR_AUTO)
9143 ext_attr->mirror = DRX_MIRROR_NO;
9145 ext_attr->mirror = channel->mirror;
9160 channel->constellation = DRX_CONSTELLATION_AUTO;
9165 channel->constellation = DRX_CONSTELLATION_QAM64;
9166 ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9167 if (channel->mirror == DRX_MIRROR_AUTO)
9168 ext_attr->mirror = DRX_MIRROR_NO;
9170 ext_attr->mirror = channel->mirror;
9172 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9179 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9186 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9200 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9215 channel->constellation = DRX_CONSTELLATION_AUTO;
9216 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
9219 channel->constellation = DRX_CONSTELLATION_QAM64;
9220 ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9223 if (channel->mirror == DRX_MIRROR_AUTO)
9224 ext_attr->mirror = DRX_MIRROR_NO;
9226 ext_attr->mirror = channel->mirror;
9227 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9234 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9241 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9255 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9268 channel->constellation = DRX_CONSTELLATION_AUTO;
9270 return -EINVAL;
9274 return -EINVAL;
9281 channel->constellation = DRX_CONSTELLATION_AUTO;
9306 return -EINVAL;
9341 /* These register values are fetched in non-atomic fashion */
9344 rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M;
9345 rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M;
9346 rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M;
9347 rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M;
9348 rs_errors->nr_snc_par_fail_count =
9362 * \param u16-t Pointer to signal strength data; range 0, .. , 100.
9365 * \retval -EINVAL sig_strength is NULL.
9366 * \retval -EIO Erroneous data, sig_strength contains invalid data.
9375 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9408 return -EIO;
9411 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max -
9418 return -EIO;
9421 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns);
9425 return -EIO;
9445 * \retval -EINVAL sig_quality is NULL.
9446 * \retval -EIO Erroneous data, sig_quality contains invalid data.
9448 * Pre-condition: Device must be started and in lock.
9453 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9454 struct drxj_data *ext_attr = demod->my_ext_attr;
9455 struct drx39xxj_state *state = dev_addr->user_data;
9456 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9458 enum drx_modulation constellation = ext_attr->constellation;
9485 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9508 fec_rs_period = ext_attr->fec_rs_period;
9509 fec_rs_prescale = ext_attr->fec_rs_prescale;
9510 rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen;
9511 qam_vd_period = ext_attr->qam_vd_period;
9512 qam_vd_prescale = ext_attr->qam_vd_prescale;
9513 vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen;
9533 rc = -EIO;
9537 /* ------------------------------ */
9539 /* ------------------------------ */
9546 qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power);
9548 /* ----------------------------------------- */
9550 /* ----------------------------------------- */
9570 qam_vd_ser = m << ((e > 2) ? (e - 3) : e);
9572 /* --------------------------------------- */
9574 /* --------------------------------------- */
9575 /* pre RS BER is good if it is below 3.5e-4 */
9582 /* pre Reed-Solomon bit error count */
9616 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9617 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9618 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9619 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9620 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
9621 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
9623 p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100;
9624 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9625 p->pre_bit_error.stat[0].uvalue += qam_vd_ser;
9626 p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
9628 p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber;
9629 p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9632 p->post_bit_error.stat[0].uvalue += qam_post_rs_ber;
9633 p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9635 p->block_error.stat[0].uvalue += pkt_errs;
9638 rc = get_acc_pkt_err(demod, &sig_quality->packet_error);
9647 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9648 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9649 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9650 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9651 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9652 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9723 /* -------------------------------------------------------------------------- */
9739 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9838 dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr;
9839 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9847 ext_attr->aud_data.audio_is_active = false;
9863 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9905 #define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */
9906 #define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */
9907 #define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */
9932 {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */
9933 {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */
9934 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
9935 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
9939 dev_addr = demod->my_i2c_dev_addr;
9940 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9941 mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob;
9967 ext_attr->oob_power_on = false;
9971 freq = oob_param->frequency;
9973 return -EIO;
9974 freq = (freq - 50000) / 50;
9979 u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg;
9981 index = (u16) ((freq - 400) / 200);
9982 remainder = (u16) ((freq - 400) % 200);
9984 trk_filtercfg[index] - (trk_filtercfg[index] -
10028 /* 1-data rate;2-frequency */
10029 switch (oob_param->standard) {
10033 ((oob_param->spectrum_inverted == true) &&
10038 ((oob_param->spectrum_inverted == false) &&
10051 ((oob_param->spectrum_inverted == true) &&
10056 ((oob_param->spectrum_inverted == false) &&
10070 ((oob_param->spectrum_inverted == true) &&
10075 ((oob_param->spectrum_inverted == false) &&
10143 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);
10183 /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */
10189 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);
10199 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);
10210 /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */
10216 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);
10226 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);
10237 /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */
10243 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);
10253 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);
10264 /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */
10270 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);
10280 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);
10291 /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */
10297 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);
10307 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);
10318 /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */
10324 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);
10334 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);
10345 /* PRE-Filter coefficients (PFI) */
10357 /* NYQUIST-Filter coefficients (NYQ) */
10399 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);
10405 ext_attr->oob_power_on = true;
10450 return -EINVAL;
10452 dev_addr = demod->my_i2c_dev_addr;
10453 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10454 standard = ext_attr->standard;
10467 return -EINVAL;
10474 switch (channel->bandwidth) {
10477 channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10482 return -EINVAL;
10487 -check symbolrate and constellation
10488 -derive bandwidth from symbolrate (input bandwidth is ignored)
10506 if (channel->symbolrate < min_symbol_rate ||
10507 channel->symbolrate > max_symbol_rate) {
10508 return -EINVAL;
10511 switch (channel->constellation) {
10517 bandwidth_temp = channel->symbolrate * bw_rolloff_factor;
10524 channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10527 channel->bandwidth = DRX_BANDWIDTH_7MHZ;
10529 channel->bandwidth = DRX_BANDWIDTH_8MHZ;
10533 return -EINVAL;
10538 -check constellation
10541 switch (channel->constellation) {
10547 return -EINVAL;
10550 switch (channel->interleavemode) {
10572 return -EINVAL;
10576 if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) {
10580 switch (channel->bandwidth) {
10592 return -EINVAL;
10613 if (channel->mirror == DRX_MIRROR_AUTO)
10614 ext_attr->mirror = DRX_MIRROR_NO;
10616 ext_attr->mirror = channel->mirror;
10641 return -EIO;
10645 ext_attr->reset_pkt_err_acc = true;
10663 * \retval -EINVAL sig_quality is NULL.
10664 * \retval -EIO Erroneous data, sig_quality contains invalid data.
10671 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
10672 struct drxj_data *ext_attr = demod->my_ext_attr;
10673 struct drx39xxj_state *state = dev_addr->user_data;
10674 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
10675 enum drx_standard standard = ext_attr->standard;
10683 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10685 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
10686 p->strength.stat[0].uvalue = 65535UL * strength/ 100;
10699 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10700 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10701 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10702 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10703 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10704 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10705 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10710 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10712 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
10713 p->block_error.stat[0].uvalue += err;
10714 p->block_count.stat[0].scale = FE_SCALE_COUNTER;
10715 p->block_count.stat[0].uvalue += pkt;
10718 /* PostViterbi is compute in steps of 10^(-6) */
10721 pr_err("error %d getting pre-ber\n", rc);
10722 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10724 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10725 p->pre_bit_error.stat[0].uvalue += ber;
10726 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10727 p->pre_bit_count.stat[0].uvalue += cnt;
10732 pr_err("error %d getting post-ber\n", rc);
10733 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10735 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10736 p->post_bit_error.stat[0].uvalue += ber;
10737 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10738 p->post_bit_count.stat[0].uvalue += cnt;
10743 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10745 p->cnr.stat[0].svalue = mer * 100;
10746 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
10762 return -EIO;
10798 return -EINVAL;
10800 dev_addr = demod->my_i2c_dev_addr;
10801 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10802 standard = ext_attr->standard;
10823 return -EIO;
10879 return -EINVAL;
10881 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10882 prev_standard = ext_attr->standard;
10911 rc = -EINVAL;
10919 ext_attr->standard = *standard;
10928 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0);
10944 ext_attr->standard = DRX_STANDARD_UNKNOWN;
10945 return -EINVAL;
10951 ext_attr->standard = DRX_STANDARD_UNKNOWN;
10960 if (ext_attr->has_lna) {
10963 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10964 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10965 ext_attr->qam_pga_cfg = 140 + (11 * 13);
10967 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10968 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10969 ext_attr->vsb_pga_cfg = 140 + (11 * 13);
10973 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10974 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10975 ext_attr->qam_if_agc_cfg.min_output_level = 0;
10976 ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF;
10977 ext_attr->qam_if_agc_cfg.speed = 3;
10978 ext_attr->qam_if_agc_cfg.top = 1297;
10979 ext_attr->qam_pga_cfg = 140;
10981 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10982 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10983 ext_attr->vsb_if_agc_cfg.min_output_level = 0;
10984 ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF;
10985 ext_attr->vsb_if_agc_cfg.speed = 3;
10986 ext_attr->vsb_if_agc_cfg.top = 1024;
10987 ext_attr->vsb_pga_cfg = 140;
10992 ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B;
10993 ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10994 ext_attr->qam_rf_agc_cfg.min_output_level = 0;
10995 ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF;
10996 ext_attr->qam_rf_agc_cfg.speed = 3;
10997 ext_attr->qam_rf_agc_cfg.top = 9500;
10998 ext_attr->qam_rf_agc_cfg.cut_off_current = 4000;
10999 ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B;
11000 ext_attr->qam_pre_saw_cfg.reference = 0x07;
11001 ext_attr->qam_pre_saw_cfg.use_pre_saw = true;
11004 ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB;
11005 ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
11006 ext_attr->vsb_rf_agc_cfg.min_output_level = 0;
11007 ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF;
11008 ext_attr->vsb_rf_agc_cfg.speed = 3;
11009 ext_attr->vsb_rf_agc_cfg.top = 9500;
11010 ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000;
11011 ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB;
11012 ext_attr->vsb_pre_saw_cfg.reference = 0x07;
11013 ext_attr->vsb_pre_saw_cfg.use_pre_saw = true;
11023 * \retval -EIO I2C error or other failure
11024 * \retval -EINVAL Invalid mode argument.
11037 common_attr = (struct drx_common_attr *) demod->my_common_attr;
11038 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11039 dev_addr = demod->my_i2c_dev_addr;
11043 return -EINVAL;
11046 if (common_attr->current_power_mode == *mode)
11065 return -EINVAL;
11069 if ((common_attr->current_power_mode != DRX_POWER_UP)) {
11085 /* Set pins with possible pull-ups connected to them in input mode */
11094 switch (ext_attr->standard) {
11118 rc = power_down_atv(demod, ext_attr->standard, true);
11129 return -EIO;
11131 ext_attr->standard = DRX_STANDARD_UNKNOWN;
11154 ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
11163 common_attr->current_power_mode = *mode;
11171 /*== CTRL Set/Get Config related functions ===================================*/
11176 * \brief Set Pre-saw reference.
11192 dev_addr = demod->my_i2c_dev_addr;
11193 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11196 if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M)
11198 return -EINVAL;
11202 if ((ext_attr->standard == pre_saw->standard) ||
11203 (DRXJ_ISQAMSTD(ext_attr->standard) &&
11204 DRXJ_ISQAMSTD(pre_saw->standard)) ||
11205 (DRXJ_ISATVSTD(ext_attr->standard) &&
11206 DRXJ_ISATVSTD(pre_saw->standard))) {
11207 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0);
11214 /* Store pre-saw settings */
11215 switch (pre_saw->standard) {
11217 ext_attr->vsb_pre_saw_cfg = *pre_saw;
11223 ext_attr->qam_pre_saw_cfg = *pre_saw;
11227 return -EINVAL;
11258 return -EINVAL;
11260 dev_addr = demod->my_i2c_dev_addr;
11261 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11263 switch (afe_gain->standard) {
11273 return -EINVAL;
11279 if (afe_gain->gain >= 329)
11281 else if (afe_gain->gain <= 147)
11284 gain = (afe_gain->gain - 140 + 6) / 13;
11287 if (ext_attr->standard == afe_gain->standard) {
11296 switch (afe_gain->standard) {
11298 ext_attr->vsb_pga_cfg = gain * 13 + 140;
11304 ext_attr->qam_pga_cfg = gain * 13 + 140;
11308 return -EIO;
11350 (demod->my_common_attr == NULL) ||
11351 (demod->my_ext_attr == NULL) ||
11352 (demod->my_i2c_dev_addr == NULL) ||
11353 (demod->my_common_attr->is_opened)) {
11354 return -EINVAL;
11358 if (demod->my_ext_attr == NULL)
11359 return -EINVAL;
11361 dev_addr = demod->my_i2c_dev_addr;
11362 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11363 common_attr = (struct drx_common_attr *) demod->my_common_attr;
11371 rc = -EINVAL;
11384 * Soft reset of sys- and osc-clockdomain
11388 * Btw, this is coherent with DRX-K, where we send reset codes
11389 * for modulation (OFTM, in DRX-k), SYS and OSC clock domains.
11429 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
11451 if (common_attr->microcode_file != NULL) {
11454 common_attr->is_opened = true;
11455 ucode_info.mc_file = common_attr->microcode_file;
11457 if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) {
11459 rc = -EINVAL;
11468 if (common_attr->verify_microcode == true) {
11476 common_attr->is_opened = false;
11487 common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT;
11488 common_attr->scan_desired_lock = DRX_LOCKED;
11491 ext_attr->standard = DRX_STANDARD_UNKNOWN;
11536 ext_attr->aud_data = drxj_default_aud_data_g;
11538 demod->my_common_attr->is_opened = true;
11542 common_attr->is_opened = false;
11555 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11559 if ((demod->my_common_attr == NULL) ||
11560 (demod->my_ext_attr == NULL) ||
11561 (demod->my_i2c_dev_addr == NULL) ||
11562 (!demod->my_common_attr->is_opened)) {
11563 return -EINVAL;
11599 * drx_u_code_compute_crc - Compute CRC of block of microcode data.
11627 * drx_check_firmware - checks if the loaded firmware is valid
11709 return -EINVAL;
11713 * drx_ctrl_u_code - Handle microcode upload or verify.
11720 * - In case of UCODE_UPLOAD: code is successfully uploaded.
11721 * - In case of UCODE_VERIFY: image on device is equal to
11723 * -EIO:
11724 * - In case of UCODE_UPLOAD: I2C error.
11725 * - In case of UCODE_VERIFY: I2C error or image on device
11727 * -EINVAL:
11728 * - Invalid arguments.
11729 * - Provided image is corrupt
11735 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11747 if (!mc_info || !mc_info->mc_file)
11748 return -EINVAL;
11750 mc_file = mc_info->mc_file;
11752 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent);
11758 if (fw->size < 2 * sizeof(u16)) {
11759 rc = -EINVAL;
11764 pr_info("Firmware %s, size %zu\n", mc_file, fw->size);
11766 mc_data_init = fw->data;
11767 size = fw->size;
11777 rc = -EINVAL;
11807 (mc_data - mc_data_init), block_hdr.addr,
11811 - data larger than 64Kb
11812 - if CRC enabled check CRC
11819 rc = -EINVAL;
11836 rc = -EIO;
11838 mc_data - mc_data_init);
11862 mc_data - mc_data_init);
11863 rc = -EIO;
11872 mc_data - mc_data_init);
11873 rc = -EIO;
11879 bytes_left -=((u32) bytes_to_comp);
11884 rc = -EINVAL;
11908 /* Configure user-I/O #3: enable read/write */
11934 struct drx39xxj_state *state = fe->demodulator_priv;
11935 struct drx_demod_instance *demod = state->demod;
11955 struct drx39xxj_state *state = fe->demodulator_priv;
11956 struct drx_demod_instance *demod = state->demod;
12003 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12005 if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12010 if (!p->pre_bit_count.stat[0].uvalue) {
12011 if (!p->pre_bit_error.stat[0].uvalue)
12016 *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue,
12017 p->pre_bit_count.stat[0].uvalue);
12025 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12027 if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12032 *strength = p->strength.stat[0].uvalue;
12038 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12041 if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12046 tmp64 = p->cnr.stat[0].svalue;
12054 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12056 if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12061 *ucb = p->block_error.stat[0].uvalue;
12070 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12071 struct drx39xxj_state *state = fe->demodulator_priv;
12072 struct drx_demod_instance *demod = state->demod;
12098 if (fe->ops.tuner_ops.set_params) {
12101 if (fe->ops.i2c_gate_ctrl)
12102 fe->ops.i2c_gate_ctrl(fe, 1);
12105 fe->ops.tuner_ops.set_params(fe);
12108 if (fe->ops.tuner_ops.get_if_frequency) {
12109 fe->ops.tuner_ops.get_if_frequency(fe, &int_freq);
12110 demod->my_common_attr->intermediate_freq = int_freq / 1000;
12113 if (fe->ops.i2c_gate_ctrl)
12114 fe->ops.i2c_gate_ctrl(fe, 0);
12117 switch (p->delivery_system) {
12124 switch (p->modulation) {
12137 return -EINVAL;
12144 return -EINVAL;
12149 channel.frequency = p->frequency / 1000;
12157 return -EINVAL;
12163 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12170 /* power-down the demodulator */
12176 struct drx39xxj_state *state = fe->demodulator_priv;
12177 struct drx_demod_instance *demod = state->demod;
12183 state->i2c_gate_open);
12191 if (state->i2c_gate_open == enable) {
12202 state->i2c_gate_open = enable;
12209 struct drx39xxj_state *state = fe->demodulator_priv;
12210 struct drx_demod_instance *demod = state->demod;
12213 if (fe->exit == DVB_FE_DEVICE_RESUME) {
12215 demod->my_common_attr->is_opened = false;
12227 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
12228 struct drx39xxj_state *state = fe->demodulator_priv;
12229 struct drx_demod_instance *demod = state->demod;
12230 struct drxj_data *ext_attr = demod->my_ext_attr;
12232 if (c->lna) {
12233 if (!ext_attr->has_lna) {
12235 return -EINVAL;
12240 return drxj_set_lna_state(demod, c->lna);
12246 tune->min_delay_ms = 1000;
12252 struct drx39xxj_state *state = fe->demodulator_priv;
12253 struct drx_demod_instance *demod = state->demod;
12256 if (fe->exit != DVB_FE_DEVICE_REMOVED)
12259 kfree(demod->my_ext_attr);
12260 kfree(demod->my_common_attr);
12261 kfree(demod->my_i2c_dev_addr);
12304 state->i2c = i2c;
12305 state->demod = demod;
12308 demod->my_i2c_dev_addr = demod_addr;
12309 demod->my_common_attr = demod_comm_attr;
12310 demod->my_i2c_dev_addr->user_data = state;
12311 demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE;
12312 demod->my_common_attr->verify_microcode = true;
12313 demod->my_common_attr->intermediate_freq = 5000;
12314 demod->my_common_attr->current_power_mode = DRX_POWER_DOWN;
12315 demod->my_ext_attr = demod_ext_attr;
12316 ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE;
12317 demod->i2c = i2c;
12326 memcpy(&state->frontend.ops, &drx39xxj_ops,
12329 state->frontend.demodulator_priv = state;
12331 /* Initialize stats - needed for DVBv5 stats to work */
12332 p = &state->frontend.dtv_property_cache;
12333 p->strength.len = 1;
12334 p->pre_bit_count.len = 1;
12335 p->pre_bit_error.len = 1;
12336 p->post_bit_count.len = 1;
12337 p->post_bit_error.len = 1;
12338 p->block_count.len = 1;
12339 p->block_error.len = 1;
12340 p->cnr.len = 1;
12342 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12343 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12344 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12345 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12346 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12347 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12348 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12349 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12351 return &state->frontend;