Lines Matching +full:gpio +full:- +full:op +full:- +full:cfg
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Linux-DVB Driver for DiBcom's DiB8000 chip (ISDB-T).
22 #define LAYER_ALL -1
66 struct dib8000_config cfg;
149 {.addr = i2c->addr >> 1, .flags = 0, .len = 2},
150 {.addr = i2c->addr >> 1, .flags = I2C_M_RD, .len = 2},
153 if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
158 msg[0].buf = i2c->i2c_write_buffer;
161 msg[1].buf = i2c->i2c_read_buffer;
163 if (i2c_transfer(i2c->adap, msg, 2) != 2)
167 mutex_unlock(i2c->i2c_buffer_lock);
175 state->i2c_write_buffer[0] = reg >> 8;
176 state->i2c_write_buffer[1] = reg & 0xff;
178 memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
179 state->msg[0].addr = state->i2c.addr >> 1;
180 state->msg[0].flags = 0;
181 state->msg[0].buf = state->i2c_write_buffer;
182 state->msg[0].len = 2;
183 state->msg[1].addr = state->i2c.addr >> 1;
184 state->msg[1].flags = I2C_M_RD;
185 state->msg[1].buf = state->i2c_read_buffer;
186 state->msg[1].len = 2;
188 if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2)
191 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
200 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
207 mutex_unlock(&state->i2c_buffer_lock);
216 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
224 mutex_unlock(&state->i2c_buffer_lock);
231 struct i2c_msg msg = {.addr = i2c->addr >> 1, .flags = 0, .len = 4};
234 if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
236 return -EINVAL;
239 msg.buf = i2c->i2c_write_buffer;
245 ret = i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
246 mutex_unlock(i2c->i2c_buffer_lock);
255 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
257 return -EINVAL;
260 state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
261 state->i2c_write_buffer[1] = reg & 0xff;
262 state->i2c_write_buffer[2] = (val >> 8) & 0xff;
263 state->i2c_write_buffer[3] = val & 0xff;
265 memset(&state->msg[0], 0, sizeof(struct i2c_msg));
266 state->msg[0].addr = state->i2c.addr >> 1;
267 state->msg[0].flags = 0;
268 state->msg[0].buf = state->i2c_write_buffer;
269 state->msg[0].len = 4;
271 ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ?
272 -EREMOTEIO : 0);
273 mutex_unlock(&state->i2c_buffer_lock);
288 (832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11,
289 (-931 << 5) | 0x0f
298 (699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12,
299 (-720 << 5) | 0x0d
303 (664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e,
304 (-610 << 5) | 0x0a
308 (-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f,
309 (-922 << 5) | 0x0d
313 (638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d,
314 (-655 << 5) | 0x0a
318 (-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14,
319 (-958 << 5) | 0x13
323 (-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12,
324 (-568 << 5) | 0x0f
328 (-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14,
329 (-848 << 5) | 0x13
333 (612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12,
334 (-869 << 5) | 0x13
338 (-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13,
339 (-598 << 5) | 0x10
353 (-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15,
354 (-877 << 5) | 0x15
358 (-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18,
359 (-921 << 5) | 0x14
376 396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
382 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
407 struct dib8000_state *state = fe->demodulator_priv;
410 state->output_mode = mode;
415 dprintk("-I- Setting output mode for demod %p to %d\n",
416 &state->fe[0], mode);
429 if (state->cfg.hostbus_diversity) {
451 &state->fe[0]);
452 return -EINVAL;
455 if (state->cfg.output_mpeg2_in_188_bytes)
468 struct dib8000_state *state = fe->demodulator_priv;
472 if (!state->differential_constellation) {
479 state->diversity_onoff = onoff;
482 case 0: /* only use the internal way - not the diversity input */
496 if (state->revision == 0x8002) {
512 if (state->revision != 0x8090)
525 if (state->revision != 0x8090)
531 if (state->revision != 0x8090)
554 if (state->revision != 0x8090) {
580 if (state->revision == 0x8090) {
619 struct dib8000_state *state = fe->demodulator_priv;
625 if (state->timf == 0) {
627 timf = state->timf_default;
630 timf = state->timf;
643 if (state->revision == 0x8090) {
665 struct dib8000_state *state = fe->demodulator_priv;
668 state->wbd_ref = value;
674 dprintk("ifreq: %d %x, inversion: %d\n", bw->ifreq, bw->ifreq, bw->ifreq >> 25);
675 if (state->revision != 0x8090) {
677 (u16) (((bw->internal * 1000) >> 16) & 0xffff));
679 (u16) ((bw->internal * 1000) & 0xffff));
681 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff));
683 (u16) ((bw->internal / 2 * 1000) & 0xffff));
685 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff));
686 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff));
687 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003));
689 if (state->revision != 0x8090)
690 dib8000_write_word(state, 922, bw->sad_cfg);
695 const struct dibx000_bandwidth_config *pll = state->cfg.pll;
698 if (state->revision != 0x8090) {
700 (pll->pll_prediv << 8) | (pll->pll_ratio << 0));
702 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
703 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) |
704 (1 << 3) | (pll->pll_range << 1) |
705 (pll->pll_reset << 0);
708 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
714 if (state->cfg.pll->ADClkSrc == 0)
717 (pll->modulo << 8) |
718 (pll->ADClkSrc << 7) | (0 << 1));
719 else if (state->cfg.refclksel != 0)
721 ((state->cfg.refclksel & 0x3) << 10) |
722 (pll->modulo << 8) |
723 (pll->ADClkSrc << 7) | (0 << 1));
726 (3 << 10) | (pll->modulo << 8) |
727 (pll->ADClkSrc << 7) | (0 << 1));
729 dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |
730 (pll->pll_range<<12) | (pll->pll_ratio<<6) |
731 (pll->pll_prediv));
734 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));
739 dib8000_write_word(state, 904, (pll->modulo << 8));
748 struct dib8000_state *state = fe->demodulator_priv;
750 u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ;
757 if ((pll == NULL) || (pll->pll_prediv == prediv &&
758 pll->pll_ratio == loopdiv))
759 return -EINVAL;
761 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio);
762 if (state->revision == 0x8090) {
769 ((pll->pll_ratio & 0x3f) << 6) |
770 (pll->pll_prediv & 0x3f));
776 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;
794 if (bw != state->current_demod_bw) {
796 dprintk("PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)\n", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv);
798 if (state->cfg.pll->pll_prediv != oldprediv) {
802 dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio);
807 ratio = state->cfg.pll->pll_ratio;
809 state->current_demod_bw = bw;
814 dprintk("PLL: Update ratio (prediv: %d, ratio: %d)\n", state->cfg.pll->pll_prediv, ratio);
815 dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL ratio is updated. */
825 dib8000_write_word(st, 1029, st->cfg.gpio_dir);
826 dib8000_write_word(st, 1030, st->cfg.gpio_val);
830 dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos);
832 dib8000_write_word(st, 1037, st->cfg.pwm_freq_div);
838 st->cfg.gpio_dir = dib8000_read_word(st, 1029);
839 st->cfg.gpio_dir &= ~(1 << num); /* reset the direction bit */
840 st->cfg.gpio_dir |= (dir & 0x1) << num; /* set the new direction */
841 dib8000_write_word(st, 1029, st->cfg.gpio_dir);
843 st->cfg.gpio_val = dib8000_read_word(st, 1030);
844 st->cfg.gpio_val &= ~(1 << num); /* reset the direction bit */
845 st->cfg.gpio_val |= (val & 0x01) << num; /* set the new value */
846 dib8000_write_word(st, 1030, st->cfg.gpio_val);
848 dprintk("gpio dir: %x: gpio val: %x\n", st->cfg.gpio_dir, st->cfg.gpio_val);
855 struct dib8000_state *state = fe->demodulator_priv;
860 /* auto search configuration - lock0 by default waiting
884 11, 80, /* set ADC level to -16 */
885 (1 << 13) - 825 - 117,
886 (1 << 13) - 837 - 117,
887 (1 << 13) - 811 - 117,
888 (1 << 13) - 766 - 117,
889 (1 << 13) - 737 - 117,
890 (1 << 13) - 693 - 117,
891 (1 << 13) - 648 - 117,
892 (1 << 13) - 619 - 117,
893 (1 << 13) - 575 - 117,
894 (1 << 13) - 531 - 117,
895 (1 << 13) - 501 - 117,
997 struct dib8000_state *state = fe->demodulator_priv;
998 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
1001 memset(&c->strength, 0, sizeof(c->strength));
1002 memset(&c->cnr, 0, sizeof(c->cnr));
1003 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
1004 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
1005 memset(&c->block_error, 0, sizeof(c->block_error));
1007 c->strength.len = 1;
1008 c->cnr.len = 1;
1009 c->block_error.len = 1;
1010 c->block_count.len = 1;
1011 c->post_bit_error.len = 1;
1012 c->post_bit_count.len = 1;
1014 c->strength.stat[0].scale = FE_SCALE_DECIBEL;
1015 c->strength.stat[0].uvalue = 0;
1017 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1018 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1019 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1020 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1021 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1025 state->init_ucb = -ucb;
1026 state->ber_jiffies_stats = 0;
1027 state->per_jiffies_stats = 0;
1028 memset(&state->ber_jiffies_stats_layer, 0,
1029 sizeof(state->ber_jiffies_stats_layer));
1034 struct dib8000_state *state = fe->demodulator_priv;
1036 if ((state->revision = dib8000_identify(&state->i2c)) == 0)
1037 return -EINVAL;
1040 if (state->revision != 0x8090)
1043 if (state->revision == 0x8000)
1046 dibx000_reset_i2c_master(&state->i2c_master);
1050 /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */
1058 if (state->revision == 0x8090)
1072 if (state->revision != 0x8090) {
1073 if (state->cfg.drives)
1074 dib8000_write_word(state, 906, state->cfg.drives);
1076 dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal.\n");
1077 /* min drive SDRAM - not optimal - adjust */
1083 if (state->revision != 0x8090)
1087 dprintk("GPIO reset was not successful.\n");
1089 if ((state->revision != 0x8090) &&
1093 state->current_agc = NULL;
1097 if (state->cfg.pll->ifreq == 0)
1112 } while (--l);
1117 state->isdbt_cfg_loaded = 0;
1120 if ((state->revision != 8090) && (state->cfg.div_cfg != 0))
1121 dib8000_write_word(state, 903, state->cfg.div_cfg);
1130 if (state->revision != 0x8090)
1154 if (state->cfg.update_lna) {
1155 // read dyn_gain here (because it is demod-dependent and not tuner)
1158 if (state->cfg.update_lna(state->fe[0], dyn_gain)) {
1172 if (state->current_band == band && state->current_agc != NULL)
1174 state->current_band = band;
1176 for (i = 0; i < state->cfg.agc_config_count; i++)
1177 if (state->cfg.agc[i].band_caps & band) {
1178 agc = &state->cfg.agc[i];
1184 return -EINVAL;
1187 state->current_agc = agc;
1190 dib8000_write_word(state, 76, agc->setup);
1191 dib8000_write_word(state, 77, agc->inv_gain);
1192 dib8000_write_word(state, 78, agc->time_stabiliz);
1193 dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock);
1196 dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp);
1197 dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp);
1200 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
1203 if (state->wbd_ref != 0)
1204 dib8000_write_word(state, 106, state->wbd_ref);
1206 dib8000_write_word(state, 106, agc->wbd_ref);
1208 if (state->revision == 0x8090) {
1210 dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2));
1213 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
1214 dib8000_write_word(state, 108, agc->agc1_max);
1215 dib8000_write_word(state, 109, agc->agc1_min);
1216 dib8000_write_word(state, 110, agc->agc2_max);
1217 dib8000_write_word(state, 111, agc->agc2_min);
1218 dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
1219 dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
1220 dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
1221 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
1223 dib8000_write_word(state, 75, agc->agc1_pt3);
1224 if (state->revision != 0x8090)
1227 (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
1234 struct dib8000_state *state = fe->demodulator_priv;
1236 dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000)));
1243 if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
1249 if (agc > state->current_agc->split.min_thres)
1250 split_offset = state->current_agc->split.min;
1251 else if (agc < state->current_agc->split.max_thres)
1252 split_offset = state->current_agc->split.max;
1254 split_offset = state->current_agc->split.max *
1255 (agc - state->current_agc->split.min_thres) /
1256 (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
1267 struct dib8000_state *state = fe->demodulator_priv;
1268 enum frontend_tune_state *tune_state = &state->tune_state;
1275 // set power-up level: interf+analog+AGC
1277 if (state->revision != 0x8090)
1295 if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) {
1297 state->status = FE_STATUS_TUNE_FAILED;
1307 if (state->cfg.agc_control)
1308 state->cfg.agc_control(fe, 1);
1331 if (state->cfg.agc_control)
1332 state->cfg.agc_control(fe, 0);
1387 if ((syncFreq & ((1 << quantif) - 1)) != 0)
1393 syncFreq = syncFreq - 1;
1468 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
1528 struct dib8000_state *state = fe->demodulator_priv;
1532 case 0: /* only use the internal way - not the diversity input */
1547 state->input_mode_mpeg = 1;
1553 state->input_mode_mpeg = 0;
1557 dib8000_set_diversity_in(state->fe[0], onoff);
1563 struct dib8000_state *state = fe->demodulator_priv;
1568 state->output_mode = mode;
1641 state->cfg.output_mpeg2_in_188_bytes);
1642 if (state->cfg.output_mpeg2_in_188_bytes)
1655 if (msg->buf[0] <= 15)
1656 msg->buf[0] -= 1;
1657 else if (msg->buf[0] == 17)
1658 msg->buf[0] = 15;
1659 else if (msg->buf[0] == 16)
1660 msg->buf[0] = 17;
1661 else if (msg->buf[0] == 19)
1662 msg->buf[0] = 16;
1663 else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
1664 msg->buf[0] -= 3;
1665 else if (msg->buf[0] == 28)
1666 msg->buf[0] = 23;
1667 else if (msg->buf[0] == 99)
1668 msg->buf[0] = 99;
1670 return -EINVAL;
1684 i--;
1705 i--;
1714 i--;
1888 struct dib8000_state *st = fe->demodulator_priv;
1889 return &st->dib8096p_tuner_adap;
1894 struct dib8000_state *state = fe->demodulator_priv;
1903 state->tuner_enable = en_cur_state ;
1908 if (state->tuner_enable != 0)
1909 en_cur_state = state->tuner_enable;
1924 struct dib8000_state *state = fe->demodulator_priv;
1934 ix = (u8)((mant-1000)/100); /* index of the LUT */
1935 val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908);
1943 struct dib8000_state *state = fe->demodulator_priv;
1955 val -= 1024;
1962 u32 timf = state->timf = dib8000_read32(state, 435);
1966 dprintk("Updated timing frequency: %d (default: %d)\n", state->timf, state->timf_default);
1969 static u32 dib8000_ctrl_timf(struct dvb_frontend *fe, uint8_t op, uint32_t timf)
1971 struct dib8000_state *state = fe->demodulator_priv;
1973 switch (op) {
1975 state->timf = timf;
1983 dib8000_set_bandwidth(state->fe[0], 6000);
1985 return state->timf;
1997 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
1999 switch (c->layer[layer_index].modulation) {
2015 switch (c->layer[layer_index].fec) {
2034 time_intlv = fls(c->layer[layer_index].interleaving);
2035 if (time_intlv > 3 && !(time_intlv == 4 && c->isdbt_sb_mode == 1))
2038 dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment_count & 0xf) << 6) | (cr << 3) | time_intlv);
2039 if (c->layer[layer_index].segment_count > 0) {
2043 if (c->layer[layer_index].modulation == QAM_16 || c->layer[layer_index].modulation == QAM_64)
2044 max_constellation = c->layer[layer_index].modulation;
2047 if (c->layer[layer_index].modulation == QAM_64)
2048 max_constellation = c->layer[layer_index].modulation;
2056 static const u16 adp_Q64[4] = {0x0148, 0xfff0, 0x00a4, 0xfff8}; /* P_adp_regul_cnt 0.04, P_adp_noise_cnt -0.002, P_adp_regul_ext 0.02, P_adp_noise_ext -0.001 */
2057 static const u16 adp_Q16[4] = {0x023d, 0xffdf, 0x00a4, 0xfff0}; /* P_adp_regul_cnt 0.07, P_adp_noise_cnt -0.004, P_adp_regul_ext 0.02, P_adp_noise_ext -0.002 */
2058 static const u16 adp_Qdefault[4] = {0x099a, 0xffae, 0x0333, 0xfff8}; /* P_adp_regul_cnt 0.3, P_adp_noise_cnt -0.01, P_adp_regul_ext 0.1, P_adp_noise_ext -0.002 */
2093 if (ana_gain) { /* set -16dB ADC target for ana_gain=-1 */
2096 } else { /* set -22dB ADC target for ana_gain=0 */
2098 dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355);
2106 if (state->isdbt_cfg_loaded == 0)
2144 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
2167 state->seg_mask = 0x1fff; /* All 13 segments enabled */
2169 /* ---- COFF ---- Carloff, the most robust --- */
2170 if (state->isdbt_cfg_loaded == 0) { /* if not Sound Broadcasting mode : put default values for 13 segments */
2196 if (state->cfg.pll->ifreq == 0)
2197 dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */
2214 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2216 dib8000_write_word(state, 352, state->seg_diff_mask);
2217 dib8000_write_word(state, 353, state->seg_mask);
2219 /* P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5 */
2220 dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5);
2222 if (c->isdbt_sb_mode) {
2223 /* ---- SMALL ---- */
2224 switch (c->transmission_mode) {
2226 if (c->isdbt_partial_reception == 0) { /* 1-seg */
2227 if (c->layer[0].modulation == DQPSK) /* DQPSK */
2231 } else { /* 3-segments */
2232 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
2233 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2238 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2246 if (c->isdbt_partial_reception == 0) { /* 1-seg */
2247 if (c->layer[0].modulation == DQPSK) /* DQPSK */
2251 } else { /* 3-segments */
2252 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
2253 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2258 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2268 if (c->isdbt_partial_reception == 0) { /* 1-seg */
2269 if (c->layer[0].modulation == DQPSK) /* DQPSK */
2273 } else { /* 3-segments */
2274 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
2275 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2280 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2298 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2302 if (c->transmission_mode == TRANSMISSION_MODE_2K || c->transmission_mode == TRANSMISSION_MODE_4K) {
2310 if (c->isdbt_partial_reception == 1) /* 3-segments */
2311 state->seg_mask = 0x00E0;
2312 else /* 1-segment */
2313 state->seg_mask = 0x0040;
2317 /* ---- COFF ---- Carloff, the most robust --- */
2319 dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partial_reception & 1) << 2) | 0x3);
2325 if (c->isdbt_partial_reception == 0) {
2326 /* P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width = (P_mode == 3) , P_coff_one_seg_sym = (P_mode-1) */
2327 if (state->mode == 3)
2328 dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14));
2330 dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14));
2345 if (c->isdbt_partial_reception == 0 && c->transmission_mode == TRANSMISSION_MODE_2K)
2359 dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh */
2361 if (c->isdbt_partial_reception == 0)
2373 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2376 c->isdbt_partial_reception = 1;
2382 state->mode = fft_to_mode(state);
2386 dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3));
2388 dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_reception & 1) << 5) | ((c->isdbt_sb_mode & 1) << 4));
2391 if (c->isdbt_partial_reception) {
2392 state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0];
2394 nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count;
2396 state->seg_diff_mask |= 1 << permu_seg[i+1];
2399 nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count;
2401 state->seg_diff_mask |= 1 << permu_seg[i];
2404 if (state->seg_diff_mask)
2412 state->layer_b_nb_seg = c->layer[1].segment_count;
2413 state->layer_c_nb_seg = c->layer[2].segment_count;
2417 dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask);
2419 state->differential_constellation = (state->seg_diff_mask != 0);
2427 /* ---- ANA_FE ---- */
2428 if (c->isdbt_partial_reception) /* 3-segments */
2431 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_1seg); /* 1-segment */
2434 if (c->isdbt_sb_mode) {
2437 c->isdbt_sb_subchannel);
2448 /* ---- CHAN_BLK ---- */
2450 if ((((~state->seg_diff_mask) >> i) & 1) == 1) {
2451 p_cfr_left_edge += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i - 1)) & 1) == 0));
2452 p_cfr_right_edge += (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i + 1)) & 1) == 0));
2459 dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */
2460 dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */
2461 dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */
2464 dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */
2468 dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */
2469 dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */
2473 /* ---- TMCC ---- */
2475 tmcc_pow += (((c->layer[i].modulation == DQPSK) * 4 + 1) * c->layer[i].segment_count) ;
2479 tmcc_pow *= (1 << (9-2));
2485 /* ---- PHA3 ---- */
2486 if (state->isdbt_cfg_loaded == 0)
2489 state->isdbt_cfg_loaded = 0;
2500 if (state->revision == 0x8090)
2516 struct dib8000_state *state = fe->demodulator_priv;
2517 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2519 u32 value, internal = state->cfg.pll->internal;
2521 if (state->revision == 0x8090)
2524 if ((state->revision >= 0x8002) &&
2525 (state->autosearch_state == AS_SEARCHING_FFT)) {
2536 if (state->revision == 0x8090)
2548 if (state->revision == 0x8090)
2561 } else if ((state->revision >= 0x8002) &&
2562 (state->autosearch_state == AS_SEARCHING_GUARD)) {
2563 c->transmission_mode = TRANSMISSION_MODE_8K;
2564 c->guard_interval = GUARD_INTERVAL_1_8;
2565 c->inversion = 0;
2566 c->layer[0].modulation = QAM_64;
2567 c->layer[0].fec = FEC_2_3;
2568 c->layer[0].interleaving = 0;
2569 c->layer[0].segment_count = 13;
2572 c->transmission_mode = state->found_nfft;
2578 if (state->revision == 0x8090)
2585 if (state->revision == 0x8090)
2601 c->inversion = 0;
2602 c->layer[0].modulation = QAM_64;
2603 c->layer[0].fec = FEC_2_3;
2604 c->layer[0].interleaving = 0;
2605 c->layer[0].segment_count = 13;
2606 if (!c->isdbt_sb_mode)
2607 c->layer[0].segment_count = 13;
2610 if (c->isdbt_sb_mode) {
2614 if (c->guard_interval == GUARD_INTERVAL_AUTO) {
2615 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
2616 c->transmission_mode = TRANSMISSION_MODE_8K;
2617 c->guard_interval = GUARD_INTERVAL_1_8;
2621 c->guard_interval = GUARD_INTERVAL_1_8;
2625 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
2626 c->transmission_mode = TRANSMISSION_MODE_8K;
2639 if (state->revision == 0x8090)
2646 if (state->revision == 0x8090)
2661 struct dib8000_state *state = fe->demodulator_priv;
2664 if ((state->revision >= 0x8002) &&
2665 (state->autosearch_state == AS_SEARCHING_FFT)) {
2700 u32 dds = state->cfg.pll->ifreq & 0x1ffffff;
2701 u8 invert = !!(state->cfg.pll->ifreq & (1 << 25));
2704 if (state->revision == 0x8090) {
2711 dds = (1 << 26) - (abs_offset_khz * unit_khz_dds_val);
2716 dds = (1<<26) - dds;
2719 unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal);
2722 unit_khz_dds_val *= -1;
2726 dds -= abs_offset_khz * unit_khz_dds_val;
2731 dprintk("setting a DDS frequency offset of %c%dkHz\n", invert ? '-' : ' ', dds / unit_khz_dds_val);
2733 if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) {
2743 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2748 if (state->fe[0]->ops.tuner_ops.get_frequency)
2749 state->fe[0]->ops.tuner_ops.get_frequency(state->fe[0], ¤t_rf);
2751 current_rf = c->frequency;
2753 total_dds_offset_khz = (int)current_rf - (int)c->frequency / 1000;
2755 if (c->isdbt_sb_mode) {
2756 state->subchannel = c->isdbt_sb_subchannel;
2759 dib8000_write_word(state, 26, c->inversion ^ i);
2761 if (state->cfg.pll->ifreq == 0) { /* low if tuner */
2762 if ((c->inversion ^ i) == 0)
2765 if ((c->inversion ^ i) == 0)
2766 total_dds_offset_khz *= -1;
2770 dprintk("%dkhz tuner offset (frequency = %dHz & current_rf = %dHz) total_dds_offset_hz = %d\n", c->frequency - current_rf, c->frequency, current_rf, total_dds_offset_khz);
2780 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2783 switch (c->transmission_mode) {
2797 return (LUT_isdbt_symbol_duration[i] / (c->bandwidth_hz / 1000)) + 1;
2802 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2807 if (c->isdbt_sb_mode) {
2808 if (c->isdbt_partial_reception == 0) {
2809 reg_32 = ((11 - state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x40 */
2810 reg_37 = (3 << 5) | (0 << 4) | (10 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (10-P_mode) */
2812 reg_32 = ((10 - state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_corm_thres=0x60 */
2813 reg_37 = (3 << 5) | (0 << 4) | (9 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (9-P_mode) */
2815 } else { /* 13-seg start conf offset loop parameters */
2816 reg_32 = ((9 - state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */
2817 reg_37 = (3 << 5) | (0 << 4) | (8 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = 9 */
2821 if (c->isdbt_sb_mode) {
2822 if (c->isdbt_partial_reception == 0) { /* Sound Broadcasting mode 1 seg */
2823 reg_32 = ((13-state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40*/
2824 reg_37 = (12-state->mode) | ((5 + state->mode) << 5);
2826 reg_32 = ((12-state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_corm_thres=0x60 */
2827 reg_37 = (11-state->mode) | ((5 + state->mode) << 5);
2830 reg_32 = ((11-state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_thres=0x80 */
2831 reg_37 = ((5+state->mode) << 5) | (10 - state->mode);
2848 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2851 /* P_dvsy_sync_wait - reuse mode */
2852 switch (c->transmission_mode) {
2865 if (state->cfg.diversity_delay == 0)
2866 sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + 48; /* add 50% SFN margin + compensate for one DVSY-fifo */
2868 sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + state->cfg.diversity_delay; /* add 50% SFN margin + compensate for DVSY-fifo */
2876 delay *= state->symbol_duration;
2883 struct dib8000_state *state = fe->demodulator_priv;
2884 return state->status;
2889 struct dib8000_state *state = fe->demodulator_priv;
2890 return state->tune_state;
2895 struct dib8000_state *state = fe->demodulator_priv;
2897 state->tune_state = tune_state;
2903 struct dib8000_state *state = fe->demodulator_priv;
2905 state->status = FE_STATUS_TUNE_PENDING;
2906 state->tune_state = CT_DEMOD_START;
2912 struct dib8000_state *state = fe->demodulator_priv;
2914 if (state->revision == 0x8090)
2937 * is_manual_mode - Check if TMCC should be used for parameters settings
2945 * It requires that both per-layer and per-transponder parameters to be
2955 /* Use auto mode on DVB-T compat mode */
2956 if (c->delivery_system != SYS_ISDBT)
2962 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
2970 if (c->guard_interval == GUARD_INTERVAL_AUTO) {
2979 if (!c->isdbt_layer_enabled) {
2985 * Check if the per-layer parameters aren't auto and
2989 if (!(c->isdbt_layer_enabled & 1 << i))
2992 if ((c->layer[i].segment_count > 13) ||
2993 (c->layer[i].segment_count == 0)) {
2994 c->isdbt_layer_enabled &= ~(1 << i);
2998 n_segs += c->layer[i].segment_count;
3000 if ((c->layer[i].modulation == QAM_AUTO) ||
3001 (c->layer[i].fec == FEC_AUTO)) {
3023 struct dib8000_state *state = fe->demodulator_priv;
3024 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
3025 enum frontend_tune_state *tune_state = &state->tune_state;
3030 unsigned long *timeout = &state->timeout;
3043 state->channel_parameters_set, *tune_state, state->autosearch_state, now);
3050 if (state->revision == 0x8090)
3052 state->status = FE_STATUS_TUNE_PENDING;
3053 state->channel_parameters_set = is_manual_mode(c);
3056 state->channel_parameters_set ? "manual" : "auto");
3064 dib8000_set_bandwidth(fe, c->bandwidth_hz / 1000);
3066 if (state->channel_parameters_set == 0) { /* The channel struct is unknown, search it ! */
3068 if (state->revision != 0x8090) {
3069 state->agc1_max = dib8000_read_word(state, 108);
3070 state->agc1_min = dib8000_read_word(state, 109);
3071 state->agc2_max = dib8000_read_word(state, 110);
3072 state->agc2_min = dib8000_read_word(state, 111);
3081 state->autosearch_state = AS_SEARCHING_FFT;
3082 state->found_nfft = TRANSMISSION_MODE_AUTO;
3083 state->found_guard = GUARD_INTERVAL_AUTO;
3086 state->autosearch_state = AS_DONE;
3089 state->symbol_duration = dib8000_get_symbol_duration(state);
3094 if (state->revision == 0x8090)
3104 state->status = FE_STATUS_TUNE_FAILED;
3105 state->autosearch_state = AS_DONE;
3109 state->status = FE_STATUS_FFT_SUCCESS; /* signal to the upper layer, that there was a channel found and the parameters can be read */
3111 if (state->autosearch_state == AS_SEARCHING_GUARD)
3114 state->autosearch_state = AS_DONE;
3123 switch (state->autosearch_state) {
3126 if (state->revision == 0x8090) {
3145 state->found_nfft = TRANSMISSION_MODE_2K;
3148 state->found_nfft = TRANSMISSION_MODE_4K;
3152 state->found_nfft = TRANSMISSION_MODE_8K;
3158 state->autosearch_state = AS_SEARCHING_GUARD;
3159 if (state->revision == 0x8090)
3166 if (state->revision == 0x8090)
3167 state->found_guard = dib8000_read_word(state, 572) & 0x3;
3169 state->found_guard = dib8000_read_word(state, 570) & 0x3;
3170 /* dprintk("guard interval found=%i\n", state->found_guard); */
3176 state->status = FE_STATUS_TUNE_FAILED;
3177 state->autosearch_state = AS_DONE;
3193 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
3203 if (locks & (0x3 << 11)) { /* coff-lock and off_cpil_lock achieved */
3204 dib8000_update_timf(state); /* we achieved a coff_cpil_lock - it's time to update the timf */
3205 if (!state->differential_constellation) {
3218 if ((state->fe[1] != NULL) && (state->output_mode != OUTMODE_DIVERSITY)) {
3220 if (dib8000_get_status(state->fe[1]) <= FE_STATUS_STD_SUCCESS) /* Something is locked on the input fe */
3222 else if (dib8000_get_status(state->fe[1]) >= FE_STATUS_TUNE_TIME_TOO_SHORT) { /* fe in input failed also, break the current one */
3226 state->status = FE_STATUS_TUNE_FAILED;
3232 state->status = FE_STATUS_TUNE_FAILED;
3250 if (c->isdbt_sb_mode
3251 && c->isdbt_sb_subchannel < 14
3252 && !state->differential_constellation) {
3253 state->subchannel = 0;
3257 state->status = FE_STATUS_LOCKED;
3262 if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable of deinterleaving : esram */
3265 if (c->layer[i].interleaving >= deeper_interleaver) {
3266 dprintk("layer%i: time interleaver = %d\n", i, c->layer[i].interleaving);
3267 if (c->layer[i].segment_count > 0) { /* valid layer */
3268 deeper_interleaver = c->layer[0].interleaving;
3269 state->longest_intlv_layer = i;
3281 if (state->diversity_onoff != 0) /* because of diversity sync */
3286 deeper_interleaver, state->longest_intlv_layer, locks, *timeout);
3295 if (locks&(1<<(7-state->longest_intlv_layer))) { /* mpeg lock : check the longest one */
3296 dprintk("ISDB-T layer locks: Layer A %s, Layer B %s, Layer C %s\n",
3297 c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3298 c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3299 c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled");
3300 if (c->isdbt_sb_mode
3301 && c->isdbt_sb_subchannel < 14
3302 && !state->differential_constellation)
3304 state->status = FE_STATUS_DEMOD_SUCCESS;
3306 state->status = FE_STATUS_DATA_LOCKED;
3309 if (c->isdbt_sb_mode
3310 && c->isdbt_sb_subchannel < 14
3311 && !state->differential_constellation) { /* continue to try init prbs autosearch */
3312 state->subchannel += 3;
3316 dprintk("Not all ISDB-T layers locked in %d ms: Layer A %s, Layer B %s, Layer C %s\n",
3317 jiffies_to_msecs(now - *timeout),
3318 c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3319 c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3320 c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled");
3322 state->status = FE_STATUS_DATA_LOCKED;
3324 state->status = FE_STATUS_TUNE_FAILED;
3331 init_prbs = dib8000_get_init_prbs(state, state->subchannel);
3338 state->status = FE_STATUS_TUNE_FAILED;
3346 /* tuning is finished - cleanup the demod */
3350 if ((state->revision != 0x8090) && (state->agc1_max != 0)) {
3351 dib8000_write_word(state, 108, state->agc1_max);
3352 dib8000_write_word(state, 109, state->agc1_min);
3353 dib8000_write_word(state, 110, state->agc2_max);
3354 dib8000_write_word(state, 111, state->agc2_min);
3355 state->agc1_max = 0;
3356 state->agc1_min = 0;
3357 state->agc2_max = 0;
3358 state->agc2_min = 0;
3368 return ret * state->symbol_duration;
3369 if ((ret > 0) && (ret < state->symbol_duration))
3370 return state->symbol_duration; /* at least one symbol */
3376 struct dib8000_state *state = fe->demodulator_priv;
3385 if (state->revision == 0x8090)
3388 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3389 ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);
3399 struct dib8000_state *state = fe->demodulator_priv;
3403 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3404 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
3409 if (state->revision != 0x8090)
3420 struct dib8000_state *state = fe->demodulator_priv;
3425 c->bandwidth_hz = 6000000;
3429 * not lock or not sync. This causes dvbv5-scan/dvbv5-zap to fail.
3437 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3438 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
3442 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], c);
3443 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
3445 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
3446 state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
3447 state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
3448 state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
3449 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
3451 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
3452 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
3453 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
3454 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
3462 c->isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
3464 if (state->revision == 0x8090)
3468 c->inversion = (val & 0x40) >> 6;
3471 c->transmission_mode = TRANSMISSION_MODE_2K;
3475 c->transmission_mode = TRANSMISSION_MODE_4K;
3480 c->transmission_mode = TRANSMISSION_MODE_8K;
3487 c->guard_interval = GUARD_INTERVAL_1_32;
3491 c->guard_interval = GUARD_INTERVAL_1_16;
3496 c->guard_interval = GUARD_INTERVAL_1_8;
3500 c->guard_interval = GUARD_INTERVAL_1_4;
3505 c->isdbt_partial_reception = val & 1;
3506 dprintk("dib8000_get_frontend: partial_reception = %d\n", c->isdbt_partial_reception);
3512 c->layer[i].segment_count = val;
3521 i, c->layer[i].segment_count);
3527 c->layer[i].interleaving = val;
3530 i, c->layer[i].interleaving);
3535 c->layer[i].fec = FEC_1_2;
3540 c->layer[i].fec = FEC_2_3;
3545 c->layer[i].fec = FEC_3_4;
3550 c->layer[i].fec = FEC_5_6;
3555 c->layer[i].fec = FEC_7_8;
3564 c->layer[i].modulation = DQPSK;
3569 c->layer[i].modulation = QPSK;
3574 c->layer[i].modulation = QAM_16;
3580 c->layer[i].modulation = QAM_64;
3588 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3589 state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = c->isdbt_sb_mode;
3590 state->fe[index_frontend]->dtv_property_cache.inversion = c->inversion;
3591 state->fe[index_frontend]->dtv_property_cache.transmission_mode = c->transmission_mode;
3592 state->fe[index_frontend]->dtv_property_cache.guard_interval = c->guard_interval;
3593 state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = c->isdbt_partial_reception;
3595 state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = c->layer[i].segment_count;
3596 state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = c->layer[i].interleaving;
3597 state->fe[index_frontend]->dtv_property_cache.layer[i].fec = c->layer[i].fec;
3598 state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = c->layer[i].modulation;
3606 struct dib8000_state *state = fe->demodulator_priv;
3607 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
3612 if (c->frequency == 0) {
3617 if (c->bandwidth_hz == 0) {
3619 c->bandwidth_hz = 6000000;
3622 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3624 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;
3625 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
3628 if (state->revision != 0x8090) {
3629 dib8000_set_diversity_in(state->fe[index_frontend], 1);
3631 dib8000_set_output_mode(state->fe[index_frontend],
3634 dib8000_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);
3636 dib8096p_set_diversity_in(state->fe[index_frontend], 1);
3638 dib8096p_set_output_mode(state->fe[index_frontend],
3641 dib8096p_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);
3645 if (state->fe[index_frontend]->ops.tuner_ops.set_params)
3646 state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]);
3648 dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);
3652 if (state->revision != 0x8090)
3653 dib8000_set_diversity_in(state->fe[index_frontend - 1], 0);
3655 dib8096p_set_diversity_in(state->fe[index_frontend - 1], 0);
3659 time = dib8000_agc_startup(state->fe[0]);
3660 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3661 time_slave = dib8000_agc_startup(state->fe[index_frontend]);
3681 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3682 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {
3689 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3690 dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
3695 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3696 delay = dib8000_tune(state->fe[index_frontend]);
3704 if (state->channel_parameters_set == 0) { /* searching */
3705 if ((dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_DEMOD_SUCCESS) || (dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_FFT_SUCCESS)) {
3707 dib8000_get_frontend(state->fe[index_frontend], c); /* we read the channel parameters from the frontend which was successful */
3708 state->channel_parameters_set = 1;
3710 for (l = 0; (l < MAX_NUMBER_OF_FRONTENDS) && (state->fe[l] != NULL); l++) {
3713 dib8000_tune_restart_from_demod(state->fe[l]);
3715 state->fe[l]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
3716 state->fe[l]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
3717 state->fe[l]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
3718 state->fe[l]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
3719 state->fe[l]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
3721 state->fe[l]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
3722 state->fe[l]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
3723 state->fe[l]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
3724 state->fe[l]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
3733 if (dib8000_get_status(state->fe[0]) == FE_STATUS_TUNE_FAILED ||
3734 dib8000_get_status(state->fe[0]) == FE_STATUS_LOCKED ||
3735 dib8000_get_status(state->fe[0]) == FE_STATUS_DATA_LOCKED) {
3738 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3739 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_DEMOD_STOP)
3743 dprintk("tuning done with status %d\n", dib8000_get_status(state->fe[0]));
3756 if (state->revision != 0x8090)
3757 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);
3759 dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode);
3760 if (state->cfg.enMpegOutput == 0) {
3773 struct dib8000_state *state = fe->demodulator_priv;
3778 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3779 lock_slave |= dib8000_read_lock(state->fe[index_frontend]);
3815 struct dib8000_state *state = fe->demodulator_priv;
3818 if (state->revision == 0x8090)
3829 struct dib8000_state *state = fe->demodulator_priv;
3832 if (state->revision == 0x8090)
3841 struct dib8000_state *state = fe->demodulator_priv;
3846 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3847 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
3848 if (val > 65535 - *strength)
3854 val = 65535 - dib8000_read_word(state, 390);
3855 if (val > 65535 - *strength)
3864 struct dib8000_state *state = fe->demodulator_priv;
3868 if (state->revision != 0x8090)
3875 exp -= 0x40;
3878 if (state->revision != 0x8090)
3885 exp -= 0x40;
3890 return t + ((s << 16) - n*t) / n;
3897 struct dib8000_state *state = fe->demodulator_priv;
3902 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3903 snr_master += dib8000_get_snr(state->fe[index_frontend]);
3933 * strength generated by a DTA-2111 RF generator directly connected into
3934 * a dib8076 device (a PixelView PV-D231U stick), using a good quality
3939 * Yet, it is better to use this measure in dB than a random non-linear
3945 { 55953, 108500 }, /* -22.5 dBm */
3958 { 50117, 96000 }, /* -35 dBm */
3974 { 42010, 80000 }, /* -51 dBm */
3988 if (value < segments[len-1].x)
3989 return segments[len-1].y;
3991 for (i = 1; i < len - 1; i++) {
4000 dy = segments[i - 1].y - segments[i].y;
4001 dx = segments[i - 1].x - segments[i].x;
4003 tmp64 = value - segments[i].x;
4013 struct dib8000_state *state = fe->demodulator_priv;
4014 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
4029 switch (c->guard_interval) {
4045 switch (c->transmission_mode) {
4060 nsegs = c->layer[i].segment_count;
4064 switch (c->layer[i].modulation) {
4078 switch (c->layer[i].fec) {
4102 interleaving = c->layer[i].interleaving;
4127 struct dib8000_state *state = fe->demodulator_priv;
4128 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
4141 ARRAY_SIZE(strength_to_db_table)) - 131000;
4142 c->strength.stat[0].svalue = db;
4146 c->cnr.len = 1;
4147 c->block_count.len = 1;
4148 c->block_error.len = 1;
4149 c->post_bit_error.len = 1;
4150 c->post_bit_count.len = 1;
4151 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4152 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4153 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4154 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4155 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4160 if (time_after(jiffies, state->per_jiffies_stats)) {
4161 state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
4166 if (state->fe[i])
4167 snr += dib8000_get_snr(state->fe[i]);
4177 c->cnr.stat[0].svalue = snr;
4178 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
4182 if (val < state->init_ucb)
4183 state->init_ucb += 0x100000000LL;
4185 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
4186 c->block_error.stat[0].uvalue = val + state->init_ucb;
4190 time_us = dib8000_get_time_us(fe, -1);
4195 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
4196 c->block_count.stat[0].uvalue += blocks;
4202 /* Get post-BER measures */
4203 if (time_after(jiffies, state->ber_jiffies_stats)) {
4204 time_us = dib8000_get_time_us(fe, -1);
4205 state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
4210 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
4211 c->post_bit_error.stat[0].uvalue += val;
4213 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
4214 c->post_bit_count.stat[0].uvalue += 100000000;
4217 if (state->revision < 0x8002)
4220 c->block_error.len = 4;
4221 c->post_bit_error.len = 4;
4222 c->post_bit_count.len = 4;
4225 unsigned nsegs = c->layer[i].segment_count;
4232 if (time_after(jiffies, state->ber_jiffies_stats_layer[i])) {
4235 state->ber_jiffies_stats_layer[i] = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
4240 c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
4241 c->post_bit_error.stat[1 + i].uvalue += val;
4243 c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
4244 c->post_bit_count.stat[1 + i].uvalue += 100000000;
4250 c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER;
4251 c->block_error.stat[1 + i].uvalue += val;
4258 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
4259 c->block_count.stat[0].uvalue += blocks;
4268 struct dib8000_state *state = fe->demodulator_priv;
4271 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
4275 state->fe[index_frontend] = fe_slave;
4280 return -ENOMEM;
4285 struct dib8000_state *state = fe->demodulator_priv;
4289 return state->fe[slave_index];
4302 return -ENOMEM;
4307 ret = -ENOMEM;
4313 ret = -ENOMEM;
4318 for (k = no_of_demods - 1; k >= 0; k--) {
4332 ret = -EINVAL;
4337 /* start diversity to pull_down div_str - just for i2c-enumeration */
4355 /* deactivate div - it was just for i2c-enumeration */
4371 tune->min_delay_ms = 1000;
4372 tune->step_size = 0;
4373 tune->max_drift = 0;
4379 struct dib8000_state *st = fe->demodulator_priv;
4382 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
4383 dvb_frontend_detach(st->fe[index_frontend]);
4385 dibx000_exit_i2c_master(&st->i2c_master);
4386 i2c_del_adapter(&st->dib8096p_tuner_adap);
4387 kfree(st->fe[0]);
4393 struct dib8000_state *st = fe->demodulator_priv;
4394 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
4399 struct dib8000_state *st = fe->demodulator_priv;
4409 struct dib8000_state *st = fe->demodulator_priv;
4417 .name = "DiBcom 8000 ISDB-T",
4444 static struct dvb_frontend *dib8000_init(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
4458 memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));
4459 state->i2c.adap = i2c_adap;
4460 state->i2c.addr = i2c_addr;
4461 state->i2c.i2c_write_buffer = state->i2c_write_buffer;
4462 state->i2c.i2c_read_buffer = state->i2c_read_buffer;
4463 mutex_init(&state->i2c_buffer_lock);
4464 state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock;
4465 state->gpio_val = cfg->gpio_val;
4466 state->gpio_dir = cfg->gpio_dir;
4471 if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
4472 state->cfg.output_mode = OUTMODE_MPEG2_FIFO;
4474 state->fe[0] = fe;
4475 fe->demodulator_priv = state;
4476 memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));
4478 state->timf_default = cfg->pll->timf;
4480 if (dib8000_identify(&state->i2c) == 0) {
4485 dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr);
4488 strscpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface",
4489 sizeof(state->dib8096p_tuner_adap.name));
4490 state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo;
4491 state->dib8096p_tuner_adap.algo_data = NULL;
4492 state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent;
4493 i2c_set_adapdata(&state->dib8096p_tuner_adap, state);
4494 i2c_add_adapter(&state->dib8096p_tuner_adap);
4499 state->current_demod_bw = 6000;
4513 ops->pwm_agc_reset = dib8000_pwm_agc_reset;
4514 ops->get_dc_power = dib8090p_get_dc_power;
4515 ops->set_gpio = dib8000_set_gpio;
4516 ops->get_slave_frontend = dib8000_get_slave_frontend;
4517 ops->set_tune_state = dib8000_set_tune_state;
4518 ops->pid_filter_ctrl = dib8000_pid_filter_ctrl;
4519 ops->get_adc_power = dib8000_get_adc_power;
4520 ops->update_pll = dib8000_update_pll;
4521 ops->tuner_sleep = dib8096p_tuner_sleep;
4522 ops->get_tune_state = dib8000_get_tune_state;
4523 ops->get_i2c_tuner = dib8096p_get_i2c_tuner;
4524 ops->set_slave_frontend = dib8000_set_slave_frontend;
4525 ops->pid_filter = dib8000_pid_filter;
4526 ops->ctrl_timf = dib8000_ctrl_timf;
4527 ops->init = dib8000_init;
4528 ops->get_i2c_master = dib8000_get_i2c_master;
4529 ops->i2c_enumeration = dib8000_i2c_enumeration;
4530 ops->set_wbd_ref = dib8000_set_wbd_ref;
4537 MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator");