Lines Matching +full:gpio +full:- +full:op +full:- +full:cfg
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Linux-DVB Driver for DiBcom's second generation DiB7000P (PC).
5 * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
27 MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
37 struct dib7000p_config cfg;
99 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
104 state->i2c_write_buffer[0] = reg >> 8;
105 state->i2c_write_buffer[1] = reg & 0xff;
107 memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
108 state->msg[0].addr = state->i2c_addr >> 1;
109 state->msg[0].flags = 0;
110 state->msg[0].buf = state->i2c_write_buffer;
111 state->msg[0].len = 2;
112 state->msg[1].addr = state->i2c_addr >> 1;
113 state->msg[1].flags = I2C_M_RD;
114 state->msg[1].buf = state->i2c_read_buffer;
115 state->msg[1].len = 2;
117 if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2)
120 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
121 mutex_unlock(&state->i2c_buffer_lock);
129 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
131 return -EINVAL;
134 state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
135 state->i2c_write_buffer[1] = reg & 0xff;
136 state->i2c_write_buffer[2] = (val >> 8) & 0xff;
137 state->i2c_write_buffer[3] = val & 0xff;
139 memset(&state->msg[0], 0, sizeof(struct i2c_msg));
140 state->msg[0].addr = state->i2c_addr >> 1;
141 state->msg[0].flags = 0;
142 state->msg[0].buf = state->i2c_write_buffer;
143 state->msg[0].len = 4;
145 ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ?
146 -EREMOTEIO : 0);
147 mutex_unlock(&state->i2c_buffer_lock);
162 } while (--l);
176 dprintk("setting output mode for demod %p to %d\n", &state->demod, mode);
189 if (state->cfg.hostbus_diversity)
206 dprintk("Unhandled output_mode passed to be set for demod %p\n", &state->demod);
210 if (state->cfg.output_mpeg2_in_188_bytes)
215 if (state->version != SOC7090)
223 struct dib7000p_state *state = demod->demodulator_priv;
225 if (state->div_force_off) {
226 dprintk("diversity combination deactivated - forced by COFDM parameters\n");
230 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
232 state->div_state = (u8) onoff;
259 if (state->version == SOC7090)
266 /* dem, cfg, iqc, sad, agc */
271 if (state->version != SOC7090)
276 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
278 if (state->version == SOC7090)
284 /* TODO following stuff is just converted from the dib7000-driver - check when is used what */
291 if (state->version != SOC7090)
302 if (state->version != SOC7090) {
309 if (state->version == SOC7090) {
328 if (state->version == SOC7090) {
359 reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4;
360 reg_908 |= (state->cfg.enable_current_mirror & 1) << 7;
362 if (state->version != SOC7090) {
373 state->current_bandwidth = bw;
375 if (state->timf == 0) {
377 timf = state->cfg.bw->timf;
380 timf = state->timf;
396 if (state->version == SOC7090)
412 struct dib7000p_state *state = demod->demodulator_priv;
415 state->wbd_ref = value;
422 struct dib7000p_state *state = fe->demodulator_priv;
438 struct dib7000p_state *state = fe->demodulator_priv;
444 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
447 if (state->version == SOC7090) {
448 dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
453 dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15));
456 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
457 (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);
462 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
463 clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);
467 dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff));
468 dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff));
469 dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff));
470 dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff));
472 dib7000p_write_word(state, 72, bw->sad_cfg);
486 struct dib7000p_state *state = fe->demodulator_priv;
495 if (loopdiv && bw && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {
496 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
501 dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
506 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */
517 return -EIO;
523 dprintk("gpio dir: %x: val: %x, pwm_pos: %x\n", st->gpio_dir, st->gpio_val, st->cfg.gpio_pwm_pos);
525 dib7000p_write_word(st, 1029, st->gpio_dir);
526 dib7000p_write_word(st, 1030, st->gpio_val);
530 dib7000p_write_word(st, 1032, st->cfg.gpio_pwm_pos);
532 dib7000p_write_word(st, 1037, st->cfg.pwm_freq_div);
538 st->gpio_dir = dib7000p_read_word(st, 1029);
539 st->gpio_dir &= ~(1 << num); /* reset the direction bit */
540 st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
541 dib7000p_write_word(st, 1029, st->gpio_dir);
543 st->gpio_val = dib7000p_read_word(st, 1030);
544 st->gpio_val &= ~(1 << num); /* reset the direction bit */
545 st->gpio_val |= (val & 0x01) << num; /* set the new value */
546 dib7000p_write_word(st, 1030, st->gpio_val);
553 struct dib7000p_state *state = demod->demodulator_priv;
581 /* set ADC level to -16 */
583 (1 << 13) - 825 - 117,
584 (1 << 13) - 837 - 117,
585 (1 << 13) - 811 - 117,
586 (1 << 13) - 766 - 117,
587 (1 << 13) - 737 - 117,
588 (1 << 13) - 693 - 117,
589 (1 << 13) - 648 - 117,
590 (1 << 13) - 619 - 117,
591 (1 << 13) - 575 - 117,
592 (1 << 13) - 531 - 117,
593 (1 << 13) - 501 - 117,
646 if (state->version == SOC7090)
647 dibx000_reset_i2c_master(&state->i2c_master);
655 dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3)));
662 if (state->version != SOC7090) {
671 dprintk("GPIO reset was not successful.\n");
673 if (state->version == SOC7090) {
678 dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
694 if (state->version == SOC7090) {
697 if (state->cfg.tuner_is_baseband)
704 if (state->version != SOC7090) {
735 if (state->cfg.update_lna) {
737 if (state->cfg.update_lna(&state->demod, dyn_gain)) {
750 if (state->current_band == band && state->current_agc != NULL)
752 state->current_band = band;
754 for (i = 0; i < state->cfg.agc_config_count; i++)
755 if (state->cfg.agc[i].band_caps & band) {
756 agc = &state->cfg.agc[i];
762 return -EINVAL;
765 state->current_agc = agc;
768 dib7000p_write_word(state, 75, agc->setup);
769 dib7000p_write_word(state, 76, agc->inv_gain);
770 dib7000p_write_word(state, 77, agc->time_stabiliz);
771 dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
774 dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
775 dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
779 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
781 if (state->wbd_ref != 0)
782 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | state->wbd_ref);
784 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | agc->wbd_ref);
786 dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
788 dib7000p_write_word(state, 107, agc->agc1_max);
789 dib7000p_write_word(state, 108, agc->agc1_min);
790 dib7000p_write_word(state, 109, agc->agc2_max);
791 dib7000p_write_word(state, 110, agc->agc2_min);
792 dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
793 dib7000p_write_word(state, 112, agc->agc1_pt3);
794 dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
795 dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
796 dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
805 u32 dds = state->cfg.bw->ifreq & 0x1ffffff;
806 u8 invert = !!(state->cfg.bw->ifreq & (1 << 25));
809 return -1;
817 unit_khz_dds_val *= -1;
821 dds -= (abs_offset_khz * unit_khz_dds_val); /* /100 because of /100 on the unit_khz_dds_val line calc for better accuracy */
834 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
835 struct dib7000p_state *state = demod->demodulator_priv;
836 int ret = -1;
837 u8 *agc_state = &state->agc_state;
843 switch (state->agc_state) {
846 if (state->version == SOC7090) {
859 if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0)
860 return -1;
862 if (demod->ops.tuner_ops.get_frequency) {
865 demod->ops.tuner_ops.get_frequency(demod, &frequency_tuner);
866 frequency_offset = (s32)frequency_tuner / 1000 - ch->frequency / 1000;
870 return -1;
877 if (state->cfg.agc_control)
878 state->cfg.agc_control(&state->demod, 1);
881 if (!state->current_agc->perform_agc_softsplit) {
882 /* we are using the wbd - so slow AGC startup */
884 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
898 dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */
899 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */
908 dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */
909 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
929 if (state->cfg.agc_control)
930 state->cfg.agc_control(&state->demod, 0);
942 state->timf = timf * 160 / (state->current_bandwidth / 50);
945 dprintk("updated timf_frequency: %d (default: %d)\n", state->timf, state->cfg.bw->timf);
949 static u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
951 struct dib7000p_state *state = fe->demodulator_priv;
952 switch (op) {
954 state->timf = timf;
962 dib7000p_set_bandwidth(state, state->current_bandwidth);
963 return state->timf;
971 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
975 switch (ch->transmission_mode) {
987 switch (ch->guard_interval) {
1002 switch (ch->modulation) {
1033 if (ch->hierarchy == 1)
1037 switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
1064 switch (ch->transmission_mode) {
1076 switch (ch->guard_interval) {
1091 if (state->cfg.diversity_delay == 0)
1092 state->div_sync_wait = (value * 3) / 2 + 48;
1094 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
1097 state->div_force_off = !1 && ch->transmission_mode != TRANSMISSION_MODE_8K;
1098 dib7000p_set_diversity_in(&state->demod, state->div_state);
1101 switch (ch->modulation) {
1104 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
1106 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
1110 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
1112 est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
1116 est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
1118 est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
1127 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
1128 struct dib7000p_state *state = demod->demodulator_priv;
1143 factor = BANDWIDTH_TO_KHZ(ch->bandwidth_hz);
1145 if (state->version == SOC7090)
1172 struct dib7000p_state *state = demod->demodulator_priv;
1186 static const s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 };
1206 u32 xtal = state->cfg.bw->xtal_hz / 1000;
1207 int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz;
1215 if (f_rel < -bw_khz / 2 || f_rel > bw_khz / 2)
1229 coef_re[k] = sine[256 - (pha & 0xff)];
1235 coef_re[k] = -sine[pha & 0xff];
1236 coef_im[k] = sine[256 - (pha & 0xff)];
1238 coef_re[k] = -256;
1241 coef_re[k] = -sine[256 - (pha & 0xff)];
1242 coef_im[k] = -sine[pha & 0xff];
1245 coef_im[k] = -256;
1248 coef_im[k] = -sine[256 - (pha & 0xff)];
1254 coef_re[k] = (1 << 24) - 1;
1260 coef_im[k] = (1 << 24) - 1;
1274 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
1275 struct dib7000p_state *state = demod->demodulator_priv;
1281 return -EINVAL;
1290 if (state->sfn_workaround_active) {
1299 // never achieved a lock with that bandwidth so far - wait for osc-freq to update
1300 if (state->timf == 0)
1307 switch (ch->transmission_mode) {
1323 switch (ch->transmission_mode) {
1339 switch (ch->transmission_mode) {
1362 // we achieved a lock - it's time to update the osc freq
1370 if (state->cfg.spur_protect)
1371 dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
1373 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
1382 struct dib7000p_state *state = demod->demodulator_priv;
1385 if (state->version == SOC7090)
1392 struct dib7000p_state *state = demod->demodulator_priv;
1393 if (state->version == SOC7090)
1401 dprintk("checking demod on I2C address: %d (%x)\n", st->i2c_addr, st->i2c_addr);
1405 return -EREMOTEIO;
1410 return -EREMOTEIO;
1419 struct dib7000p_state *state = fe->demodulator_priv;
1422 fep->inversion = INVERSION_AUTO;
1424 fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth);
1428 fep->transmission_mode = TRANSMISSION_MODE_2K;
1431 fep->transmission_mode = TRANSMISSION_MODE_8K;
1433 /* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */
1438 fep->guard_interval = GUARD_INTERVAL_1_32;
1441 fep->guard_interval = GUARD_INTERVAL_1_16;
1444 fep->guard_interval = GUARD_INTERVAL_1_8;
1447 fep->guard_interval = GUARD_INTERVAL_1_4;
1453 fep->modulation = QPSK;
1456 fep->modulation = QAM_16;
1460 fep->modulation = QAM_64;
1467 fep->hierarchy = HIERARCHY_NONE;
1470 fep->code_rate_HP = FEC_1_2;
1473 fep->code_rate_HP = FEC_2_3;
1476 fep->code_rate_HP = FEC_3_4;
1479 fep->code_rate_HP = FEC_5_6;
1483 fep->code_rate_HP = FEC_7_8;
1490 fep->code_rate_LP = FEC_1_2;
1493 fep->code_rate_LP = FEC_2_3;
1496 fep->code_rate_LP = FEC_3_4;
1499 fep->code_rate_LP = FEC_5_6;
1503 fep->code_rate_LP = FEC_7_8;
1514 struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
1515 struct dib7000p_state *state = fe->demodulator_priv;
1518 if (state->version == SOC7090)
1524 state->sfn_workaround_active = buggy_sfn_workaround;
1526 if (fe->ops.tuner_ops.set_params)
1527 fe->ops.tuner_ops.set_params(fe);
1530 state->agc_state = 0;
1533 if (time != -1)
1535 } while (time != -1);
1537 if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
1538 fep->guard_interval == GUARD_INTERVAL_AUTO || fep->modulation == QAM_AUTO || fep->code_rate_HP == FEC_AUTO) {
1545 } while (found == 0 && i--);
1557 if (state->version == SOC7090) {
1558 dib7090_set_output_mode(fe, state->cfg.output_mode);
1559 if (state->cfg.enMpegOutput == 0) {
1564 dib7000p_set_output_mode(state, state->cfg.output_mode);
1573 struct dib7000p_state *state = fe->demodulator_priv;
1596 struct dib7000p_state *state = fe->demodulator_priv;
1603 struct dib7000p_state *state = fe->demodulator_priv;
1610 struct dib7000p_state *state = fe->demodulator_priv;
1612 *strength = 65535 - val;
1618 struct dib7000p_state *state = fe->demodulator_priv;
1629 noise_exp -= 0x40;
1634 signal_exp -= 0x40;
1639 result = intlog10(2) * 10 * signal_exp - 100;
1642 result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant);
1644 result -= intlog10(2) * 10 * noise_exp - 100;
1661 struct dib7000p_state *state = demod->demodulator_priv;
1662 struct dtv_frontend_properties *c = &demod->dtv_property_cache;
1665 memset(&c->strength, 0, sizeof(c->strength));
1666 memset(&c->cnr, 0, sizeof(c->cnr));
1667 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
1668 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
1669 memset(&c->block_error, 0, sizeof(c->block_error));
1671 c->strength.len = 1;
1672 c->cnr.len = 1;
1673 c->block_error.len = 1;
1674 c->block_count.len = 1;
1675 c->post_bit_error.len = 1;
1676 c->post_bit_count.len = 1;
1678 c->strength.stat[0].scale = FE_SCALE_DECIBEL;
1679 c->strength.stat[0].uvalue = 0;
1681 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1682 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1683 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1684 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1685 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1689 state->old_ucb = ucb;
1690 state->ber_jiffies_stats = 0;
1691 state->per_jiffies_stats = 0;
1705 * by a DTA-2111 RF generator directly connected into a dib7000p device
1706 * (a Hauppauge Nova-TD stick), using a good quality 3 meters length
1708 * As the minimum output power of DTA-2111 is -31dBm, a 16 dBm attenuator
1713 * Yet, it is better to use this measure in dB than a random non-linear
1721 { 63630, DB_OFFSET - 20500},
1722 { 62273, DB_OFFSET - 21000},
1723 { 60162, DB_OFFSET - 22000},
1724 { 58730, DB_OFFSET - 23000},
1725 { 58294, DB_OFFSET - 24000},
1726 { 57778, DB_OFFSET - 25000},
1727 { 57320, DB_OFFSET - 26000},
1728 { 56779, DB_OFFSET - 27000},
1729 { 56293, DB_OFFSET - 28000},
1730 { 55724, DB_OFFSET - 29000},
1731 { 55145, DB_OFFSET - 30000},
1732 { 54680, DB_OFFSET - 31000},
1733 { 54293, DB_OFFSET - 32000},
1734 { 53813, DB_OFFSET - 33000},
1735 { 53427, DB_OFFSET - 34000},
1736 { 52981, DB_OFFSET - 35000},
1738 { 52636, DB_OFFSET - 36000},
1739 { 52014, DB_OFFSET - 37000},
1740 { 51674, DB_OFFSET - 38000},
1741 { 50692, DB_OFFSET - 39000},
1742 { 49824, DB_OFFSET - 40000},
1743 { 49052, DB_OFFSET - 41000},
1744 { 48436, DB_OFFSET - 42000},
1745 { 47836, DB_OFFSET - 43000},
1746 { 47368, DB_OFFSET - 44000},
1747 { 46468, DB_OFFSET - 45000},
1748 { 45597, DB_OFFSET - 46000},
1749 { 44586, DB_OFFSET - 47000},
1750 { 43667, DB_OFFSET - 48000},
1751 { 42673, DB_OFFSET - 49000},
1752 { 41816, DB_OFFSET - 50000},
1753 { 40876, DB_OFFSET - 51000},
1767 if (value < segments[len-1].x)
1768 return segments[len-1].y;
1770 for (i = 1; i < len - 1; i++) {
1779 dy = segments[i - 1].y - segments[i].y;
1780 dx = segments[i - 1].x - segments[i].x;
1782 tmp64 = value - segments[i].x;
1790 /* FIXME: may require changes - this one was borrowed from dib8000 */
1793 struct dtv_frontend_properties *c = &demod->dtv_property_cache;
1799 switch (c->guard_interval) {
1815 switch (c->transmission_mode) {
1828 switch (c->modulation) {
1842 switch ((c->hierarchy == 0 || 1 == 1) ? c->code_rate_HP : c->code_rate_LP) {
1893 struct dib7000p_state *state = demod->demodulator_priv;
1894 struct dtv_frontend_properties *c = &demod->dtv_property_cache;
1906 ARRAY_SIZE(strength_to_db_table)) - DB_OFFSET;
1907 c->strength.stat[0].svalue = db;
1911 c->cnr.len = 1;
1912 c->block_count.len = 1;
1913 c->block_error.len = 1;
1914 c->post_bit_error.len = 1;
1915 c->post_bit_count.len = 1;
1916 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1917 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1918 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1919 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1920 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1925 if (time_after(jiffies, state->per_jiffies_stats)) {
1926 state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
1934 c->cnr.stat[0].svalue = snr;
1935 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1939 ucb = val - state->old_ucb;
1940 if (val < state->old_ucb)
1943 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1944 c->block_error.stat[0].uvalue = ucb;
1953 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1954 c->block_count.stat[0].uvalue += blocks;
1960 /* Get post-BER measures */
1961 if (time_after(jiffies, state->ber_jiffies_stats)) {
1963 state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
1968 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1969 c->post_bit_error.stat[0].uvalue += val;
1971 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1972 c->post_bit_count.stat[0].uvalue += 100000000;
1979 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1980 c->block_error.stat[0].uvalue += val;
1986 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1987 c->block_count.stat[0].uvalue += blocks;
1995 tune->min_delay_ms = 1000;
2001 struct dib7000p_state *st = demod->demodulator_priv;
2002 dibx000_exit_i2c_master(&st->i2c_master);
2003 i2c_del_adapter(&st->dib7090_tuner_adap);
2018 return -ENOMEM;
2021 ret = -ENOMEM;
2033 dprintk("-D- DiB7000PC detected\n");
2042 dprintk("-D- DiB7000PC detected\n");
2047 dprintk("-D- DiB7000PC not detected\n");
2058 struct dib7000p_state *st = demod->demodulator_priv;
2059 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
2064 struct dib7000p_state *state = fe->demodulator_priv;
2073 struct dib7000p_state *state = fe->demodulator_priv;
2078 static int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
2086 return -ENOMEM;
2088 dpst->i2c_adap = i2c;
2089 mutex_init(&dpst->i2c_buffer_lock);
2091 for (k = no_of_demods - 1; k >= 0; k--) {
2092 dpst->cfg = cfg[k];
2095 if (cfg[k].default_i2c_addr != 0)
2096 new_addr = cfg[k].default_i2c_addr + (k << 1);
2099 dpst->i2c_addr = new_addr;
2102 dpst->i2c_addr = default_addr;
2107 return -EIO;
2111 /* start diversity to pull_down div_str - just for i2c-enumeration */
2121 dpst->cfg = cfg[k];
2122 if (cfg[k].default_i2c_addr != 0)
2123 dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1;
2125 dpst->i2c_addr = (0x40 + k) << 1;
2128 dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2);
2130 /* deactivate div - it was just for i2c-enumeration */
2144 struct dib7000p_state *state = fe->demodulator_priv;
2162 ix = (u8) ((mant - 1000) / 100); /* index of the LUT */
2165 pow_i = (lut_1000ln_mant[ix] + 693 * (exp - 20) - 6908);
2174 if ((msg->buf[0] <= 15))
2175 msg->buf[0] -= 1;
2176 else if (msg->buf[0] == 17)
2177 msg->buf[0] = 15;
2178 else if (msg->buf[0] == 16)
2179 msg->buf[0] = 17;
2180 else if (msg->buf[0] == 19)
2181 msg->buf[0] = 16;
2182 else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
2183 msg->buf[0] -= 3;
2184 else if (msg->buf[0] == 28)
2185 msg->buf[0] = 23;
2187 return -EINVAL;
2200 i--;
2220 i--;
2229 i--;
2396 struct dib7000p_state *st = fe->demodulator_priv;
2397 return &st->dib7090_tuner_adap;
2439 if ((syncFreq & ((1 << quantif) - 1)) != 0)
2445 syncFreq = syncFreq - 1;
2514 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
2577 struct dib7000p_state *state = fe->demodulator_priv;
2581 case 0: /* only use the internal way - not the diversity input */
2594 state->input_mode_mpeg = 1;
2600 state->input_mode_mpeg = 0;
2604 dib7000p_set_diversity_in(&state->demod, onoff);
2610 struct dib7000p_state *state = fe->demodulator_priv;
2680 if (state->cfg.output_mpeg2_in_188_bytes)
2692 struct dib7000p_state *state = fe->demodulator_priv;
2700 state->tuner_enable = en_cur_state;
2705 if (state->tuner_enable != 0)
2706 en_cur_state = state->tuner_enable;
2721 struct dib7000p_state *state = fe->demodulator_priv;
2732 static struct dvb_frontend *dib7000p_init(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
2740 memcpy(&st->cfg, cfg, sizeof(struct dib7000p_config));
2741 st->i2c_adap = i2c_adap;
2742 st->i2c_addr = i2c_addr;
2743 st->gpio_val = cfg->gpio_val;
2744 st->gpio_dir = cfg->gpio_dir;
2749 if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
2750 st->cfg.output_mode = OUTMODE_MPEG2_FIFO;
2752 demod = &st->demod;
2753 demod->demodulator_priv = st;
2754 memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
2755 mutex_init(&st->i2c_buffer_lock);
2762 st->version = dib7000p_read_word(st, 897);
2767 st->i2c_master.gated_tuner_i2c_adap.dev.parent = i2c_adap->dev.parent;
2769 dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr);
2772 strscpy(st->dib7090_tuner_adap.name, "DiB7090 tuner interface",
2773 sizeof(st->dib7090_tuner_adap.name));
2774 st->dib7090_tuner_adap.algo = &dib7090_tuner_xfer_algo;
2775 st->dib7090_tuner_adap.algo_data = NULL;
2776 st->dib7090_tuner_adap.dev.parent = st->i2c_adap->dev.parent;
2777 i2c_set_adapdata(&st->dib7090_tuner_adap, st);
2778 i2c_add_adapter(&st->dib7090_tuner_adap);
2784 if (st->version == SOC7090) {
2785 dib7090_set_output_mode(demod, st->cfg.output_mode);
2801 ops->slave_reset = dib7090_slave_reset;
2802 ops->get_adc_power = dib7090_get_adc_power;
2803 ops->dib7000pc_detection = dib7000pc_detection;
2804 ops->get_i2c_tuner = dib7090_get_i2c_tuner;
2805 ops->tuner_sleep = dib7090_tuner_sleep;
2806 ops->init = dib7000p_init;
2807 ops->set_agc1_min = dib7000p_set_agc1_min;
2808 ops->set_gpio = dib7000p_set_gpio;
2809 ops->i2c_enumeration = dib7000p_i2c_enumeration;
2810 ops->pid_filter = dib7000p_pid_filter;
2811 ops->pid_filter_ctrl = dib7000p_pid_filter_ctrl;
2812 ops->get_i2c_master = dib7000p_get_i2c_master;
2813 ops->update_pll = dib7000p_update_pll;
2814 ops->ctrl_timf = dib7000p_ctrl_timf;
2815 ops->get_agc_values = dib7000p_get_agc_values;
2816 ops->set_wbd_ref = dib7000p_set_wbd_ref;