Lines Matching refs:dib3000mc_write_word
83 static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val) in dib3000mc_write_word() function
156 dib3000mc_write_word(state, 23, (u16) (timf >> 16)); in dib3000mc_set_timing()
157 dib3000mc_write_word(state, 24, (u16) (timf ) & 0xffff); in dib3000mc_set_timing()
172 dib3000mc_write_word(state, 51, reg_51); in dib3000mc_setup_pwm_state()
173 dib3000mc_write_word(state, 52, reg_52); in dib3000mc_setup_pwm_state()
176 dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0)); in dib3000mc_setup_pwm_state()
178 dib3000mc_write_word(state, 245, 0); in dib3000mc_setup_pwm_state()
180 dib3000mc_write_word(state, 1040, 0x3); in dib3000mc_setup_pwm_state()
238 ret |= dib3000mc_write_word(state, 244, outreg); in dib3000mc_set_output_mode()
239 ret |= dib3000mc_write_word(state, 206, smo_reg); /*smo_ mode*/ in dib3000mc_set_output_mode()
240 ret |= dib3000mc_write_word(state, 207, fifo_threshold); /* synchronous fread */ in dib3000mc_set_output_mode()
241 ret |= dib3000mc_write_word(state, 1040, elecout); /* P_out_cfg */ in dib3000mc_set_output_mode()
277 dib3000mc_write_word(state, reg, bw_cfg[reg - 6]); in dib3000mc_set_bandwidth()
278 dib3000mc_write_word(state, 12, 0x0000); in dib3000mc_set_bandwidth()
279 dib3000mc_write_word(state, 13, 0x03e8); in dib3000mc_set_bandwidth()
280 dib3000mc_write_word(state, 14, 0x0000); in dib3000mc_set_bandwidth()
281 dib3000mc_write_word(state, 15, 0x03f2); in dib3000mc_set_bandwidth()
282 dib3000mc_write_word(state, 16, 0x0001); in dib3000mc_set_bandwidth()
283 dib3000mc_write_word(state, 17, 0xb0d0); in dib3000mc_set_bandwidth()
285 dib3000mc_write_word(state, 18, 0x0393); in dib3000mc_set_bandwidth()
286 dib3000mc_write_word(state, 19, 0x8700); in dib3000mc_set_bandwidth()
289 dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]); in dib3000mc_set_bandwidth()
309 dib3000mc_write_word(state, i, impulse_noise_val[i-58]); in dib3000mc_set_impulse_noise()
312 dib3000mc_write_word(state, 58, 0x3b); in dib3000mc_set_impulse_noise()
313 dib3000mc_write_word(state, 84, 0x00); in dib3000mc_set_impulse_noise()
314 dib3000mc_write_word(state, 85, 0x8200); in dib3000mc_set_impulse_noise()
317 dib3000mc_write_word(state, 34, 0x1294); in dib3000mc_set_impulse_noise()
318 dib3000mc_write_word(state, 35, 0x1ff8); in dib3000mc_set_impulse_noise()
320 dib3000mc_write_word(state, 55, dib3000mc_read_word(state, 55) | (1 << 10)); in dib3000mc_set_impulse_noise()
329 dib3000mc_write_word(state, 1027, 0x8000); in dib3000mc_init()
330 dib3000mc_write_word(state, 1027, 0x0000); in dib3000mc_init()
333 dib3000mc_write_word(state, 140, 0x0000); in dib3000mc_init()
334 dib3000mc_write_word(state, 1031, 0); in dib3000mc_init()
337 dib3000mc_write_word(state, 139, 0x0000); in dib3000mc_init()
338 dib3000mc_write_word(state, 141, 0x0000); in dib3000mc_init()
339 dib3000mc_write_word(state, 175, 0x0002); in dib3000mc_init()
340 dib3000mc_write_word(state, 1032, 0x0000); in dib3000mc_init()
342 dib3000mc_write_word(state, 139, 0x0001); in dib3000mc_init()
343 dib3000mc_write_word(state, 141, 0x0000); in dib3000mc_init()
344 dib3000mc_write_word(state, 175, 0x0000); in dib3000mc_init()
345 dib3000mc_write_word(state, 1032, 0x012C); in dib3000mc_init()
347 dib3000mc_write_word(state, 1033, 0x0000); in dib3000mc_init()
350 dib3000mc_write_word(state, 1037, 0x3130); in dib3000mc_init()
355 dib3000mc_write_word(state, 33, (5 << 0)); in dib3000mc_init()
356 dib3000mc_write_word(state, 88, (1 << 10) | (0x10 << 0)); in dib3000mc_init()
360 dib3000mc_write_word(state, 99, (1 << 9) | (0x20 << 0)); in dib3000mc_init()
363 dib3000mc_write_word(state, 111, 0x00); in dib3000mc_init()
365 dib3000mc_write_word(state, 111, 0x02); in dib3000mc_init()
368 dib3000mc_write_word(state, 50, 0x8000); in dib3000mc_init()
374 dib3000mc_write_word(state, 53, 0x87); in dib3000mc_init()
376 dib3000mc_write_word(state, 54, 0x87); in dib3000mc_init()
379 dib3000mc_write_word(state, 36, state->cfg->max_time); in dib3000mc_init()
380 …dib3000mc_write_word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12… in dib3000mc_init()
381 dib3000mc_write_word(state, 38, state->cfg->pwm3_value); in dib3000mc_init()
382 dib3000mc_write_word(state, 39, state->cfg->ln_adc_level); in dib3000mc_init()
385 dib3000mc_write_word(state, 40, 0x0179); in dib3000mc_init()
386 dib3000mc_write_word(state, 41, 0x03f0); in dib3000mc_init()
388 dib3000mc_write_word(state, 42, agc->agc1_max); in dib3000mc_init()
389 dib3000mc_write_word(state, 43, agc->agc1_min); in dib3000mc_init()
390 dib3000mc_write_word(state, 44, agc->agc2_max); in dib3000mc_init()
391 dib3000mc_write_word(state, 45, agc->agc2_min); in dib3000mc_init()
392 dib3000mc_write_word(state, 46, (agc->agc1_pt1 << 8) | agc->agc1_pt2); in dib3000mc_init()
393 dib3000mc_write_word(state, 47, (agc->agc1_slope1 << 8) | agc->agc1_slope2); in dib3000mc_init()
394 dib3000mc_write_word(state, 48, (agc->agc2_pt1 << 8) | agc->agc2_pt2); in dib3000mc_init()
395 dib3000mc_write_word(state, 49, (agc->agc2_slope1 << 8) | agc->agc2_slope2); in dib3000mc_init()
399 dib3000mc_write_word(state, 110, 3277); in dib3000mc_init()
401 dib3000mc_write_word(state, 26, 0x6680); in dib3000mc_init()
403 dib3000mc_write_word(state, 1, 4); in dib3000mc_init()
405 dib3000mc_write_word(state, 2, 4); in dib3000mc_init()
407 dib3000mc_write_word(state, 3, 0x1000); in dib3000mc_init()
409 dib3000mc_write_word(state, 5, 1); in dib3000mc_init()
414 dib3000mc_write_word(state, 4, 0x814); in dib3000mc_init()
416 dib3000mc_write_word(state, 21, (1 << 9) | 0x164); in dib3000mc_init()
417 dib3000mc_write_word(state, 22, 0x463d); in dib3000mc_init()
421 dib3000mc_write_word(state, 120, 0x200f); in dib3000mc_init()
423 dib3000mc_write_word(state, 134, 0); in dib3000mc_init()
426 dib3000mc_write_word(state, 195, 0x10); in dib3000mc_init()
429 dib3000mc_write_word(state, 180, 0x2FF0); in dib3000mc_init()
438 dib3000mc_write_word(state, 769, (1 << 7) ); in dib3000mc_init()
447 dib3000mc_write_word(state, 1031, 0xFFFF); in dib3000mc_sleep()
448 dib3000mc_write_word(state, 1032, 0xFFFF); in dib3000mc_sleep()
449 dib3000mc_write_word(state, 1033, 0xFFF0); in dib3000mc_sleep()
469 dib3000mc_write_word(state, reg, cfg[reg - 129]); in dib3000mc_set_adp_cfg()
482 dib3000mc_write_word(state, 100, (16 << 6) + 9); in dib3000mc_set_channel_cfg()
485 dib3000mc_write_word(state, 100, (11 << 6) + 6); in dib3000mc_set_channel_cfg()
487 dib3000mc_write_word(state, 100, (16 << 6) + 9); in dib3000mc_set_channel_cfg()
490 dib3000mc_write_word(state, 1027, 0x0800); in dib3000mc_set_channel_cfg()
491 dib3000mc_write_word(state, 1027, 0x0000); in dib3000mc_set_channel_cfg()
494 dib3000mc_write_word(state, 26, 0x6680); in dib3000mc_set_channel_cfg()
495 dib3000mc_write_word(state, 29, 0x1273); in dib3000mc_set_channel_cfg()
496 dib3000mc_write_word(state, 33, 5); in dib3000mc_set_channel_cfg()
498 dib3000mc_write_word(state, 133, 15564); in dib3000mc_set_channel_cfg()
500 dib3000mc_write_word(state, 12 , 0x0); in dib3000mc_set_channel_cfg()
501 dib3000mc_write_word(state, 13 , 0x3e8); in dib3000mc_set_channel_cfg()
502 dib3000mc_write_word(state, 14 , 0x0); in dib3000mc_set_channel_cfg()
503 dib3000mc_write_word(state, 15 , 0x3f2); in dib3000mc_set_channel_cfg()
505 dib3000mc_write_word(state, 93,0); in dib3000mc_set_channel_cfg()
506 dib3000mc_write_word(state, 94,0); in dib3000mc_set_channel_cfg()
507 dib3000mc_write_word(state, 95,0); in dib3000mc_set_channel_cfg()
508 dib3000mc_write_word(state, 96,0); in dib3000mc_set_channel_cfg()
509 dib3000mc_write_word(state, 97,0); in dib3000mc_set_channel_cfg()
510 dib3000mc_write_word(state, 98,0); in dib3000mc_set_channel_cfg()
539 dib3000mc_write_word(state, 0, value); in dib3000mc_set_channel_cfg()
540 dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4)); in dib3000mc_set_channel_cfg()
555 dib3000mc_write_word(state, 181, value); in dib3000mc_set_channel_cfg()
572 dib3000mc_write_word(state, 180, value); in dib3000mc_set_channel_cfg()
576 dib3000mc_write_word(state, 0, value | (1 << 9)); in dib3000mc_set_channel_cfg()
577 dib3000mc_write_word(state, 0, value); in dib3000mc_set_channel_cfg()
607 dib3000mc_write_word(state, 0, reg | (1 << 8)); in dib3000mc_autosearch_start()
609 dib3000mc_write_word(state, 0, reg); in dib3000mc_autosearch_start()
639 dib3000mc_write_word(state, 29, 0x1273); in dib3000mc_tune()
640 dib3000mc_write_word(state, 108, 0x4000); // P_pha3_force_pha_shift in dib3000mc_tune()
642 dib3000mc_write_word(state, 29, 0x1073); in dib3000mc_tune()
643 dib3000mc_write_word(state, 108, 0x0000); // P_pha3_force_pha_shift in dib3000mc_tune()
648 dib3000mc_write_word(state, 26, 38528); in dib3000mc_tune()
649 dib3000mc_write_word(state, 33, 8); in dib3000mc_tune()
651 dib3000mc_write_word(state, 26, 30336); in dib3000mc_tune()
652 dib3000mc_write_word(state, 33, 6); in dib3000mc_tune()
835 dib3000mc_write_word(state, 212 + index, onoff ? (1 << 13) | pid : 0); in dib3000mc_pid_control()
845 return dib3000mc_write_word(state, 206, tmp); in dib3000mc_pid_parse()
888 dib3000mc_write_word(dmcst, 1024, (new_addr << 3) | 0x1); in dib3000mc_i2c_enumeration()
896 dib3000mc_write_word(dmcst, 1024, dmcst->i2c_addr << 3); in dib3000mc_i2c_enumeration()
930 dib3000mc_write_word(st, 1037, 0x3130); in dib3000mc_attach()