Lines Matching +full:0 +full:x1294
23 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
27 MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
33 } while (0)
56 { .addr = state->i2c_addr >> 1, .flags = 0, .len = 2 }, in dib3000mc_read_word()
64 return 0; in dib3000mc_read_word()
66 b[0] = (reg >> 8) | 0x80; in dib3000mc_read_word()
68 b[2] = 0; in dib3000mc_read_word()
69 b[3] = 0; in dib3000mc_read_word()
71 msg[0].buf = b; in dib3000mc_read_word()
86 .addr = state->i2c_addr >> 1, .flags = 0, .len = 4 in dib3000mc_write_word()
95 b[0] = reg >> 8; in dib3000mc_write_word()
102 rc = i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; in dib3000mc_write_word()
111 if ((value = dib3000mc_read_word(state, 1025)) != 0x01b3) { in dib3000mc_identify()
112 dprintk("-E- DiB3000MC/P: wrong Vendor ID (read=0x%x)\n",value); in dib3000mc_identify()
117 if (value != 0x3001 && value != 0x3002) { in dib3000mc_identify()
125 return 0; in dib3000mc_identify()
132 if (state->timf == 0) { in dib3000mc_set_timing()
144 if (tim_offs & 0x2000) in dib3000mc_set_timing()
145 tim_offs -= 0x4000; in dib3000mc_set_timing()
157 dib3000mc_write_word(state, 24, (u16) (timf ) & 0xffff); in dib3000mc_set_timing()
159 return 0; in dib3000mc_set_timing()
164 u16 reg_51, reg_52 = state->cfg->agc->setup & 0xfefb; in dib3000mc_setup_pwm_state()
166 reg_51 = (2 << 14) | (0 << 10) | (7 << 6) | (2 << 2) | (2 << 0); in dib3000mc_setup_pwm_state()
169 reg_51 = (2 << 14) | (4 << 10) | (7 << 6) | (2 << 2) | (2 << 0); in dib3000mc_setup_pwm_state()
176 dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0)); in dib3000mc_setup_pwm_state()
178 dib3000mc_write_word(state, 245, 0); in dib3000mc_setup_pwm_state()
180 dib3000mc_write_word(state, 1040, 0x3); in dib3000mc_setup_pwm_state()
181 return 0; in dib3000mc_setup_pwm_state()
186 int ret = 0; in dib3000mc_set_output_mode()
188 u16 outreg = 0; in dib3000mc_set_output_mode()
189 u16 outmode = 0; in dib3000mc_set_output_mode()
191 u16 smo_reg = dib3000mc_read_word(state, 206) & 0x0010; /* keep the pid_parse bit */ in dib3000mc_set_output_mode()
198 elecout = 0; in dib3000mc_set_output_mode()
201 outmode = 0; in dib3000mc_set_output_mode()
212 P_smo_error_discard [1;6:6] = 0 in dib3000mc_set_output_mode()
213 P_smo_rs_discard [1;5:5] = 0 in dib3000mc_set_output_mode()
214 P_smo_pid_parse [1;4:4] = 0 in dib3000mc_set_output_mode()
215 P_smo_fifo_flush [1;3:3] = 0 in dib3000mc_set_output_mode()
217 P_smo_ovf_prot [1;0:0] = 0 in dib3000mc_set_output_mode()
229 outmode = 0; in dib3000mc_set_output_mode()
236 outreg = dib3000mc_read_word(state, 244) & 0x07FF; in dib3000mc_set_output_mode()
247 u16 bw_cfg[6] = { 0 }; in dib3000mc_set_bandwidth()
248 u16 imp_bw_cfg[3] = { 0 }; in dib3000mc_set_bandwidth()
254 …bw_cfg[0] = 0x0019; bw_cfg[1] = 0x5c30; bw_cfg[2] = 0x0054; bw_cfg[3] = 0x88a0; bw_cfg[4] = 0x01a6… in dib3000mc_set_bandwidth()
255 imp_bw_cfg[0] = 0x04db; imp_bw_cfg[1] = 0x00db; imp_bw_cfg[2] = 0x00b7; in dib3000mc_set_bandwidth()
259 …bw_cfg[0] = 0x001c; bw_cfg[1] = 0xfba5; bw_cfg[2] = 0x0060; bw_cfg[3] = 0x9c25; bw_cfg[4] = 0x01e3… in dib3000mc_set_bandwidth()
260 imp_bw_cfg[0] = 0x04c0; imp_bw_cfg[1] = 0x00c0; imp_bw_cfg[2] = 0x00a0; in dib3000mc_set_bandwidth()
264 …bw_cfg[0] = 0x0021; bw_cfg[1] = 0xd040; bw_cfg[2] = 0x0070; bw_cfg[3] = 0xb62b; bw_cfg[4] = 0x0233… in dib3000mc_set_bandwidth()
265 imp_bw_cfg[0] = 0x04a5; imp_bw_cfg[1] = 0x00a5; imp_bw_cfg[2] = 0x0089; in dib3000mc_set_bandwidth()
269 …bw_cfg[0] = 0x0028; bw_cfg[1] = 0x9380; bw_cfg[2] = 0x0087; bw_cfg[3] = 0x4100; bw_cfg[4] = 0x02a4… in dib3000mc_set_bandwidth()
270 imp_bw_cfg[0] = 0x0489; imp_bw_cfg[1] = 0x0089; imp_bw_cfg[2] = 0x0072; in dib3000mc_set_bandwidth()
278 dib3000mc_write_word(state, 12, 0x0000); in dib3000mc_set_bandwidth()
279 dib3000mc_write_word(state, 13, 0x03e8); in dib3000mc_set_bandwidth()
280 dib3000mc_write_word(state, 14, 0x0000); in dib3000mc_set_bandwidth()
281 dib3000mc_write_word(state, 15, 0x03f2); in dib3000mc_set_bandwidth()
282 dib3000mc_write_word(state, 16, 0x0001); in dib3000mc_set_bandwidth()
283 dib3000mc_write_word(state, 17, 0xb0d0); in dib3000mc_set_bandwidth()
285 dib3000mc_write_word(state, 18, 0x0393); in dib3000mc_set_bandwidth()
286 dib3000mc_write_word(state, 19, 0x8700); in dib3000mc_set_bandwidth()
292 dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0); in dib3000mc_set_bandwidth()
294 return 0; in dib3000mc_set_bandwidth()
300 0x38, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c, 0x3ffe, 0x7f3,
301 0x2d94, 0x76, 0x53d, 0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3, 0x3feb, 0x7d2,
302 0x365e, 0x76, 0x48c, 0x3ffe, 0x5b3, 0x3feb, 0x76, 0x0000, 0xd
312 dib3000mc_write_word(state, 58, 0x3b); in dib3000mc_set_impulse_noise()
313 dib3000mc_write_word(state, 84, 0x00); in dib3000mc_set_impulse_noise()
314 dib3000mc_write_word(state, 85, 0x8200); in dib3000mc_set_impulse_noise()
317 dib3000mc_write_word(state, 34, 0x1294); in dib3000mc_set_impulse_noise()
318 dib3000mc_write_word(state, 35, 0x1ff8); in dib3000mc_set_impulse_noise()
329 dib3000mc_write_word(state, 1027, 0x8000); in dib3000mc_init()
330 dib3000mc_write_word(state, 1027, 0x0000); in dib3000mc_init()
333 dib3000mc_write_word(state, 140, 0x0000); in dib3000mc_init()
334 dib3000mc_write_word(state, 1031, 0); in dib3000mc_init()
337 dib3000mc_write_word(state, 139, 0x0000); in dib3000mc_init()
338 dib3000mc_write_word(state, 141, 0x0000); in dib3000mc_init()
339 dib3000mc_write_word(state, 175, 0x0002); in dib3000mc_init()
340 dib3000mc_write_word(state, 1032, 0x0000); in dib3000mc_init()
342 dib3000mc_write_word(state, 139, 0x0001); in dib3000mc_init()
343 dib3000mc_write_word(state, 141, 0x0000); in dib3000mc_init()
344 dib3000mc_write_word(state, 175, 0x0000); in dib3000mc_init()
345 dib3000mc_write_word(state, 1032, 0x012C); in dib3000mc_init()
347 dib3000mc_write_word(state, 1033, 0x0000); in dib3000mc_init()
350 dib3000mc_write_word(state, 1037, 0x3130); in dib3000mc_init()
355 dib3000mc_write_word(state, 33, (5 << 0)); in dib3000mc_init()
356 dib3000mc_write_word(state, 88, (1 << 10) | (0x10 << 0)); in dib3000mc_init()
360 dib3000mc_write_word(state, 99, (1 << 9) | (0x20 << 0)); in dib3000mc_init()
362 if (state->cfg->phase_noise_mode == 0) in dib3000mc_init()
363 dib3000mc_write_word(state, 111, 0x00); in dib3000mc_init()
365 dib3000mc_write_word(state, 111, 0x02); in dib3000mc_init()
368 dib3000mc_write_word(state, 50, 0x8000); in dib3000mc_init()
374 dib3000mc_write_word(state, 53, 0x87); in dib3000mc_init()
376 dib3000mc_write_word(state, 54, 0x87); in dib3000mc_init()
380 …word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12) | (0x1d << 0)); in dib3000mc_init()
385 dib3000mc_write_word(state, 40, 0x0179); in dib3000mc_init()
386 dib3000mc_write_word(state, 41, 0x03f0); in dib3000mc_init()
400 // P_timf_alpha = 6, P_corm_alpha = 6, P_corm_thres = 0x80 in dib3000mc_init()
401 dib3000mc_write_word(state, 26, 0x6680); in dib3000mc_init()
407 dib3000mc_write_word(state, 3, 0x1000); in dib3000mc_init()
414 dib3000mc_write_word(state, 4, 0x814); in dib3000mc_init()
416 dib3000mc_write_word(state, 21, (1 << 9) | 0x164); in dib3000mc_init()
417 dib3000mc_write_word(state, 22, 0x463d); in dib3000mc_init()
421 dib3000mc_write_word(state, 120, 0x200f); in dib3000mc_init()
423 dib3000mc_write_word(state, 134, 0); in dib3000mc_init()
426 dib3000mc_write_word(state, 195, 0x10); in dib3000mc_init()
429 dib3000mc_write_word(state, 180, 0x2FF0); in dib3000mc_init()
432 dib3000mc_set_impulse_noise(state, 0, TRANSMISSION_MODE_8K); in dib3000mc_init()
440 return 0; in dib3000mc_init()
447 dib3000mc_write_word(state, 1031, 0xFFFF); in dib3000mc_sleep()
448 dib3000mc_write_word(state, 1032, 0xFFFF); in dib3000mc_sleep()
449 dib3000mc_write_word(state, 1033, 0xFFF0); in dib3000mc_sleep()
451 return 0; in dib3000mc_sleep()
456 u16 cfg[4] = { 0 },reg; in dib3000mc_set_adp_cfg()
459 cfg[0] = 0x099a; cfg[1] = 0x7fae; cfg[2] = 0x0333; cfg[3] = 0x7ff0; in dib3000mc_set_adp_cfg()
462 cfg[0] = 0x023d; cfg[1] = 0x7fdf; cfg[2] = 0x00a4; cfg[3] = 0x7ff0; in dib3000mc_set_adp_cfg()
465 cfg[0] = 0x0148; cfg[1] = 0x7ff0; cfg[2] = 0x00a4; cfg[3] = 0x7ff8; in dib3000mc_set_adp_cfg()
479 dib3000mc_set_timing(state, ch->transmission_mode, bw, 0); in dib3000mc_set_channel_cfg()
490 dib3000mc_write_word(state, 1027, 0x0800); in dib3000mc_set_channel_cfg()
491 dib3000mc_write_word(state, 1027, 0x0000); in dib3000mc_set_channel_cfg()
494 dib3000mc_write_word(state, 26, 0x6680); in dib3000mc_set_channel_cfg()
495 dib3000mc_write_word(state, 29, 0x1273); in dib3000mc_set_channel_cfg()
500 dib3000mc_write_word(state, 12 , 0x0); in dib3000mc_set_channel_cfg()
501 dib3000mc_write_word(state, 13 , 0x3e8); in dib3000mc_set_channel_cfg()
502 dib3000mc_write_word(state, 14 , 0x0); in dib3000mc_set_channel_cfg()
503 dib3000mc_write_word(state, 15 , 0x3f2); in dib3000mc_set_channel_cfg()
505 dib3000mc_write_word(state, 93,0); in dib3000mc_set_channel_cfg()
506 dib3000mc_write_word(state, 94,0); in dib3000mc_set_channel_cfg()
507 dib3000mc_write_word(state, 95,0); in dib3000mc_set_channel_cfg()
508 dib3000mc_write_word(state, 96,0); in dib3000mc_set_channel_cfg()
509 dib3000mc_write_word(state, 97,0); in dib3000mc_set_channel_cfg()
510 dib3000mc_write_word(state, 98,0); in dib3000mc_set_channel_cfg()
512 dib3000mc_set_impulse_noise(state, 0, ch->transmission_mode); in dib3000mc_set_channel_cfg()
514 value = 0; in dib3000mc_set_channel_cfg()
516 case TRANSMISSION_MODE_2K: value |= (0 << 7); break; in dib3000mc_set_channel_cfg()
521 case GUARD_INTERVAL_1_32: value |= (0 << 5); break; in dib3000mc_set_channel_cfg()
528 case QPSK: value |= (0 << 3); break; in dib3000mc_set_channel_cfg()
539 dib3000mc_write_word(state, 0, value); in dib3000mc_set_channel_cfg()
540 dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4)); in dib3000mc_set_channel_cfg()
542 value = 0; in dib3000mc_set_channel_cfg()
547 switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) { in dib3000mc_set_channel_cfg()
571 value |= dib3000mc_read_word(state, 180) & 0x000f; in dib3000mc_set_channel_cfg()
575 value = dib3000mc_read_word(state, 0); in dib3000mc_set_channel_cfg()
576 dib3000mc_write_word(state, 0, value | (1 << 9)); in dib3000mc_set_channel_cfg()
577 dib3000mc_write_word(state, 0, value); in dib3000mc_set_channel_cfg()
602 schan.hierarchy = 0; in dib3000mc_autosearch_start()
606 reg = dib3000mc_read_word(state, 0); in dib3000mc_autosearch_start()
607 dib3000mc_write_word(state, 0, reg | (1 << 8)); in dib3000mc_autosearch_start()
609 dib3000mc_write_word(state, 0, reg); in dib3000mc_autosearch_start()
611 return 0; in dib3000mc_autosearch_start()
619 if (irq_pending & 0x1) // failed in dib3000mc_autosearch_is_irq()
622 if (irq_pending & 0x2) // succeeded in dib3000mc_autosearch_is_irq()
625 return 0; // still pending in dib3000mc_autosearch_is_irq()
634 dib3000mc_set_channel_cfg(state, ch, 0); in dib3000mc_tune()
639 dib3000mc_write_word(state, 29, 0x1273); in dib3000mc_tune()
640 dib3000mc_write_word(state, 108, 0x4000); // P_pha3_force_pha_shift in dib3000mc_tune()
642 dib3000mc_write_word(state, 29, 0x1073); in dib3000mc_tune()
643 dib3000mc_write_word(state, 108, 0x0000); // P_pha3_force_pha_shift in dib3000mc_tune()
655 if (dib3000mc_read_word(state, 509) & 0x80) in dib3000mc_tune()
659 return 0; in dib3000mc_tune()
680 switch ((tps >> 8) & 0x1) { in dib3000mc_get_frontend()
681 case 0: fep->transmission_mode = TRANSMISSION_MODE_2K; break; in dib3000mc_get_frontend()
685 switch (tps & 0x3) { in dib3000mc_get_frontend()
686 case 0: fep->guard_interval = GUARD_INTERVAL_1_32; break; in dib3000mc_get_frontend()
692 switch ((tps >> 13) & 0x3) { in dib3000mc_get_frontend()
693 case 0: fep->modulation = QPSK; break; in dib3000mc_get_frontend()
700 /* (tps >> 12) & 0x1 == hrch is used, (tps >> 9) & 0x7 == alpha */ in dib3000mc_get_frontend()
703 switch ((tps >> 5) & 0x7) { in dib3000mc_get_frontend()
713 switch ((tps >> 2) & 0x7) { in dib3000mc_get_frontend()
722 return 0; in dib3000mc_get_frontend()
754 } while (found == 0 && i--); in dib3000mc_set_frontend()
757 if (found == 0 || found == 1) in dib3000mc_set_frontend()
758 return 0; // no channel found in dib3000mc_set_frontend()
775 *stat = 0; in dib3000mc_read_status()
777 if (lock & 0x8000) in dib3000mc_read_status()
779 if (lock & 0x3000) in dib3000mc_read_status()
781 if (lock & 0x0100) in dib3000mc_read_status()
783 if (lock & 0x0010) in dib3000mc_read_status()
785 if (lock & 0x0008) in dib3000mc_read_status()
788 return 0; in dib3000mc_read_status()
795 return 0; in dib3000mc_read_ber()
802 return 0; in dib3000mc_read_unc_blocks()
810 return 0; in dib3000mc_read_signal_strength()
815 *snr = 0x0000; in dib3000mc_read_snr()
816 return 0; in dib3000mc_read_snr()
822 return 0; in dib3000mc_fe_get_tune_settings()
835 dib3000mc_write_word(state, 212 + index, onoff ? (1 << 13) | pid : 0); in dib3000mc_pid_control()
836 return 0; in dib3000mc_pid_control()
870 for (k = no_of_demods-1; k >= 0; k--) { in dib3000mc_i2c_enumeration()
876 if (dib3000mc_identify(dmcst) != 0) { in dib3000mc_i2c_enumeration()
878 if (dib3000mc_identify(dmcst) != 0) { in dib3000mc_i2c_enumeration()
887 // set new i2c address and force divstr (Bit 1) to value 0 (Bit 0) in dib3000mc_i2c_enumeration()
888 dib3000mc_write_word(dmcst, 1024, (new_addr << 3) | 0x1); in dib3000mc_i2c_enumeration()
892 for (k = 0; k < no_of_demods; k++) { in dib3000mc_i2c_enumeration()
903 return 0; in dib3000mc_i2c_enumeration()
925 if (dib3000mc_identify(st) != 0) in dib3000mc_attach()
930 dib3000mc_write_word(st, 1037, 0x3130); in dib3000mc_attach()