38 	} while (0)
43 	{{0x09,0x01}, /* SoftResetAll */
44 	 {0x09,0x00}, /* release reset */
45 	 {0x01,0xe8}, /* MSB of code rate 27.5MS/s */
46 	 {0x02,0x17}, /* middle byte " */
47 	 {0x03,0x29}, /* LSB         " */
48 	 {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
49 	 {0x06,0xa5}, /* @ PLL 60MHz */
50 	 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
51 	 {0x0a,0x00}, /* @ partial chip disables, do not set */
52 	 {0x0b,0x01}, /* set output clock in gapped mode, start signal low
54 	 {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
55 	 {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
56 	 {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
59 	 {0x15,0xff}, /* @ size of the limited time window for RS BER
62 	 {0x16,0x00}, /* @ enable all RS output ports */
63 	 {0x17,0x04}, /* @ time window allowed for the RS to sync */
64 	 {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
68 	 {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
70 	 {0x23,0x18}, /* @ size of the limited time window for Viterbi BER
73 	 {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
76 	 {0x35,0x40}, /* disable all interrupts. They are not connected anyway */
77 	 {0x36,0xff}, /* clear all interrupt pending flags */
78 	 {0x37,0x00}, /* @ fully enable AutoAcqq state machine */
79 	 {0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
82 	 {0x41,0x00}, /* @ MSB of front-end derotator frequency */
83 	 {0x42,0x00}, /* @ middle bytes " */
84 	 {0x43,0x00}, /* @ LSB          " */
87 	 {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
89 	 {0x57,0x00}, /* @ Filter sigma delta enabled, positive */
90 	 {0x61,0x95}, /* GPIO pins 1-4 have special function */
91 	 {0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
92 	 {0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
93 	 {0x64,0x20}, /* GPIO 6 is input, all others are outputs */
94 	 {0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
95 	 {0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
96 	 {0x73,0x00}, /* @ disable several demod bypasses */
97 	 {0x74,0x00}, /* @  " */
98 	 {0x75,0x00}  /* @  " */
106 	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };  in cx24110_writereg()
110 		dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n",  in cx24110_writereg()
115 	return 0;  in cx24110_writereg()
122 	u8 b1 [] = { 0 };  in cx24110_readreg()
123 …struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 …  in cx24110_readreg()
130 	return b1[0];  in cx24110_readreg()
140 		cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);  in cx24110_set_inversion()
142 		cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7);  in cx24110_set_inversion()
143 		/* Initial value 0 at start of acq */  in cx24110_set_inversion()
144 		cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef);  in cx24110_set_inversion()
145 		/* current value 0 */  in cx24110_set_inversion()
150 		cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);  in cx24110_set_inversion()
152 		cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08);  in cx24110_set_inversion()
154 		cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10);  in cx24110_set_inversion()
158 		cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe);  in cx24110_set_inversion()
165 	return 0;  in cx24110_set_inversion()
171 	static const int g1[FEC_AUTO]   = {-1, 0x01, 0x02, 0x05, 0x15, 0x45, -1};  in cx24110_set_fec()
172 	static const int g2[FEC_AUTO]   = {-1, 0x01, 0x03, 0x06, 0x1a, 0x7a, -1};  in cx24110_set_fec()
182 		cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) & 0xdf);  in cx24110_set_fec()
184 		cx24110_writereg(state, 0x18, 0xae);  in cx24110_set_fec()
186 		cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | 0x3);  in cx24110_set_fec()
188 		cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | 0x3);  in cx24110_set_fec()
190 		cx24110_writereg(state, 0x1a, 0x05);  in cx24110_set_fec()
191 		cx24110_writereg(state, 0x1b, 0x06);  in cx24110_set_fec()
193 		return 0;  in cx24110_set_fec()
195 		cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) | 0x20);  in cx24110_set_fec()
197 		if (rate[fec] < 0)  in cx24110_set_fec()
200 		cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | rate[fec]);  in cx24110_set_fec()
202 		cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | rate[fec]);  in cx24110_set_fec()
204 		cx24110_writereg(state, 0x1a, g1[fec]);  in cx24110_set_fec()
205 		cx24110_writereg(state, 0x1b, g2[fec]);  in cx24110_set_fec()
208 	return 0;  in cx24110_set_fec()
215 	i=cx24110_readreg(state,0x22)&0x0f;  in cx24110_get_fec()
216 	if(!(i&0x08)) {  in cx24110_get_fec()
242 	for(i = 0; (i < ARRAY_SIZE(bands)) && (srate>bands[i]); i++)  in cx24110_set_symbolrate()
245 	   and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,  in cx24110_set_symbolrate()
246 	   R06[3:0] PLLphaseDetGain */  in cx24110_set_symbolrate()
247 	tmp=cx24110_readreg(state,0x07)&0xfc;  in cx24110_set_symbolrate()
249 		cx24110_writereg(state,0x07,tmp);  in cx24110_set_symbolrate()
250 		cx24110_writereg(state,0x06,0x78);  in cx24110_set_symbolrate()
253 		cx24110_writereg(state,0x07,tmp|0x1);  in cx24110_set_symbolrate()
254 		cx24110_writereg(state,0x06,0xa5);  in cx24110_set_symbolrate()
257 		cx24110_writereg(state,0x07,tmp|0x2);  in cx24110_set_symbolrate()
258 		cx24110_writereg(state,0x06,0x87);  in cx24110_set_symbolrate()
261 		cx24110_writereg(state,0x07,tmp|0x3);  in cx24110_set_symbolrate()
262 		cx24110_writereg(state,0x06,0x78);  in cx24110_set_symbolrate()
268 	/* the maximum dividend is 90999000/2, 0x02b6446c, this number is  in cx24110_set_symbolrate()
291 	cx24110_writereg(state, 0x1, (ratio>>16)&0xff);  in cx24110_set_symbolrate()
292 	cx24110_writereg(state, 0x2, (ratio>>8)&0xff);  in cx24110_set_symbolrate()
293 	cx24110_writereg(state, 0x3, (ratio)&0xff);  in cx24110_set_symbolrate()
295 	return 0;  in cx24110_set_symbolrate()
310 	cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */  in _cx24110_pll_write()
311 	cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */  in _cx24110_pll_write()
314 	while (cx24110_readreg(state,0x6d)&0x80)  in _cx24110_pll_write()
315 		cx24110_writereg(state,0x72,0);  in _cx24110_pll_write()
318 	cx24110_writereg(state,0x72,buf[0]);  in _cx24110_pll_write()
321 	while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)  in _cx24110_pll_write()
325 	cx24110_writereg(state,0x72,buf[1]);  in _cx24110_pll_write()
326 	while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)  in _cx24110_pll_write()
330 	cx24110_writereg(state,0x72,buf[2]);  in _cx24110_pll_write()
331 	while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)  in _cx24110_pll_write()
335 	cx24110_writereg(state,0x6d,0x32);  in _cx24110_pll_write()
336 	cx24110_writereg(state,0x6d,0x30);  in _cx24110_pll_write()
338 	return 0;  in _cx24110_pll_write()
349 	for(i = 0; i < ARRAY_SIZE(cx24110_regdata); i++) {  in cx24110_initfe()
353 	return 0;  in cx24110_initfe()
363 		return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0);  in cx24110_set_voltage()
365 		return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40);  in cx24110_set_voltage()
379 		bit = 0x00;  in cx24110_diseqc_send_burst()
381 		bit = 0x08;  in cx24110_diseqc_send_burst()
385 	rv = cx24110_readreg(state, 0x77);  in cx24110_diseqc_send_burst()
386 	if (!(rv & 0x04))  in cx24110_diseqc_send_burst()
387 		cx24110_writereg(state, 0x77, rv | 0x04);  in cx24110_diseqc_send_burst()
389 	rv = cx24110_readreg(state, 0x76);  in cx24110_diseqc_send_burst()
390 	cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40 | bit));  in cx24110_diseqc_send_burst()
392 	while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))  in cx24110_diseqc_send_burst()
395 	return 0;  in cx24110_diseqc_send_burst()
408 	for (i = 0; i < cmd->msg_len; i++)  in cx24110_send_diseqc_msg()
409 		cx24110_writereg(state, 0x79 + i, cmd->msg[i]);  in cx24110_send_diseqc_msg()
411 	rv = cx24110_readreg(state, 0x77);  in cx24110_send_diseqc_msg()
412 	if (rv & 0x04) {  in cx24110_send_diseqc_msg()
413 		cx24110_writereg(state, 0x77, rv & ~0x04);  in cx24110_send_diseqc_msg()
417 	rv = cx24110_readreg(state, 0x76);  in cx24110_send_diseqc_msg()
419 	cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));  in cx24110_send_diseqc_msg()
421 	while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))  in cx24110_send_diseqc_msg()
424 	return 0;  in cx24110_send_diseqc_msg()
432 	int sync = cx24110_readreg (state, 0x55);  in cx24110_read_status()
434 	*status = 0;  in cx24110_read_status()
436 	if (sync & 0x10)  in cx24110_read_status()
439 	if (sync & 0x08)  in cx24110_read_status()
442 	sync = cx24110_readreg (state, 0x08);  in cx24110_read_status()
444 	if (sync & 0x40)  in cx24110_read_status()
447 	if (sync & 0x20)  in cx24110_read_status()
450 	if ((sync & 0x60) == 0x60)  in cx24110_read_status()
453 	return 0;  in cx24110_read_status()
461 	if(cx24110_readreg(state,0x24)&0x10) {  in cx24110_read_ber()
463 		cx24110_writereg(state,0x24,0x04); /* select the ber reg */  in cx24110_read_ber()
464 		state->lastber=cx24110_readreg(state,0x25)|  in cx24110_read_ber()
465 			(cx24110_readreg(state,0x26)<<8);  in cx24110_read_ber()
466 		cx24110_writereg(state,0x24,0x04); /* start new count window */  in cx24110_read_ber()
467 		cx24110_writereg(state,0x24,0x14);  in cx24110_read_ber()
471 	return 0;  in cx24110_read_ber()
479 	u8 signal = cx24110_readreg (state, 0x27)+128;  in cx24110_read_signal_strength()
482 	return 0;  in cx24110_read_signal_strength()
490 	if(cx24110_readreg(state,0x6a)&0x80) {  in cx24110_read_snr()
492 		state->lastesn0=cx24110_readreg(state,0x69)|  in cx24110_read_snr()
493 			(cx24110_readreg(state,0x68)<<8);  in cx24110_read_snr()
494 		cx24110_writereg(state,0x6a,0x84); /* start new count window */  in cx24110_read_snr()
498 	return 0;  in cx24110_read_snr()
505 	if(cx24110_readreg(state,0x10)&0x40) {  in cx24110_read_ucblocks()
507 		cx24110_writereg(state,0x10,0x60); /* select the byer reg */  in cx24110_read_ucblocks()
508 		(void)(cx24110_readreg(state, 0x12) |  in cx24110_read_ucblocks()
509 			(cx24110_readreg(state, 0x13) << 8) |  in cx24110_read_ucblocks()
510 			(cx24110_readreg(state, 0x14) << 16));  in cx24110_read_ucblocks()
511 		cx24110_writereg(state,0x10,0x70); /* select the bler reg */  in cx24110_read_ucblocks()
512 		state->lastbler=cx24110_readreg(state,0x12)|  in cx24110_read_ucblocks()
513 			(cx24110_readreg(state,0x13)<<8)|  in cx24110_read_ucblocks()
514 			(cx24110_readreg(state,0x14)<<16);  in cx24110_read_ucblocks()
515 		cx24110_writereg(state,0x10,0x20); /* start new count window */  in cx24110_read_ucblocks()
519 	return 0;  in cx24110_read_ucblocks()
529 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);  in cx24110_set_frontend()
535 	cx24110_writereg(state,0x04,0x05); /* start acquisition */  in cx24110_set_frontend()
537 	return 0;  in cx24110_set_frontend()
548 	sclk = cx24110_readreg (state, 0x07) & 0x03;  in cx24110_get_frontend()
551 	if (sclk==0) sclk=90999000L/2L;  in cx24110_get_frontend()
556 	afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+  in cx24110_get_frontend()
557 	      ((sclk*cx24110_readreg (state, 0x45))>>8)+  in cx24110_get_frontend()
558 	      ((sclk*cx24110_readreg (state, 0x46))>>16);  in cx24110_get_frontend()
561 	p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ?  in cx24110_get_frontend()
565 	return 0;  in cx24110_get_frontend()
573 …return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10…  in cx24110_set_tone()
597 	state->lastber = 0;  in cx24110_attach()
598 	state->lastbler = 0;  in cx24110_attach()
599 	state->lastesn0 = 0;  in cx24110_attach()
602 	ret = cx24110_readreg(state, 0x00);  in cx24110_attach()
603 	if ((ret != 0x5a) && (ret != 0x69)) goto error;  in cx24110_attach()