Lines Matching +full:mt8196 +full:- +full:gpufreq
1 // SPDX-License-Identifier: GPL-2.0-only
3 * MediaTek GPUEB mailbox driver for SoCs such as the MT8196
8 * - Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
44 * struct mtk_gpueb_mbox_chan - per-channel runtime data
60 * struct mtk_gpueb_mbox_chan_desc - per-channel constant data
83 * mtk_gpueb_mbox_read_rx - read RX buffer from MMIO into channel's RX buffer
89 memcpy_fromio(buf, chan->ebm->mbox_mmio + chan->c->rx_offset, chan->c->rx_len); in mtk_gpueb_mbox_read_rx()
97 rx_sts = readl(ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_RX_STS); in mtk_gpueb_mbox_isr()
99 if (rx_sts & BIT(ch->num)) { in mtk_gpueb_mbox_isr()
100 if (!atomic_cmpxchg(&ch->rx_status, 0, GPUEB_MBOX_FULL | GPUEB_MBOX_BLOCKED)) in mtk_gpueb_mbox_isr()
112 status = atomic_cmpxchg(&ch->rx_status, GPUEB_MBOX_FULL | GPUEB_MBOX_BLOCKED, in mtk_gpueb_mbox_thread()
118 writel(BIT(ch->num), ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_IRQ_CLR); in mtk_gpueb_mbox_thread()
119 mbox_chan_received_data(&ch->ebm->mbox.chans[ch->num], buf); in mtk_gpueb_mbox_thread()
120 atomic_set(&ch->rx_status, 0); in mtk_gpueb_mbox_thread()
129 struct mtk_gpueb_mbox_chan *ch = chan->con_priv; in mtk_gpueb_mbox_send_data()
133 if (atomic_read(&ch->rx_status)) in mtk_gpueb_mbox_send_data()
134 return -EBUSY; in mtk_gpueb_mbox_send_data()
137 * We don't want any fancy nonsense, just write the 32-bit values in in mtk_gpueb_mbox_send_data()
142 for (i = 0; i < ch->c->tx_len; i += 4) in mtk_gpueb_mbox_send_data()
143 writel(values[i / 4], ch->ebm->mbox_mmio + ch->c->tx_offset + i); in mtk_gpueb_mbox_send_data()
145 writel(BIT(ch->num), ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_IRQ_SET); in mtk_gpueb_mbox_send_data()
152 struct mtk_gpueb_mbox_chan *ch = chan->con_priv; in mtk_gpueb_mbox_startup()
155 atomic_set(&ch->rx_status, 0); in mtk_gpueb_mbox_startup()
157 ret = clk_enable(ch->ebm->clk); in mtk_gpueb_mbox_startup()
159 dev_err(ch->ebm->dev, "Failed to enable EB clock: %pe\n", in mtk_gpueb_mbox_startup()
164 writel(BIT(ch->num), ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_IRQ_CLR); in mtk_gpueb_mbox_startup()
166 ret = devm_request_threaded_irq(ch->ebm->dev, ch->ebm->irq, mtk_gpueb_mbox_isr, in mtk_gpueb_mbox_startup()
168 ch->full_name, ch); in mtk_gpueb_mbox_startup()
170 dev_err(ch->ebm->dev, "Failed to request IRQ: %pe\n", in mtk_gpueb_mbox_startup()
178 clk_disable(ch->ebm->clk); in mtk_gpueb_mbox_startup()
180 atomic_set(&ch->rx_status, GPUEB_MBOX_BLOCKED); in mtk_gpueb_mbox_startup()
187 struct mtk_gpueb_mbox_chan *ch = chan->con_priv; in mtk_gpueb_mbox_shutdown()
189 atomic_set(&ch->rx_status, GPUEB_MBOX_BLOCKED); in mtk_gpueb_mbox_shutdown()
191 devm_free_irq(ch->ebm->dev, ch->ebm->irq, ch); in mtk_gpueb_mbox_shutdown()
193 clk_disable(ch->ebm->clk); in mtk_gpueb_mbox_shutdown()
198 struct mtk_gpueb_mbox_chan *ch = chan->con_priv; in mtk_gpueb_mbox_last_tx_done()
200 return !(readl(ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_TX_STS) & BIT(ch->num)); in mtk_gpueb_mbox_last_tx_done()
216 ebm = devm_kzalloc(&pdev->dev, sizeof(*ebm), GFP_KERNEL); in mtk_gpueb_mbox_probe()
218 return -ENOMEM; in mtk_gpueb_mbox_probe()
220 ebm->dev = &pdev->dev; in mtk_gpueb_mbox_probe()
221 ebm->v = of_device_get_match_data(ebm->dev); in mtk_gpueb_mbox_probe()
223 ebm->irq = platform_get_irq(pdev, 0); in mtk_gpueb_mbox_probe()
224 if (ebm->irq < 0) in mtk_gpueb_mbox_probe()
225 return ebm->irq; in mtk_gpueb_mbox_probe()
227 ebm->clk = devm_clk_get_prepared(ebm->dev, NULL); in mtk_gpueb_mbox_probe()
228 if (IS_ERR(ebm->clk)) in mtk_gpueb_mbox_probe()
229 return dev_err_probe(ebm->dev, PTR_ERR(ebm->clk), in mtk_gpueb_mbox_probe()
232 ebm->mbox_mmio = devm_platform_ioremap_resource(pdev, 0); in mtk_gpueb_mbox_probe()
233 if (IS_ERR(ebm->mbox_mmio)) in mtk_gpueb_mbox_probe()
234 return dev_err_probe(ebm->dev, PTR_ERR(ebm->mbox_mmio), in mtk_gpueb_mbox_probe()
237 ebm->mbox_ctl = devm_platform_ioremap_resource(pdev, 1); in mtk_gpueb_mbox_probe()
238 if (IS_ERR(ebm->mbox_ctl)) in mtk_gpueb_mbox_probe()
240 ebm->dev, PTR_ERR(ebm->mbox_ctl), in mtk_gpueb_mbox_probe()
243 ebm->ch = devm_kmalloc_array(ebm->dev, ebm->v->num_channels, in mtk_gpueb_mbox_probe()
244 sizeof(*ebm->ch), GFP_KERNEL); in mtk_gpueb_mbox_probe()
245 if (!ebm->ch) in mtk_gpueb_mbox_probe()
246 return -ENOMEM; in mtk_gpueb_mbox_probe()
248 ebm->mbox.chans = devm_kcalloc(ebm->dev, ebm->v->num_channels, in mtk_gpueb_mbox_probe()
250 if (!ebm->mbox.chans) in mtk_gpueb_mbox_probe()
251 return -ENOMEM; in mtk_gpueb_mbox_probe()
253 for (i = 0; i < ebm->v->num_channels; i++) { in mtk_gpueb_mbox_probe()
254 ch = &ebm->ch[i]; in mtk_gpueb_mbox_probe()
255 ch->c = &ebm->v->channels[i]; in mtk_gpueb_mbox_probe()
256 if (ch->c->rx_len > GPUEB_MBOX_MAX_RX_SIZE) { in mtk_gpueb_mbox_probe()
257 dev_err(ebm->dev, "Channel %s RX size (%d) too large\n", in mtk_gpueb_mbox_probe()
258 ch->c->name, ch->c->rx_len); in mtk_gpueb_mbox_probe()
259 return -EINVAL; in mtk_gpueb_mbox_probe()
261 ch->full_name = devm_kasprintf(ebm->dev, GFP_KERNEL, "%s:%s", in mtk_gpueb_mbox_probe()
262 dev_name(ebm->dev), ch->c->name); in mtk_gpueb_mbox_probe()
263 if (!ch->full_name) in mtk_gpueb_mbox_probe()
264 return -ENOMEM; in mtk_gpueb_mbox_probe()
266 ch->ebm = ebm; in mtk_gpueb_mbox_probe()
267 ch->num = i; in mtk_gpueb_mbox_probe()
268 spin_lock_init(&ebm->mbox.chans[i].lock); in mtk_gpueb_mbox_probe()
269 ebm->mbox.chans[i].con_priv = ch; in mtk_gpueb_mbox_probe()
270 atomic_set(&ch->rx_status, GPUEB_MBOX_BLOCKED); in mtk_gpueb_mbox_probe()
273 ebm->mbox.dev = ebm->dev; in mtk_gpueb_mbox_probe()
274 ebm->mbox.num_chans = ebm->v->num_channels; in mtk_gpueb_mbox_probe()
275 ebm->mbox.txdone_poll = true; in mtk_gpueb_mbox_probe()
276 ebm->mbox.txpoll_period = 0; /* minimum hrtimer interval */ in mtk_gpueb_mbox_probe()
277 ebm->mbox.ops = &mtk_gpueb_mbox_ops; in mtk_gpueb_mbox_probe()
279 dev_set_drvdata(ebm->dev, ebm); in mtk_gpueb_mbox_probe()
281 return devm_mbox_controller_register(ebm->dev, &ebm->mbox); in mtk_gpueb_mbox_probe()
287 { "fast-dvfs-event", 0, 0x0000, 16, 0x00e0, 16 },
288 { "gpufreq", 1, 0x0010, 32, 0x00f0, 32 },
294 { "fast-dvfs", 7, 0x00a0, 24, 0x0130, 24 },
295 { "ipir-c-met", 8, 0x00b8, 4, 0x0148, 16 },
296 { "ipis-c-met", 9, 0x00bc, 16, 0x0158, 4 },
303 { .compatible = "mediatek,mt8196-gpueb-mbox", .data = &mtk_gpueb_mbox_mt8196 },
311 .name = "mtk-gpueb-mbox",