Lines Matching +full:imx6sx +full:- +full:mu
1 // SPDX-License-Identifier: GPL-2.0
29 /* TX0/RX0/RXDB[0-3] */
127 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
128 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
129 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
132 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
134 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
136 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
138 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
139 /* MU reset */
151 iowrite32(val, priv->base + offs); in imx_mu_write()
156 return ioread32(priv->base + offs); in imx_mu_read()
165 dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx); in imx_mu_tx_waiting_write()
168 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); in imx_mu_tx_waiting_write()
169 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4); in imx_mu_tx_waiting_write()
173 dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n", in imx_mu_tx_waiting_write()
175 return -ETIME; in imx_mu_tx_waiting_write()
178 imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4); in imx_mu_tx_waiting_write()
189 dev_dbg(priv->dev, "Trying to read from idx %d\n", idx); in imx_mu_rx_waiting_read()
192 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); in imx_mu_rx_waiting_read()
193 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4); in imx_mu_rx_waiting_read()
197 dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n", in imx_mu_rx_waiting_read()
199 return -ETIME; in imx_mu_rx_waiting_read()
202 *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4); in imx_mu_rx_waiting_read()
203 dev_dbg(priv->dev, "Read %.8x\n", *val); in imx_mu_rx_waiting_read()
213 spin_lock_irqsave(&priv->xcr_lock, flags); in imx_mu_xcr_rmw()
214 val = imx_mu_read(priv, priv->dcfg->xCR[type]); in imx_mu_xcr_rmw()
217 imx_mu_write(priv, val, priv->dcfg->xCR[type]); in imx_mu_xcr_rmw()
218 spin_unlock_irqrestore(&priv->xcr_lock, flags); in imx_mu_xcr_rmw()
231 switch (cp->type) { in imx_mu_generic_tx()
233 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4); in imx_mu_generic_tx()
234 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); in imx_mu_generic_tx()
237 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); in imx_mu_generic_tx()
238 queue_work(system_bh_wq, &cp->txdb_work); in imx_mu_generic_tx()
241 imx_mu_write(priv, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), in imx_mu_generic_tx()
242 priv->dcfg->xCR[IMX_MU_GCR]); in imx_mu_generic_tx()
243 ret = readl_poll_timeout(priv->base + priv->dcfg->xCR[IMX_MU_GCR], val, in imx_mu_generic_tx()
244 !(val & IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx)), in imx_mu_generic_tx()
247 dev_warn_ratelimited(priv->dev, "channel type: %d failure\n", cp->type); in imx_mu_generic_tx()
250 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); in imx_mu_generic_tx()
251 return -EINVAL; in imx_mu_generic_tx()
262 dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4); in imx_mu_generic_rx()
263 mbox_chan_received_data(cp->chan, (void *)&dat); in imx_mu_generic_rx()
271 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), in imx_mu_generic_rxdb()
272 priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_generic_rxdb()
273 mbox_chan_received_data(cp->chan, NULL); in imx_mu_generic_rxdb()
281 u32 num_tr = priv->num_tr; in imx_mu_specific_tx()
286 if (priv->dcfg->type & IMX_MU_V2_S4) { in imx_mu_specific_tx()
287 size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size; in imx_mu_specific_tx()
290 size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size; in imx_mu_specific_tx()
294 switch (cp->type) { in imx_mu_specific_tx()
297 * msg->hdr.size specifies the number of u32 words while in imx_mu_specific_tx()
306 …dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, si… in imx_mu_specific_tx()
307 return -EINVAL; in imx_mu_specific_tx()
311 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); in imx_mu_specific_tx()
313 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR], in imx_mu_specific_tx()
315 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr), in imx_mu_specific_tx()
318 dev_err(priv->dev, "Send data index: %d timeout\n", i); in imx_mu_specific_tx()
321 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); in imx_mu_specific_tx()
324 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); in imx_mu_specific_tx()
327 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); in imx_mu_specific_tx()
328 return -EINVAL; in imx_mu_specific_tx()
340 u32 num_rr = priv->num_rr; in imx_mu_specific_rx()
342 data = (u32 *)priv->msg; in imx_mu_specific_rx()
344 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0)); in imx_mu_specific_rx()
345 *data++ = imx_mu_read(priv, priv->dcfg->xRR); in imx_mu_specific_rx()
347 if (priv->dcfg->type & IMX_MU_V2_S4) { in imx_mu_specific_rx()
348 size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size; in imx_mu_specific_rx()
351 size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size; in imx_mu_specific_rx()
356 …dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, si… in imx_mu_specific_rx()
357 return -EINVAL; in imx_mu_specific_rx()
361 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr, in imx_mu_specific_rx()
362 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0, in imx_mu_specific_rx()
365 dev_err(priv->dev, "timeout read idx %d\n", i); in imx_mu_specific_rx()
368 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4); in imx_mu_specific_rx()
371 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0); in imx_mu_specific_rx()
372 mbox_chan_received_data(cp->chan, (void *)priv->msg); in imx_mu_specific_rx()
386 dev_dbg(priv->dev, "Sending message\n"); in imx_mu_seco_tx()
388 switch (cp->type) { in imx_mu_seco_tx()
390 byte_size = msg->hdr.size * sizeof(u32); in imx_mu_seco_tx()
396 dev_err(priv->dev, in imx_mu_seco_tx()
399 return -EINVAL; in imx_mu_seco_tx()
406 dev_dbg(priv->dev, "Sending header\n"); in imx_mu_seco_tx()
407 imx_mu_write(priv, *arg++, priv->dcfg->xTR); in imx_mu_seco_tx()
410 dev_dbg(priv->dev, "Sending signaling\n"); in imx_mu_seco_tx()
412 IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); in imx_mu_seco_tx()
415 for (i = 1; i < 4 && i < msg->hdr.size; i++) { in imx_mu_seco_tx()
416 dev_dbg(priv->dev, "Sending word %d\n", i); in imx_mu_seco_tx()
418 priv->dcfg->xTR + (i % 4) * 4); in imx_mu_seco_tx()
422 for (; i < msg->hdr.size; i++) { in imx_mu_seco_tx()
423 dev_dbg(priv->dev, "Sending word %d\n", i); in imx_mu_seco_tx()
426 dev_err(priv->dev, "Timeout tx %d\n", i); in imx_mu_seco_tx()
432 queue_work(system_bh_wq, &cp->txdb_work); in imx_mu_seco_tx()
436 dev_warn_ratelimited(priv->dev, in imx_mu_seco_tx()
438 cp->type); in imx_mu_seco_tx()
439 return -EINVAL; in imx_mu_seco_tx()
453 dev_dbg(priv->dev, "Receiving message\n"); in imx_mu_seco_rxdb()
456 dev_dbg(priv->dev, "Receiving header\n"); in imx_mu_seco_rxdb()
457 *data++ = imx_mu_read(priv, priv->dcfg->xRR); in imx_mu_seco_rxdb()
460 dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n", in imx_mu_seco_rxdb()
462 err = -EINVAL; in imx_mu_seco_rxdb()
468 dev_dbg(priv->dev, "Receiving word %d\n", i); in imx_mu_seco_rxdb()
471 dev_err(priv->dev, "Timeout rx %d\n", i); in imx_mu_seco_rxdb()
477 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), in imx_mu_seco_rxdb()
478 priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_seco_rxdb()
484 dev_dbg(priv->dev, "Sending message to client\n"); in imx_mu_seco_rxdb()
485 mbox_chan_received_data(cp->chan, (void *)&msg); in imx_mu_seco_rxdb()
490 mbox_chan_received_data(cp->chan, ERR_PTR(err)); in imx_mu_seco_rxdb()
500 mbox_chan_txdone(cp->chan, 0); in imx_mu_txdb_work()
506 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_isr()
507 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_isr()
510 switch (cp->type) { in imx_mu_isr()
512 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]); in imx_mu_isr()
513 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); in imx_mu_isr()
514 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) & in imx_mu_isr()
515 (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); in imx_mu_isr()
518 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]); in imx_mu_isr()
519 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); in imx_mu_isr()
520 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) & in imx_mu_isr()
521 (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); in imx_mu_isr()
524 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]); in imx_mu_isr()
525 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_isr()
526 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) & in imx_mu_isr()
527 (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); in imx_mu_isr()
532 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n", in imx_mu_isr()
533 cp->type); in imx_mu_isr()
540 if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) && in imx_mu_isr()
541 (cp->type == IMX_MU_TYPE_TX)) { in imx_mu_isr()
542 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); in imx_mu_isr()
544 } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) && in imx_mu_isr()
545 (cp->type == IMX_MU_TYPE_RX)) { in imx_mu_isr()
546 priv->dcfg->rx(priv, cp); in imx_mu_isr()
547 } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) && in imx_mu_isr()
548 (cp->type == IMX_MU_TYPE_RXDB)) { in imx_mu_isr()
549 priv->dcfg->rxdb(priv, cp); in imx_mu_isr()
551 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); in imx_mu_isr()
555 if (priv->suspend) in imx_mu_isr()
563 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_send_data()
564 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_send_data()
566 return priv->dcfg->tx(priv, cp, data); in imx_mu_send_data()
571 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_startup()
572 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_startup()
576 pm_runtime_get_sync(priv->dev); in imx_mu_startup()
577 if (cp->type == IMX_MU_TYPE_TXDB_V2) in imx_mu_startup()
580 if (cp->type == IMX_MU_TYPE_TXDB) { in imx_mu_startup()
582 INIT_WORK(&cp->txdb_work, imx_mu_txdb_work); in imx_mu_startup()
586 /* IPC MU should be with IRQF_NO_SUSPEND set */ in imx_mu_startup()
587 if (!priv->dev->pm_domain) in imx_mu_startup()
590 if (!(priv->dcfg->type & IMX_MU_V2_IRQ)) in imx_mu_startup()
593 ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan); in imx_mu_startup()
595 dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]); in imx_mu_startup()
599 switch (cp->type) { in imx_mu_startup()
601 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0); in imx_mu_startup()
604 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0); in imx_mu_startup()
615 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_shutdown()
616 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_shutdown()
620 if (cp->type == IMX_MU_TYPE_TXDB_V2) { in imx_mu_shutdown()
621 pm_runtime_put_sync(priv->dev); in imx_mu_shutdown()
625 if (cp->type == IMX_MU_TYPE_TXDB) { in imx_mu_shutdown()
626 cancel_work_sync(&cp->txdb_work); in imx_mu_shutdown()
627 pm_runtime_put_sync(priv->dev); in imx_mu_shutdown()
631 switch (cp->type) { in imx_mu_shutdown()
633 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); in imx_mu_shutdown()
636 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); in imx_mu_shutdown()
639 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); in imx_mu_shutdown()
642 imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0); in imx_mu_shutdown()
643 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr, in imx_mu_shutdown()
644 !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5); in imx_mu_shutdown()
646 dev_warn(priv->dev, "RST channel timeout\n"); in imx_mu_shutdown()
652 free_irq(priv->irq[cp->type], chan); in imx_mu_shutdown()
653 pm_runtime_put_sync(priv->dev); in imx_mu_shutdown()
667 if (sp->args_count != 2) { in imx_mu_specific_xlate()
668 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_specific_xlate()
669 return ERR_PTR(-EINVAL); in imx_mu_specific_xlate()
672 type = sp->args[0]; /* channel type */ in imx_mu_specific_xlate()
673 idx = sp->args[1]; /* index */ in imx_mu_specific_xlate()
679 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx); in imx_mu_specific_xlate()
686 dev_err(mbox->dev, "Invalid chan type: %d\n", type); in imx_mu_specific_xlate()
687 return ERR_PTR(-EINVAL); in imx_mu_specific_xlate()
690 if (chan >= mbox->num_chans) { in imx_mu_specific_xlate()
691 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); in imx_mu_specific_xlate()
692 return ERR_PTR(-EINVAL); in imx_mu_specific_xlate()
695 return &mbox->chans[chan]; in imx_mu_specific_xlate()
704 if (sp->args_count != 2) { in imx_mu_xlate()
705 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_xlate()
706 return ERR_PTR(-EINVAL); in imx_mu_xlate()
709 type = sp->args[0]; /* channel type */ in imx_mu_xlate()
710 idx = sp->args[1]; /* index */ in imx_mu_xlate()
714 dev_err(mbox->dev, "Invalid RST channel %d\n", idx); in imx_mu_xlate()
715 return ERR_PTR(-EINVAL); in imx_mu_xlate()
719 if (chan >= mbox->num_chans) { in imx_mu_xlate()
720 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); in imx_mu_xlate()
721 return ERR_PTR(-EINVAL); in imx_mu_xlate()
724 p_chan = &mbox->chans[chan]; in imx_mu_xlate()
727 p_chan->txdone_method = TXDONE_BY_ACK; in imx_mu_xlate()
737 if (sp->args_count < 1) { in imx_mu_seco_xlate()
738 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_seco_xlate()
739 return ERR_PTR(-EINVAL); in imx_mu_seco_xlate()
742 type = sp->args[0]; /* channel type */ in imx_mu_seco_xlate()
746 dev_err(mbox->dev, "Invalid type: %d\n", type); in imx_mu_seco_xlate()
747 return ERR_PTR(-EINVAL); in imx_mu_seco_xlate()
757 if (priv->dcfg->type & IMX_MU_V2) { in imx_mu_get_tr_rr()
759 priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val); in imx_mu_get_tr_rr()
760 priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val); in imx_mu_get_tr_rr()
762 priv->num_tr = 4; in imx_mu_get_tr_rr()
763 priv->num_rr = 4; in imx_mu_get_tr_rr()
772 if (priv->num_rr > 4 || priv->num_tr > 4) { in imx_mu_init_generic()
774 return -EOPNOTSUPP; in imx_mu_init_generic()
778 struct imx_mu_con_priv *cp = &priv->con_priv[i]; in imx_mu_init_generic()
780 cp->idx = i % 4; in imx_mu_init_generic()
781 cp->type = i >> 2; in imx_mu_init_generic()
782 cp->chan = &priv->mbox_chans[i]; in imx_mu_init_generic()
783 priv->mbox_chans[i].con_priv = cp; in imx_mu_init_generic()
784 snprintf(cp->irq_desc, sizeof(cp->irq_desc), in imx_mu_init_generic()
785 "%s[%i-%i]", dev_name(priv->dev), cp->type, cp->idx); in imx_mu_init_generic()
788 priv->mbox.num_chans = IMX_MU_CHANS; in imx_mu_init_generic()
789 priv->mbox.of_xlate = imx_mu_xlate; in imx_mu_init_generic()
791 if (priv->side_b) in imx_mu_init_generic()
794 /* Set default MU configuration */ in imx_mu_init_generic()
796 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); in imx_mu_init_generic()
799 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_init_generic()
800 imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_init_generic()
803 for (i = 0; i < priv->num_rr; i++) in imx_mu_init_generic()
804 imx_mu_read(priv, priv->dcfg->xRR + i * 4); in imx_mu_init_generic()
812 int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS; in imx_mu_init_specific()
815 struct imx_mu_con_priv *cp = &priv->con_priv[i]; in imx_mu_init_specific()
817 cp->idx = i < 2 ? 0 : i - 2; in imx_mu_init_specific()
818 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB; in imx_mu_init_specific()
819 cp->chan = &priv->mbox_chans[i]; in imx_mu_init_specific()
820 priv->mbox_chans[i].con_priv = cp; in imx_mu_init_specific()
821 snprintf(cp->irq_desc, sizeof(cp->irq_desc), in imx_mu_init_specific()
822 "%s[%i-%i]", dev_name(priv->dev), cp->type, cp->idx); in imx_mu_init_specific()
825 priv->mbox.num_chans = num_chans; in imx_mu_init_specific()
826 priv->mbox.of_xlate = imx_mu_specific_xlate; in imx_mu_init_specific()
828 /* Set default MU configuration */ in imx_mu_init_specific()
830 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); in imx_mu_init_specific()
842 priv->mbox.of_xlate = imx_mu_seco_xlate; in imx_mu_init_seco()
849 struct device *dev = &pdev->dev; in imx_mu_probe()
850 struct device_node *np = dev->of_node; in imx_mu_probe()
858 return -ENOMEM; in imx_mu_probe()
860 priv->dev = dev; in imx_mu_probe()
862 priv->base = devm_platform_ioremap_resource(pdev, 0); in imx_mu_probe()
863 if (IS_ERR(priv->base)) in imx_mu_probe()
864 return PTR_ERR(priv->base); in imx_mu_probe()
868 return -EINVAL; in imx_mu_probe()
869 priv->dcfg = dcfg; in imx_mu_probe()
870 if (priv->dcfg->type & IMX_MU_V2_IRQ) { in imx_mu_probe()
871 priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx"); in imx_mu_probe()
872 if (priv->irq[IMX_MU_TYPE_TX] < 0) in imx_mu_probe()
873 return priv->irq[IMX_MU_TYPE_TX]; in imx_mu_probe()
874 priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx"); in imx_mu_probe()
875 if (priv->irq[IMX_MU_TYPE_RX] < 0) in imx_mu_probe()
876 return priv->irq[IMX_MU_TYPE_RX]; in imx_mu_probe()
883 priv->irq[i] = ret; in imx_mu_probe()
886 if (priv->dcfg->type & IMX_MU_V2_S4) in imx_mu_probe()
891 priv->msg = devm_kzalloc(dev, size, GFP_KERNEL); in imx_mu_probe()
892 if (!priv->msg) in imx_mu_probe()
893 return -ENOMEM; in imx_mu_probe()
895 priv->clk = devm_clk_get(dev, NULL); in imx_mu_probe()
896 if (IS_ERR(priv->clk)) { in imx_mu_probe()
897 if (PTR_ERR(priv->clk) != -ENOENT) in imx_mu_probe()
898 return PTR_ERR(priv->clk); in imx_mu_probe()
900 priv->clk = NULL; in imx_mu_probe()
903 ret = clk_prepare_enable(priv->clk); in imx_mu_probe()
911 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); in imx_mu_probe()
913 ret = priv->dcfg->init(priv); in imx_mu_probe()
915 dev_err(dev, "Failed to init MU\n"); in imx_mu_probe()
919 spin_lock_init(&priv->xcr_lock); in imx_mu_probe()
921 priv->mbox.dev = dev; in imx_mu_probe()
922 priv->mbox.ops = &imx_mu_ops; in imx_mu_probe()
923 priv->mbox.chans = priv->mbox_chans; in imx_mu_probe()
924 priv->mbox.txdone_irq = true; in imx_mu_probe()
928 ret = devm_mbox_controller_register(dev, &priv->mbox); in imx_mu_probe()
932 of_platform_populate(dev->of_node, NULL, NULL, dev); in imx_mu_probe()
944 clk_disable_unprepare(priv->clk); in imx_mu_probe()
951 clk_disable_unprepare(priv->clk); in imx_mu_probe()
959 pm_runtime_disable(priv->dev); in imx_mu_remove()
1041 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
1042 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
1043 { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
1044 { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
1045 { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
1046 { .compatible = "fsl,imx95-mu", .data = &imx_mu_cfg_imx8ulp },
1047 { .compatible = "fsl,imx95-mu-ele", .data = &imx_mu_cfg_imx8ulp_s4 },
1048 { .compatible = "fsl,imx95-mu-v2x", .data = &imx_mu_cfg_imx8ulp_s4 },
1049 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
1050 { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
1060 if (!priv->clk) { in imx_mu_suspend_noirq()
1062 priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]); in imx_mu_suspend_noirq()
1065 priv->suspend = true; in imx_mu_suspend_noirq()
1076 * ONLY restore MU when context lost, the TIE could in imx_mu_resume_noirq()
1077 * be set during noirq resume as there is MU data in imx_mu_resume_noirq()
1079 * value will overwrite the TIE and cause MU data in imx_mu_resume_noirq()
1083 if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) { in imx_mu_resume_noirq()
1085 imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]); in imx_mu_resume_noirq()
1088 priv->suspend = false; in imx_mu_resume_noirq()
1097 clk_disable_unprepare(priv->clk); in imx_mu_runtime_suspend()
1107 ret = clk_prepare_enable(priv->clk); in imx_mu_runtime_resume()