Lines Matching full:descriptor
20 * The PDC driver allows multiple messages to be pending in the descriptor
21 * rings. The tx_msg_start descriptor index indicates where the last message
22 * starts. The txin_numd value at this index indicates how many descriptor
55 * Minimum number of ring descriptor entries that must be free to tell mailbox
68 /* descriptor bumping macros */
141 /* descriptor flags */
142 #define D64_CTRL1_EOT BIT(28) /* end of descriptor table */
161 /* dma descriptor */
172 u32 ptr; /* last descriptor posted to chip */
173 u32 addrlow; /* descriptor ring base address low 32-bits */
174 u32 addrhigh; /* descriptor ring base address bits 63:32 */
175 u32 status0; /* last rx descriptor written by hw */
256 * context associated with a receive descriptor.
262 * at a descriptor index. Not set for every index. For example,
263 * if descriptor index i points to a scatterlist with 4 entries,
264 * then the next three descriptor indexes don't have a value set.
313 * The base virtual address of DMA tx/rx descriptor rings. Corresponding
328 struct dma64dd *txd_64; /* tx descriptor ring */
329 struct dma64dd *rxd_64; /* rx descriptor ring */
331 /* descriptor ring sizes */
338 * Index of next tx descriptor to reclaim. That is, the descriptor
345 * Index of the first receive descriptor for the sequence of
352 /* Index of next tx descriptor to post. */
357 * at this tx descriptor index.
362 * Index of next rx descriptor to reclaim. This is the index of
363 * the next descriptor whose data has yet to be processed by the host.
368 * Index of the first receive descriptor for the sequence of
376 * Saved value of current hardware rx descriptor index.
382 /* Index of next rx descriptor to post. */
400 u32 txnobuf; /* unable to create tx descriptor */
401 u32 rxnobuf; /* unable to create rx descriptor */
509 * pdc_build_rxd() - Build DMA descriptor to receive SPU result.
511 * @dma_addr: DMA address of buffer that descriptor is being built for
513 * @flags: Flags to be stored in descriptor
523 "Writing rx descriptor for PDC %u at index %u with length %u. flags %#x\n", in pdc_build_rxd()
536 * pdc_build_txd() - Build a DMA descriptor to transmit a SPU request to
541 * @flags: Flags to be stored in descriptor
551 "Writing tx descriptor for PDC %u at index %u with length %u, flags %#x\n", in pdc_build_txd()
709 * Num descriptors needed. Conservatively assume we need a descriptor in pdc_tx_list_sg_add()
714 u32 bufcnt; /* Number of bytes of buffer pointed to by descriptor */ in pdc_tx_list_sg_add()
715 dma_addr_t databufptr; /* DMA address to put in descriptor */ in pdc_tx_list_sg_add()
760 /* Writing last descriptor for frame */ in pdc_tx_list_sg_add()
764 /* Clear start of frame after first descriptor */ in pdc_tx_list_sg_add()
777 * Sets the index of the last descriptor written in both the rx and tx ring.
796 * pdc_rx_list_init() - Start a new receive descriptor list for a given PDC.
802 * Posts a single receive descriptor to hold the metadata that precedes a
804 * an 8-byte BCM header. Moves the msg_start descriptor indexes for both tx and
834 * of a new sequence of descriptor indexes that contain the fragments in pdc_rx_list_init()
840 /* This is always the first descriptor in the receive sequence */ in pdc_rx_list_init()
876 * Num descriptors needed. Conservatively assume we need a descriptor in pdc_rx_list_sg_add()
881 u32 bufcnt; /* Number of bytes of buffer pointed to by descriptor */ in pdc_rx_list_sg_add()
882 dma_addr_t databufptr; /* DMA address to put in descriptor */ in pdc_rx_list_sg_add()
1019 /* Set descriptor array base addresses */ in pdc_ring_init()
1051 /* Every tx descriptor can be used for start of frame. */ in pdc_ring_init()
1056 /* Last descriptor in ringset. Set End of Table. */ in pdc_ring_init()
1061 /* Every rx descriptor can be used for start of frame */ in pdc_ring_init()
1066 /* Last descriptor in ringset. Set End of Table. */ in pdc_ring_init()
1228 * and the entire sequence of descriptor to happen without another in pdc_send_data()