Lines Matching +full:pm8916 +full:- +full:pwm
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2022 Linaro Ltd
4 * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
5 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <linux/led-class-multicolor.h>
11 #include <linux/nvmem-consumer.h>
14 #include <linux/pwm.h>
17 #include <linux/soc/qcom/qcom-pbs.h>
43 #define PWM_DTEST_REG(x) (0xe2 + (x) - 1)
87 * struct lpg - LPG device context
90 * @lock: used to synchronize LED and pwm callback requests
91 * @pwm: PWM-chip object, if operating in PWM mode
101 * @triled_src: power-source for the TRILED
104 * @channels: list of PWM channels
113 struct pwm_chip *pwm;
136 * struct lpg_channel - per channel data
138 * @base: base address of the PWM channel
153 * @pwm_resolution_sel: pwm resolution selector
202 * struct lpg_led - logical LED object
220 * struct lpg_channel_data - per channel initialization data
222 * @base: base address for PWM channel registers
232 * struct lpg_data - initialization data
258 if (!lpg->lpg_chan_sdam)
261 lpg->pbs_en_bitmap &= (~lut_mask);
262 if (!lpg->pbs_en_bitmap) {
263 rc = nvmem_device_write(lpg->lpg_chan_sdam, SDAM_REG_PBS_SEQ_EN, 1, &val);
267 if (lpg->lut_sdam) {
269 rc = nvmem_device_write(lpg->lpg_chan_sdam, SDAM_PBS_TRIG_CLR, 1, &val);
283 if (!lpg->lpg_chan_sdam)
286 if (!lpg->pbs_en_bitmap) {
287 rc = nvmem_device_write(lpg->lpg_chan_sdam, SDAM_REG_PBS_SEQ_EN, 1, &val);
291 if (lpg->lut_sdam) {
292 rc = nvmem_device_write(lpg->lpg_chan_sdam, SDAM_PBS_TRIG_SET, 1, &val);
296 rc = qcom_pbs_trigger_event(lpg->pbs_dev, val);
301 lpg->pbs_en_bitmap |= lut_mask;
308 u32 addr = SDAM_LUT_EN_OFFSET + chan->sdam_offset;
310 if (!chan->lpg->lpg_chan_sdam)
313 return nvmem_device_write(chan->lpg->lpg_chan_sdam, addr, 1, &set_trig);
319 if (!lpg->triled_base)
322 return regmap_update_bits(lpg->map, lpg->triled_base + TRI_LED_EN_CTL,
334 if (len > lpg->lut_size) {
335 dev_err(lpg->dev, "Pattern length (%zu) exceeds maximum pattern length (%d)\n",
336 len, lpg->lut_size);
337 return -EINVAL;
340 idx = bitmap_find_next_zero_area(lpg->lut_bitmap, lpg->lut_size, 0, len, 0);
341 if (idx >= lpg->lut_size)
342 return -ENOSPC;
347 if (lpg->lut_sdam) {
349 rc = nvmem_device_write(lpg->lut_sdam, addr, 1, &brightness);
352 rc = nvmem_device_write(lpg->lpg_chan_sdam, addr, 1, &brightness);
359 bitmap_set(lpg->lut_bitmap, idx, len);
362 *hi_idx = idx + len - 1;
374 idx = bitmap_find_next_zero_area(lpg->lut_bitmap, lpg->lut_size,
376 if (idx >= lpg->lut_size)
377 return -ENOMEM;
382 regmap_bulk_write(lpg->map, lpg->lut_base + LPG_LUT_REG(idx + i),
386 bitmap_set(lpg->lut_bitmap, idx, len);
389 *hi_idx = idx + len - 1;
398 len = hi_idx - lo_idx + 1;
402 bitmap_clear(lpg->lut_bitmap, lo_idx, len);
407 if (!lpg->lut_base)
410 return regmap_write(lpg->map, lpg->lut_base + RAMP_CONTROL_REG, mask);
434 * The PWM period is determined by:
437 * period = --------------------------
440 * Resolution = 2^{6 or 9} bits for PWM or
441 * 2^{8, 9, 10, 11, 12, 13, 14, 15} bits for high resolution PWM
445 * This allows for periods between 3uS and 384s for PWM channels and periods between
447 * The PWM framework wants a period of equal or lower length than requested,
451 if (chan->subtype == LPG_SUBTYPE_HI_RES_PWM) {
465 min_period = div64_u64((u64)NSEC_PER_SEC * ((1 << pwm_resolution_arr[0]) - 1),
466 clk_rate_arr[clk_len - 1]);
468 return -EINVAL;
481 * M = log2 -------------------------------------
486 resolution = (1 << pwm_resolution_arr[i]) - 1;
506 error = period - actual;
518 chan->clk_sel = best_clk;
519 chan->pre_div_sel = best_div;
520 chan->pre_div_exp = best_m;
521 chan->period = best_period;
522 chan->pwm_resolution_sel = best_pwm_resolution_sel;
532 if (chan->subtype == LPG_SUBTYPE_HI_RES_PWM) {
533 max = BIT(lpg_pwm_resolution_hi_res[chan->pwm_resolution_sel]) - 1;
534 clk_rate = lpg_clk_rates_hi_res[chan->clk_sel];
536 max = BIT(lpg_pwm_resolution[chan->pwm_resolution_sel]) - 1;
537 clk_rate = lpg_clk_rates[chan->clk_sel];
541 (u64)NSEC_PER_SEC * lpg_pre_divs[chan->pre_div_sel] * (1 << chan->pre_div_exp));
543 chan->pwm_value = min(val, max);
549 struct lpg *lpg = chan->lpg;
551 if (!chan->enabled)
554 val = chan->clk_sel;
557 switch (chan->subtype) {
562 val |= FIELD_PREP(PWM_SIZE_SELECT_MASK, chan->pwm_resolution_sel);
565 val |= FIELD_PREP(PWM_SIZE_HI_RES_MASK, chan->pwm_resolution_sel);
573 regmap_write(lpg->map, chan->base + LPG_SIZE_CLK_REG, val);
575 val = FIELD_PREP(PWM_FREQ_PRE_DIV_MASK, chan->pre_div_sel) |
576 FIELD_PREP(PWM_FREQ_EXP_MASK, chan->pre_div_exp);
577 regmap_write(lpg->map, chan->base + LPG_PREDIV_CLK_REG, val);
584 struct lpg *lpg = chan->lpg;
586 regmap_update_bits(lpg->map, chan->base + PWM_TYPE_CONFIG_REG,
592 struct lpg *lpg = chan->lpg;
594 regmap_update_bits(lpg->map, chan->base + PWM_TYPE_CONFIG_REG,
601 struct lpg *lpg = chan->lpg;
602 u16 val = chan->pwm_value;
604 if (!chan->enabled)
607 regmap_bulk_write(lpg->map, chan->base + PWM_VALUE_REG, &val, sizeof(val));
618 struct nvmem_device *lpg_chan_sdam = chan->lpg->lpg_chan_sdam;
619 unsigned int lo_idx = chan->pattern_lo_idx;
620 unsigned int hi_idx = chan->pattern_hi_idx;
623 struct lpg *lpg = chan->lpg;
625 if (!chan->ramp_enabled || chan->pattern_lo_idx == chan->pattern_hi_idx)
628 hi_pause = DIV_ROUND_UP(chan->ramp_hi_pause_ms, chan->ramp_tick_ms);
629 lo_pause = DIV_ROUND_UP(chan->ramp_lo_pause_ms, chan->ramp_tick_ms);
631 if (!chan->ramp_oneshot)
633 if (chan->ramp_hi_pause_ms && lpg->lut_sdam)
635 if (chan->ramp_lo_pause_ms && lpg->lut_sdam)
638 if (lpg->lut_sdam) {
639 lut_offset = SDAM_LUT_SDAM_LUT_PATTERN_OFFSET - SDAM_START_BASE;
644 nvmem_device_write(lpg_chan_sdam, SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET + chan->sdam_offset, 1, &val);
645 nvmem_device_write(lpg_chan_sdam, SDAM_PATTERN_CONFIG_OFFSET + chan->sdam_offset, 1, &conf);
646 nvmem_device_write(lpg_chan_sdam, SDAM_END_INDEX_OFFSET + chan->sdam_offset, 1, &hi_idx);
647 nvmem_device_write(lpg_chan_sdam, SDAM_START_INDEX_OFFSET + chan->sdam_offset, 1, &lo_idx);
649 val = RAMP_STEP_DURATION(chan->ramp_tick_ms);
652 if (lpg->lut_sdam) {
653 nvmem_device_write(lpg_chan_sdam, SDAM_PAUSE_HI_MULTIPLIER_OFFSET + chan->sdam_offset, 1, &hi_pause);
654 nvmem_device_write(lpg_chan_sdam, SDAM_PAUSE_LO_MULTIPLIER_OFFSET + chan->sdam_offset, 1, &lo_pause);
661 struct lpg *lpg = chan->lpg;
665 unsigned int lo_idx = chan->pattern_lo_idx;
666 unsigned int hi_idx = chan->pattern_hi_idx;
667 u16 step = chan->ramp_tick_ms;
669 if (!chan->ramp_enabled || chan->pattern_lo_idx == chan->pattern_hi_idx)
672 hi_pause = DIV_ROUND_UP(chan->ramp_hi_pause_ms, step);
673 lo_pause = DIV_ROUND_UP(chan->ramp_lo_pause_ms, step);
675 if (!chan->ramp_reverse)
677 if (!chan->ramp_oneshot)
679 if (chan->ramp_ping_pong)
681 if (chan->ramp_hi_pause_ms)
683 if (chan->ramp_lo_pause_ms)
686 regmap_write(lpg->map, chan->base + LPG_PATTERN_CONFIG_REG, conf);
687 regmap_write(lpg->map, chan->base + LPG_HI_IDX_REG, hi_idx);
688 regmap_write(lpg->map, chan->base + LPG_LO_IDX_REG, lo_idx);
690 regmap_bulk_write(lpg->map, chan->base + LPG_RAMP_DURATION_REG, &step, sizeof(step));
691 regmap_write(lpg->map, chan->base + LPG_HI_PAUSE_REG, hi_pause);
692 regmap_write(lpg->map, chan->base + LPG_LO_PAUSE_REG, lo_pause);
703 struct lpg *lpg = chan->lpg;
707 if (chan->enabled)
710 if (chan->pattern_lo_idx != chan->pattern_hi_idx)
715 regmap_write(lpg->map, chan->base + PWM_ENABLE_CONTROL_REG, ctrl);
718 * Due to LPG hardware bug, in the PWM mode, having enabled PWM,
719 * We have to write PWM values one more time.
721 if (chan->enabled)
729 struct lpg *lpg = chan->lpg;
731 regmap_write(lpg->map, chan->base + PWM_SYNC_REG, LPG_SYNC_PWM);
737 struct device_node *np = lpg->dev->of_node;
743 if (count == -EINVAL) {
748 } else if (count != lpg->data->num_channels * 2) {
749 return dev_err_probe(lpg->dev, -EINVAL,
751 lpg->data->num_channels * 2);
754 for (i = 0; i < lpg->data->num_channels; i++) {
755 chan = &lpg->channels[i];
758 &chan->dtest_line);
763 &chan->dtest_value);
771 return dev_err_probe(lpg->dev, ret, "malformed qcom,dtest\n");
776 struct lpg *lpg = chan->lpg;
778 if (!chan->dtest_line)
781 regmap_write(lpg->map, chan->base + PWM_SEC_ACCESS_REG, 0xa5);
782 regmap_write(lpg->map, chan->base + PWM_DTEST_REG(chan->dtest_line),
783 chan->dtest_value);
793 if (chan->lpg->lpg_chan_sdam)
809 struct lpg *lpg = led->lpg;
812 for (i = 0; i < led->num_channels; i++) {
813 chan = led->channels[i];
817 chan->enabled = false;
818 chan->ramp_enabled = false;
819 } else if (chan->pattern_lo_idx != chan->pattern_hi_idx) {
823 chan->enabled = true;
824 chan->ramp_enabled = true;
826 lut_mask |= chan->lut_mask;
827 triled_enabled |= chan->triled_mask;
831 duty = div_u64(brightness * chan->period, cdev->max_brightness);
833 chan->enabled = true;
834 chan->ramp_enabled = false;
836 triled_enabled |= chan->triled_mask;
839 triled_mask |= chan->triled_mask;
861 mutex_lock(&led->lpg->lock);
866 mutex_unlock(&led->lpg->lock);
877 mutex_lock(&led->lpg->lock);
880 lpg_brightness_set(led, cdev, mc->subled_info);
882 mutex_unlock(&led->lpg->lock);
893 struct lpg *lpg = led->lpg;
905 for (i = 0; i < led->num_channels; i++) {
906 chan = led->channels[i];
911 chan->enabled = true;
912 chan->ramp_enabled = false;
914 triled_mask |= chan->triled_mask;
922 chan = led->channels[0];
923 duty = div_u64(chan->pwm_value * chan->period, LPG_RESOLUTION_9BIT);
925 *delay_off = div_u64(chan->period - duty, NSEC_PER_MSEC);
936 mutex_lock(&led->lpg->lock);
940 mutex_unlock(&led->lpg->lock);
952 mutex_lock(&led->lpg->lock);
956 mutex_unlock(&led->lpg->lock);
965 struct lpg *lpg = led->lpg;
977 int ret = -EINVAL;
980 if (repeat != -1 && repeat != 1)
981 return -EINVAL;
984 * The standardized leds-trigger-pattern format defines that the
987 * describes that the way to perform instant transitions a zero-length
992 * a zero-length transition.
995 return -EINVAL;
999 return -ENOMEM;
1039 * SDAM-based devices do not support "ping pong", and only supports
1044 if (lpg->lut_base) {
1047 brightness_b = pattern[len - i - 1].brightness;
1074 if (i != actual_len - 1)
1085 * SDAM-based devices without dedicated LUT SDAM require equal
1088 if (lpg->lut_base || lpg->lut_sdam) {
1090 hi_pause = pattern[actual_len - 1].delta_t;
1092 if (delta_t != pattern[0].delta_t || delta_t != pattern[actual_len - 1].delta_t)
1097 mutex_lock(&lpg->lock);
1099 if (lpg->lut_base)
1107 for (i = 0; i < led->num_channels; i++) {
1108 chan = led->channels[i];
1110 chan->ramp_tick_ms = delta_t;
1111 chan->ramp_ping_pong = ping_pong;
1112 chan->ramp_oneshot = repeat != -1;
1114 chan->ramp_lo_pause_ms = lo_pause;
1115 chan->ramp_hi_pause_ms = hi_pause;
1117 chan->pattern_lo_idx = lo_idx;
1118 chan->pattern_hi_idx = hi_idx;
1122 mutex_unlock(&lpg->lock);
1154 for (i = 0; i < led->num_channels; i++)
1155 triled_mask |= led->channels[i]->triled_mask;
1156 triled_set(led->lpg, triled_mask, 0);
1163 lpg_brightness_set(led, cdev, mc->subled_info);
1171 struct lpg *lpg = led->lpg;
1174 mutex_lock(&lpg->lock);
1176 chan = led->channels[0];
1177 lpg_lut_free(lpg, chan->pattern_lo_idx, chan->pattern_hi_idx);
1179 for (i = 0; i < led->num_channels; i++) {
1180 chan = led->channels[i];
1182 lpg_clear_pbs_trigger(chan->lpg, chan->lut_mask);
1183 chan->pattern_lo_idx = 0;
1184 chan->pattern_hi_idx = 0;
1187 mutex_unlock(&lpg->lock);
1212 static int lpg_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
1215 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];
1217 return chan->in_use ? -EBUSY : 0;
1222 * - Updating both duty and period is not done atomically, so the output signal
1224 * - Changed parameters takes effect immediately.
1225 * - A disabled channel outputs a logical 0.
1227 static int lpg_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
1231 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];
1234 if (state->polarity != PWM_POLARITY_NORMAL)
1235 return -EINVAL;
1237 mutex_lock(&lpg->lock);
1239 if (state->enabled) {
1240 ret = lpg_calc_freq(chan, state->period);
1244 lpg_calc_duty(chan, state->duty_cycle);
1246 chan->enabled = state->enabled;
1250 triled_set(lpg, chan->triled_mask, chan->enabled ? chan->triled_mask : 0);
1253 mutex_unlock(&lpg->lock);
1258 static int lpg_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
1262 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];
1271 ret = regmap_read(lpg->map, chan->base + LPG_SIZE_CLK_REG, &val);
1275 if (chan->subtype == LPG_SUBTYPE_HI_RES_PWM) {
1284 ret = regmap_read(lpg->map, chan->base + LPG_PREDIV_CLK_REG, &val);
1291 ret = regmap_bulk_read(lpg->map, chan->base + PWM_VALUE_REG, &pwm_value, sizeof(pwm_value));
1295 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * ((1 << resolution) - 1) *
1297 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pwm_value * pre_div * (1 << m), refclk);
1299 state->period = 0;
1300 state->duty_cycle = 0;
1303 ret = regmap_read(lpg->map, chan->base + PWM_ENABLE_CONTROL_REG, &val);
1307 state->enabled = FIELD_GET(LPG_ENABLE_CONTROL_OUTPUT, val);
1308 state->polarity = PWM_POLARITY_NORMAL;
1310 if (state->duty_cycle > state->period)
1311 state->duty_cycle = state->period;
1327 lpg->pwm = chip = devm_pwmchip_alloc(lpg->dev, lpg->num_channels, 0);
1331 chip->ops = &lpg_pwm_ops;
1334 ret = devm_pwmchip_add(lpg->dev, chip);
1336 dev_err_probe(lpg->dev, ret, "failed to add PWM chip\n");
1350 if (ret || !reg || reg > lpg->num_channels)
1351 return dev_err_probe(lpg->dev, -EINVAL, "invalid \"reg\" of %pOFn\n", np);
1353 chan = &lpg->channels[reg - 1];
1354 chan->in_use = true;
1357 if (ret < 0 && ret != -EINVAL)
1358 return dev_err_probe(lpg->dev, ret,
1361 chan->color = color;
1381 if (ret < 0 && ret != -EINVAL)
1382 return dev_err_probe(lpg->dev, ret,
1390 led = devm_kzalloc(lpg->dev, struct_size(led, channels, num_channels), GFP_KERNEL);
1392 return -ENOMEM;
1394 led->lpg = lpg;
1395 led->num_channels = num_channels;
1398 info = devm_kcalloc(lpg->dev, num_channels, sizeof(*info), GFP_KERNEL);
1400 return -ENOMEM;
1403 ret = lpg_parse_channel(lpg, child, &led->channels[i]);
1407 info[i].color_index = led->channels[i]->color;
1412 led->mcdev.subled_info = info;
1413 led->mcdev.num_colors = num_channels;
1415 cdev = &led->mcdev.led_cdev;
1416 cdev->brightness_set_blocking = lpg_brightness_mc_set;
1417 cdev->blink_set = lpg_blink_mc_set;
1420 if (lpg->lut_base || lpg->lpg_chan_sdam) {
1421 cdev->pattern_set = lpg_pattern_mc_set;
1422 cdev->pattern_clear = lpg_pattern_mc_clear;
1425 ret = lpg_parse_channel(lpg, np, &led->channels[0]);
1429 cdev = &led->cdev;
1430 cdev->brightness_set_blocking = lpg_brightness_single_set;
1431 cdev->blink_set = lpg_blink_single_set;
1434 if (lpg->lut_base || lpg->lpg_chan_sdam) {
1435 cdev->pattern_set = lpg_pattern_single_set;
1436 cdev->pattern_clear = lpg_pattern_single_clear;
1440 cdev->default_trigger = of_get_property(np, "linux,default-trigger", NULL);
1442 if (lpg->lpg_chan_sdam)
1443 cdev->max_brightness = PPG_MAX_LED_BRIGHTNESS;
1445 cdev->max_brightness = LPG_RESOLUTION_9BIT - 1;
1447 if (!of_property_read_string(np, "default-state", &state) &&
1449 cdev->brightness = cdev->max_brightness;
1451 cdev->brightness = LED_OFF;
1453 cdev->brightness_set_blocking(cdev, cdev->brightness);
1458 ret = devm_led_classdev_multicolor_register_ext(lpg->dev, &led->mcdev, &init_data);
1460 ret = devm_led_classdev_register_ext(lpg->dev, &led->cdev, &init_data);
1462 dev_err_probe(lpg->dev, ret, "unable to register %s\n", cdev->name);
1469 const struct lpg_data *data = lpg->data;
1473 lpg->num_channels = data->num_channels;
1474 lpg->channels = devm_kcalloc(lpg->dev, data->num_channels,
1476 if (!lpg->channels)
1477 return -ENOMEM;
1479 for (i = 0; i < data->num_channels; i++) {
1480 chan = &lpg->channels[i];
1482 chan->lpg = lpg;
1483 chan->base = data->channels[i].base;
1484 chan->triled_mask = data->channels[i].triled_mask;
1485 chan->lut_mask = BIT(i);
1486 chan->sdam_offset = data->channels[i].sdam_offset;
1488 regmap_read(lpg->map, chan->base + LPG_SUBTYPE_REG, &chan->subtype);
1496 struct device_node *np = lpg->dev->of_node;
1500 if (!lpg->data->triled_base)
1503 lpg->triled_base = lpg->data->triled_base;
1504 lpg->triled_has_atc_ctl = lpg->data->triled_has_atc_ctl;
1505 lpg->triled_has_src_sel = lpg->data->triled_has_src_sel;
1507 if (lpg->triled_has_src_sel) {
1508 ret = of_property_read_u32(np, "qcom,power-source", &lpg->triled_src);
1509 if (ret || lpg->triled_src == 2 || lpg->triled_src > 3)
1510 return dev_err_probe(lpg->dev, -EINVAL,
1515 if (lpg->triled_has_atc_ctl)
1516 regmap_write(lpg->map, lpg->triled_base + TRI_LED_ATC_CTL, 0);
1519 if (lpg->triled_has_src_sel)
1520 regmap_write(lpg->map, lpg->triled_base + TRI_LED_SRC_SEL, lpg->triled_src);
1523 regmap_write(lpg->map, lpg->triled_base + TRI_LED_EN_CTL, 0);
1530 const struct lpg_data *data = lpg->data;
1532 if (!data->lut_size)
1535 lpg->lut_size = data->lut_size;
1536 if (data->lut_base)
1537 lpg->lut_base = data->lut_base;
1539 lpg->lut_bitmap = devm_bitmap_zalloc(lpg->dev, lpg->lut_size, GFP_KERNEL);
1540 if (!lpg->lut_bitmap)
1541 return -ENOMEM;
1551 sdam_count = of_property_count_strings(lpg->dev->of_node, "nvmem-names");
1555 return -EINVAL;
1558 lpg->lpg_chan_sdam = devm_nvmem_device_get(lpg->dev, "lpg_chan_sdam");
1559 if (IS_ERR(lpg->lpg_chan_sdam))
1560 return dev_err_probe(lpg->dev, PTR_ERR(lpg->lpg_chan_sdam),
1565 lpg->pbs_dev = get_pbs_client_device(lpg->dev);
1566 if (IS_ERR(lpg->pbs_dev))
1567 return dev_err_probe(lpg->dev, PTR_ERR(lpg->pbs_dev),
1571 lpg->lut_sdam = devm_nvmem_device_get(lpg->dev, "lut_sdam");
1572 if (IS_ERR(lpg->lut_sdam))
1573 return dev_err_probe(lpg->dev, PTR_ERR(lpg->lut_sdam),
1577 for (i = 0; i < lpg->num_channels; i++) {
1578 struct lpg_channel *chan = &lpg->channels[i];
1580 if (chan->sdam_offset) {
1581 rc = nvmem_device_write(lpg->lpg_chan_sdam,
1582 SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET + chan->sdam_offset, 1, &val);
1590 rc = lpg_clear_pbs_trigger(chan->lpg, chan->lut_mask);
1605 lpg = devm_kzalloc(&pdev->dev, sizeof(*lpg), GFP_KERNEL);
1607 return -ENOMEM;
1609 lpg->data = of_device_get_match_data(&pdev->dev);
1610 if (!lpg->data)
1611 return -EINVAL;
1613 lpg->dev = &pdev->dev;
1614 mutex_init(&lpg->lock);
1616 lpg->map = dev_get_regmap(pdev->dev.parent, NULL);
1617 if (!lpg->map)
1618 return dev_err_probe(&pdev->dev, -ENXIO, "parent regmap unavailable\n");
1640 for_each_available_child_of_node_scoped(pdev->dev.of_node, np) {
1646 for (i = 0; i < lpg->num_channels; i++)
1647 lpg_apply_dtest(&lpg->channels[i]);
1822 { .compatible = "qcom,pm660l-lpg", .data = &pm660l_lpg_data },
1823 { .compatible = "qcom,pm8150b-lpg", .data = &pm8150b_lpg_data },
1824 { .compatible = "qcom,pm8150l-lpg", .data = &pm8150l_lpg_data },
1825 { .compatible = "qcom,pm8350c-pwm", .data = &pm8350c_pwm_data },
1826 { .compatible = "qcom,pm8916-pwm", .data = &pm8916_pwm_data },
1827 { .compatible = "qcom,pm8941-lpg", .data = &pm8941_lpg_data },
1828 { .compatible = "qcom,pm8994-lpg", .data = &pm8994_lpg_data },
1829 { .compatible = "qcom,pmi632-lpg", .data = &pmi632_lpg_data },
1830 { .compatible = "qcom,pmi8950-pwm", .data = &pmi8950_pwm_data },
1831 { .compatible = "qcom,pmi8994-lpg", .data = &pmi8994_lpg_data },
1832 { .compatible = "qcom,pmi8998-lpg", .data = &pmi8998_lpg_data },
1833 { .compatible = "qcom,pmc8180c-lpg", .data = &pm8150l_lpg_data },
1834 { .compatible = "qcom,pmk8550-pwm", .data = &pmk8550_pwm_data },
1842 .name = "qcom-spmi-lpg",