Lines Matching +full:0 +full:xd000
19 #define LPG_SUBTYPE_REG 0x05
20 #define LPG_SUBTYPE_LPG 0x2
21 #define LPG_SUBTYPE_PWM 0xb
22 #define LPG_SUBTYPE_HI_RES_PWM 0xc
23 #define LPG_SUBTYPE_LPG_LITE 0x11
24 #define LPG_PATTERN_CONFIG_REG 0x40
25 #define LPG_SIZE_CLK_REG 0x41
26 #define PWM_CLK_SELECT_MASK GENMASK(1, 0)
27 #define PWM_CLK_SELECT_HI_RES_MASK GENMASK(2, 0)
29 #define LPG_PREDIV_CLK_REG 0x42
31 #define PWM_FREQ_EXP_MASK GENMASK(2, 0)
32 #define PWM_TYPE_CONFIG_REG 0x43
33 #define PWM_VALUE_REG 0x44
34 #define PWM_ENABLE_CONTROL_REG 0x46
35 #define PWM_SYNC_REG 0x47
36 #define LPG_RAMP_DURATION_REG 0x50
37 #define LPG_HI_PAUSE_REG 0x52
38 #define LPG_LO_PAUSE_REG 0x54
39 #define LPG_HI_IDX_REG 0x56
40 #define LPG_LO_IDX_REG 0x57
41 #define PWM_SEC_ACCESS_REG 0xd0
42 #define PWM_DTEST_REG(x) (0xe2 + (x) - 1)
44 #define SDAM_REG_PBS_SEQ_EN 0x42
45 #define SDAM_PBS_TRIG_SET 0xe5
46 #define SDAM_PBS_TRIG_CLR 0xe6
48 #define TRI_LED_SRC_SEL 0x45
49 #define TRI_LED_EN_CTL 0x46
50 #define TRI_LED_ATC_CTL 0x47
52 #define LPG_LUT_REG(x) (0x40 + (x) * 2)
53 #define RAMP_CONTROL_REG 0xc8
63 #define RAMP_STEP_DURATION(x) (((x) * 1000 / DEFAULT_TICK_DURATION_US) & 0xff)
67 #define SDAM_START_BASE 0x40
68 #define SDAM_REG_RAMP_STEP_DURATION 0x47
70 #define SDAM_LUT_SDAM_LUT_PATTERN_OFFSET 0x45
71 #define SDAM_LPG_SDAM_LUT_PATTERN_OFFSET 0x80
74 #define SDAM_LUT_EN_OFFSET 0x0
75 #define SDAM_PATTERN_CONFIG_OFFSET 0x1
76 #define SDAM_END_INDEX_OFFSET 0x3
77 #define SDAM_START_INDEX_OFFSET 0x4
78 #define SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET 0x6
79 #define SDAM_PAUSE_HI_MULTIPLIER_OFFSET 0x8
80 #define SDAM_PAUSE_LO_MULTIPLIER_OFFSET 0x9
144 * @dtest_line: DTEST line for output, or 0 if disabled
250 #define PBS_SW_TRIG_BIT BIT(0)
254 u8 val = 0; in lpg_clear_pbs_trigger()
258 return 0; in lpg_clear_pbs_trigger()
263 if (rc < 0) in lpg_clear_pbs_trigger()
269 if (rc < 0) in lpg_clear_pbs_trigger()
274 return 0; in lpg_clear_pbs_trigger()
283 return 0; in lpg_set_pbs_trigger()
287 if (rc < 0) in lpg_set_pbs_trigger()
292 if (rc < 0) in lpg_set_pbs_trigger()
296 if (rc < 0) in lpg_set_pbs_trigger()
302 return 0; in lpg_set_pbs_trigger()
310 return 0; in lpg_sdam_configure_triggers()
319 return 0; in triled_set()
339 idx = bitmap_find_next_zero_area(lpg->lut_bitmap, lpg->lut_size, 0, len, 0); in lpg_lut_store_sdam()
343 for (i = 0; i < len; i++) { in lpg_lut_store_sdam()
354 if (rc < 0) in lpg_lut_store_sdam()
363 return 0; in lpg_lut_store_sdam()
374 0, len, 0); in lpg_lut_store()
378 for (i = 0; i < len; i++) { in lpg_lut_store()
390 return 0; in lpg_lut_store()
407 return 0; in lpg_lut_sync()
412 static const unsigned int lpg_clk_rates[] = {0, 1024, 32768, 19200000};
413 static const unsigned int lpg_clk_rates_hi_res[] = {0, 1024, 32768, 19200000, 76800000};
420 unsigned int i, pwm_resolution_count, best_pwm_resolution_sel = 0; in lpg_calc_freq()
422 unsigned int clk_sel, clk_len, best_clk = 0; in lpg_calc_freq()
423 unsigned int div, best_div = 0; in lpg_calc_freq()
424 unsigned int m, best_m = 0; in lpg_calc_freq()
429 u64 best_period = 0; in lpg_calc_freq()
442 * M = [0..7]. in lpg_calc_freq()
464 min_period = div64_u64((u64)NSEC_PER_SEC * (1 << pwm_resolution_arr[0]), in lpg_calc_freq()
484 for (i = 0; i < pwm_resolution_count; i++) { in lpg_calc_freq()
489 for (div = 0; div < ARRAY_SIZE(lpg_pre_divs); div++) { in lpg_calc_freq()
522 return 0; in lpg_calc_freq()
586 LPG_ENABLE_GLITCH_REMOVAL, 0); in lpg_enable_glitch()
613 #define LPG_PATTERN_CONFIG_PAUSE_LO BIT(0)
620 u8 val = 0, conf = 0, lut_offset = 0; in lpg_sdam_apply_lut_control()
663 unsigned int conf = 0; in lpg_apply_lut_control()
724 #define LPG_SYNC_PWM BIT(0)
743 return 0; in lpg_parse_dtest()
744 } else if (count < 0) { in lpg_parse_dtest()
753 for (i = 0; i < lpg->data->num_channels; i++) { in lpg_parse_dtest()
767 return 0; in lpg_parse_dtest()
780 regmap_write(lpg->map, chan->base + PWM_SEC_ACCESS_REG, 0xa5); in lpg_apply_dtest()
804 unsigned int triled_enabled = 0; in lpg_brightness_set()
805 unsigned int triled_mask = 0; in lpg_brightness_set()
806 unsigned int lut_mask = 0; in lpg_brightness_set()
811 for (i = 0; i < led->num_channels; i++) { in lpg_brightness_set()
867 return 0; in lpg_brightness_single_set()
883 return 0; in lpg_brightness_mc_set()
891 unsigned int triled_mask = 0; in lpg_blink_set()
904 for (i = 0; i < led->num_channels; i++) { in lpg_blink_set()
921 chan = led->channels[0]; in lpg_blink_set()
926 return 0; in lpg_blink_set()
968 unsigned int hi_pause = 0; in lpg_pattern_set()
969 unsigned int lo_pause = 0; in lpg_pattern_set()
1000 for (i = 0; i < len; i += 2) { in lpg_pattern_set()
1003 if (led_pattern[i + 1].delta_t != 0) in lpg_pattern_set()
1044 for (i = 0; i < len / 2; i++) { in lpg_pattern_set()
1088 lo_pause = pattern[0].delta_t; in lpg_pattern_set()
1091 if (delta_t != pattern[0].delta_t || delta_t != pattern[actual_len - 1].delta_t) in lpg_pattern_set()
1103 if (ret < 0) in lpg_pattern_set()
1106 for (i = 0; i < led->num_channels; i++) { in lpg_pattern_set()
1136 if (ret < 0) in lpg_pattern_single_set()
1141 return 0; in lpg_pattern_single_set()
1150 unsigned int triled_mask = 0; in lpg_pattern_mc_set()
1153 for (i = 0; i < led->num_channels; i++) in lpg_pattern_mc_set()
1155 triled_set(led->lpg, triled_mask, 0); in lpg_pattern_mc_set()
1158 if (ret < 0) in lpg_pattern_mc_set()
1164 return 0; in lpg_pattern_mc_set()
1175 chan = led->channels[0]; in lpg_pattern_clear()
1178 for (i = 0; i < led->num_channels; i++) { in lpg_pattern_clear()
1180 lpg_sdam_configure_triggers(chan, 0); in lpg_pattern_clear()
1182 chan->pattern_lo_idx = 0; in lpg_pattern_clear()
1183 chan->pattern_hi_idx = 0; in lpg_pattern_clear()
1188 return 0; in lpg_pattern_clear()
1216 return chan->in_use ? -EBUSY : 0; in lpg_pwm_request()
1224 * - A disabled channel outputs a logical 0.
1231 int ret = 0; in lpg_pwm_apply()
1240 if (ret < 0) in lpg_pwm_apply()
1249 triled_set(lpg, chan->triled_mask, chan->enabled ? chan->triled_mask : 0); in lpg_pwm_apply()
1298 state->period = 0; in lpg_pwm_get_state()
1299 state->duty_cycle = 0; in lpg_pwm_get_state()
1312 return 0; in lpg_pwm_get_state()
1326 lpg->pwm = chip = devm_pwmchip_alloc(lpg->dev, lpg->num_channels, 0); in lpg_add_pwm()
1356 if (ret < 0 && ret != -EINVAL) in lpg_parse_channel()
1364 return 0; in lpg_parse_channel()
1375 u32 color = 0; in lpg_add_led()
1380 if (ret < 0 && ret != -EINVAL) in lpg_add_led()
1400 i = 0; in lpg_add_led()
1403 if (ret < 0) in lpg_add_led()
1407 info[i].intensity = 0; in lpg_add_led()
1424 ret = lpg_parse_channel(lpg, np, &led->channels[0]); in lpg_add_led()
1425 if (ret < 0) in lpg_add_led()
1478 for (i = 0; i < data->num_channels; i++) { in lpg_init_channels()
1490 return 0; in lpg_init_channels()
1500 return 0; in lpg_init_triled()
1515 regmap_write(lpg->map, lpg->triled_base + TRI_LED_ATC_CTL, 0); in lpg_init_triled()
1522 regmap_write(lpg->map, lpg->triled_base + TRI_LED_EN_CTL, 0); in lpg_init_triled()
1524 return 0; in lpg_init_triled()
1532 return 0; in lpg_init_lut()
1542 return 0; in lpg_init_lut()
1548 u8 val = 0; in lpg_init_sdam()
1551 if (sdam_count <= 0) in lpg_init_sdam()
1552 return 0; in lpg_init_sdam()
1576 for (i = 0; i < lpg->num_channels; i++) { in lpg_init_sdam()
1582 if (rc < 0) in lpg_init_sdam()
1585 rc = lpg_sdam_configure_triggers(chan, 0); in lpg_init_sdam()
1586 if (rc < 0) in lpg_init_sdam()
1590 if (rc < 0) in lpg_init_sdam()
1595 return 0; in lpg_init_sdam()
1620 if (ret < 0) in lpg_probe()
1624 if (ret < 0) in lpg_probe()
1628 if (ret < 0) in lpg_probe()
1632 if (ret < 0) in lpg_probe()
1636 if (ret < 0) in lpg_probe()
1645 for (i = 0; i < lpg->num_channels; i++) in lpg_probe()
1652 .lut_base = 0xb000,
1655 .triled_base = 0xd000,
1661 { .base = 0xb100, .triled_mask = BIT(5) },
1662 { .base = 0xb200, .triled_mask = BIT(6) },
1663 { .base = 0xb300, .triled_mask = BIT(7) },
1664 { .base = 0xb400 },
1671 { .base = 0xbc00 },
1676 .lut_base = 0xb000,
1679 .triled_base = 0xd000,
1685 { .base = 0xb100 },
1686 { .base = 0xb200 },
1687 { .base = 0xb300 },
1688 { .base = 0xb400 },
1689 { .base = 0xb500, .triled_mask = BIT(5) },
1690 { .base = 0xb600, .triled_mask = BIT(6) },
1691 { .base = 0xb700, .triled_mask = BIT(7) },
1692 { .base = 0xb800 },
1699 { .base = 0xb000 },
1704 .lut_base = 0xb000,
1709 { .base = 0xb100 },
1710 { .base = 0xb200 },
1711 { .base = 0xb300 },
1712 { .base = 0xb400 },
1713 { .base = 0xb500 },
1714 { .base = 0xb600 },
1720 .triled_base = 0xd000,
1726 { .base = 0xb300, .triled_mask = BIT(7), .sdam_offset = 0x48 },
1727 { .base = 0xb400, .triled_mask = BIT(6), .sdam_offset = 0x56 },
1728 { .base = 0xb500, .triled_mask = BIT(5), .sdam_offset = 0x64 },
1729 { .base = 0xb600 },
1730 { .base = 0xb700 },
1735 .lut_base = 0xb000,
1738 .triled_base = 0xd000,
1744 { .base = 0xb100, .triled_mask = BIT(5) },
1745 { .base = 0xb200, .triled_mask = BIT(6) },
1746 { .base = 0xb300, .triled_mask = BIT(7) },
1747 { .base = 0xb400 },
1752 .lut_base = 0xb000,
1755 .triled_base = 0xd000,
1759 { .base = 0xb100 },
1760 { .base = 0xb200 },
1761 { .base = 0xb300, .triled_mask = BIT(5) },
1762 { .base = 0xb400, .triled_mask = BIT(6) },
1763 { .base = 0xb500, .triled_mask = BIT(7) },
1764 { .base = 0xb600 },
1769 .lut_base = 0xb000,
1772 .triled_base = 0xd000,
1776 { .base = 0xb100, .triled_mask = BIT(7) },
1777 { .base = 0xb200, .triled_mask = BIT(6) },
1782 .lut_base = 0xb000,
1785 .triled_base = 0xd000,
1789 { .base = 0xb100, .triled_mask = BIT(7) },
1790 { .base = 0xb200, .triled_mask = BIT(6) },
1791 { .base = 0xb300, .triled_mask = BIT(5) },
1792 { .base = 0xbc00 },
1793 { .base = 0xbd00 },
1799 .triled_base = 0xef00,
1805 { .base = 0xe800, .triled_mask = BIT(7), .sdam_offset = 0x48 },
1806 { .base = 0xe900, .triled_mask = BIT(6), .sdam_offset = 0x56 },
1807 { .base = 0xea00, .triled_mask = BIT(5), .sdam_offset = 0x64 },
1808 { .base = 0xeb00 },
1815 { .base = 0xe800 },
1816 { .base = 0xe900 },