2  * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
3  * Copyright (C) 2012-2013 Xilinx, Inc.
4  * Copyright (C) 2007-2009 PetaLogix
32 #define MER_ME (1<<0)
33 #define MER_HIE (1<<1)
35 #define SPURIOUS_IRQ	(-1U)
51 		iowrite32be(data, irqc->base + reg);  in xintc_write()
53 		iowrite32(data, irqc->base + reg);  in xintc_write()
59 		return ioread32be(irqc->base + reg);  in xintc_read()
61 		return ioread32(irqc->base + reg);  in xintc_read()
67 	unsigned long mask = BIT(d->hwirq);  in intc_enable_or_unmask()
69 	pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);  in intc_enable_or_unmask()
85 	pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);  in intc_disable_or_mask()
86 	xintc_write(irqc, CIE, BIT(d->hwirq));  in intc_disable_or_mask()
93 	pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);  in intc_ack()
94 	xintc_write(irqc, IAR, BIT(d->hwirq));  in intc_ack()
100 	unsigned long mask = BIT(d->hwirq);  in intc_mask_ack()
102 	pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);  in intc_mask_ack()
108 	.name = "Xilinx INTC",
117 	struct xintc_irq_chip *irqc = d->host_data;  in xintc_map()
119 	if (irqc->intr_mask & BIT(hw)) {  in xintc_map()
142 	irqc = irq_data_get_irq_handler_data(&desc->irq_data);  in xil_intc_irq_handler()
147 		if (hwirq == -1U)  in xil_intc_irq_handler()
150 		generic_handle_domain_irq(irqc->root_domain, hwirq);  in xil_intc_irq_handler()
164 		generic_handle_domain_irq(primary_intc->root_domain, hwirq);  in xil_intc_handle_irq()
168 static int __init xilinx_intc_of_init(struct device_node *intc,  in xilinx_intc_of_init()  argument
176 		return -ENOMEM;  in xilinx_intc_of_init()
177 	irqc->base = of_iomap(intc, 0);  in xilinx_intc_of_init()
178 	BUG_ON(!irqc->base);  in xilinx_intc_of_init()
180 	ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq);  in xilinx_intc_of_init()
182 		pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");  in xilinx_intc_of_init()
186 	ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);  in xilinx_intc_of_init()
188 		pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n");  in xilinx_intc_of_init()
189 		irqc->intr_mask = 0;  in xilinx_intc_of_init()
192 	if ((u64)irqc->intr_mask >> irqc->nr_irq)  in xilinx_intc_of_init()
193 		pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");  in xilinx_intc_of_init()
195 	pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n",  in xilinx_intc_of_init()
196 		intc, irqc->nr_irq, irqc->intr_mask);  in xilinx_intc_of_init()
215 	irqc->root_domain = irq_domain_create_linear(of_fwnode_handle(intc), irqc->nr_irq,  in xilinx_intc_of_init()
217 	if (!irqc->root_domain) {  in xilinx_intc_of_init()
218 		pr_err("irq-xilinx: Unable to create IRQ domain\n");  in xilinx_intc_of_init()
219 		ret = -EINVAL;  in xilinx_intc_of_init()
224 		irq = irq_of_parse_and_map(intc, 0);  in xilinx_intc_of_init()
230 			pr_err("irq-xilinx: interrupts property not in DT\n");  in xilinx_intc_of_init()
231 			ret = -EINVAL;  in xilinx_intc_of_init()
236 		irq_set_default_domain(primary_intc->root_domain);  in xilinx_intc_of_init()
243 	iounmap(irqc->base);  in xilinx_intc_of_init()
249 IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
250 IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);