62 	{ .compatible = "nvidia,tegra210-ictlr", .data = &tegra210_ictlr_soc },
63 	{ .compatible = "nvidia,tegra30-ictlr", .data = &tegra30_ictlr_soc },
64 	{ .compatible = "nvidia,tegra20-ictlr", .data = &tegra20_ictlr_soc },
142 		void __iomem *ictlr = lic->base[i];  in tegra_ictlr_suspend()  local
145 		lic->cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);  in tegra_ictlr_suspend()
146 		lic->cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);  in tegra_ictlr_suspend()
147 		lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);  in tegra_ictlr_suspend()
148 		lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);  in tegra_ictlr_suspend()
151 		writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);  in tegra_ictlr_suspend()
154 		writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);  in tegra_ictlr_suspend()
156 		/* Enable the wakeup sources of ictlr */  in tegra_ictlr_suspend()
157 		writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);  in tegra_ictlr_suspend()
171 		void __iomem *ictlr = lic->base[i];  in tegra_ictlr_resume()  local
174 			       ictlr + ICTLR_CPU_IEP_CLASS);  in tegra_ictlr_resume()
175 		writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);  in tegra_ictlr_resume()
177 			       ictlr + ICTLR_CPU_IER_SET);  in tegra_ictlr_resume()
179 			       ictlr + ICTLR_COP_IEP_CLASS);  in tegra_ictlr_resume()
180 		writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);  in tegra_ictlr_resume()
182 			       ictlr + ICTLR_COP_IER_SET);  in tegra_ictlr_resume()
256 		int ictlr = (hwirq + i) / 32;  in tegra_ictlr_domain_alloc()  local
260 					      (void __force *)info->base[ictlr]);  in tegra_ictlr_domain_alloc()
356 IRQCHIP_DECLARE(tegra20_ictlr, "nvidia,tegra20-ictlr", tegra_ictlr_init);
357 IRQCHIP_DECLARE(tegra30_ictlr, "nvidia,tegra30-ictlr", tegra_ictlr_init);
358 IRQCHIP_DECLARE(tegra210_ictlr, "nvidia,tegra210-ictlr", tegra_ictlr_init);