1 // SPDX-License-Identifier: GPL-2.0-only
44 	uint32_t mod, pol, im = data->mask;  in tb10x_irq_set_type()
46 	guard(raw_spinlock)(&gc->lock);  in tb10x_irq_set_type()
68 		pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",	__func__, data->irq);  in tb10x_irq_set_type()
69 		return -EBADR;  in tb10x_irq_set_type()
89 static int __init of_tb10x_init_irq(struct device_node *ictl,  in of_tb10x_init_irq()  argument
92 	int i, ret, nrirqs = of_irq_count(ictl);  in of_tb10x_init_irq()
98 	if (of_address_to_resource(ictl, 0, &mem)) {  in of_tb10x_init_irq()
100 			ictl);  in of_tb10x_init_irq()
101 		return -EINVAL;  in of_tb10x_init_irq()
105 		ictl->full_name)) {  in of_tb10x_init_irq()
106 		pr_err("%pOFn: Request mem region failed.\n", ictl);  in of_tb10x_init_irq()
107 		return -EBUSY;  in of_tb10x_init_irq()
112 		ret = -EBUSY;  in of_tb10x_init_irq()
113 		pr_err("%pOFn: ioremap failed.\n", ictl);  in of_tb10x_init_irq()
117 	domain = irq_domain_create_linear(of_fwnode_handle(ictl), AB_IRQCTL_MAXIRQ,  in of_tb10x_init_irq()
120 		ret = -ENOMEM;  in of_tb10x_init_irq()
122 			ictl);  in of_tb10x_init_irq()
127 				2, ictl->name, handle_level_irq,  in of_tb10x_init_irq()
132 			ictl);  in of_tb10x_init_irq()
136 	gc = domain->gc->gc[0];  in of_tb10x_init_irq()
137 	gc->reg_base                         = reg_base;  in of_tb10x_init_irq()
139 	gc->chip_types[0].type               = IRQ_TYPE_LEVEL_MASK;  in of_tb10x_init_irq()
140 	gc->chip_types[0].chip.irq_mask      = irq_gc_mask_clr_bit;  in of_tb10x_init_irq()
141 	gc->chip_types[0].chip.irq_unmask    = irq_gc_mask_set_bit;  in of_tb10x_init_irq()
142 	gc->chip_types[0].chip.irq_set_type  = tb10x_irq_set_type;  in of_tb10x_init_irq()
143 	gc->chip_types[0].regs.mask          = AB_IRQCTL_INT_ENABLE;  in of_tb10x_init_irq()
145 	gc->chip_types[1].type               = IRQ_TYPE_EDGE_BOTH;  in of_tb10x_init_irq()
146 	gc->chip_types[1].chip.irq_ack       = irq_gc_ack_set_bit;  in of_tb10x_init_irq()
147 	gc->chip_types[1].chip.irq_mask      = irq_gc_mask_clr_bit;  in of_tb10x_init_irq()
148 	gc->chip_types[1].chip.irq_unmask    = irq_gc_mask_set_bit;  in of_tb10x_init_irq()
149 	gc->chip_types[1].chip.irq_set_type  = tb10x_irq_set_type;  in of_tb10x_init_irq()
150 	gc->chip_types[1].regs.ack           = AB_IRQCTL_INT_STATUS;  in of_tb10x_init_irq()
151 	gc->chip_types[1].regs.mask          = AB_IRQCTL_INT_ENABLE;  in of_tb10x_init_irq()
152 	gc->chip_types[1].handler            = handle_edge_irq;  in of_tb10x_init_irq()
155 		unsigned int irq = irq_of_parse_and_map(ictl, i);  in of_tb10x_init_irq()
176 IRQCHIP_DECLARE(tb10x_intc, "abilis,tb10x-ictl", of_tb10x_init_irq);