Lines Matching refs:gc

85 static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off, u32 val)
87 	irq_reg_writel(gc, val, off);
90 static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off)
92 	return irq_reg_readl(gc, off);
107 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
108 	struct irq_chip_type *ct = gc->chip_types;
114 	irq_gc_lock(gc);
131 		irq_gc_unlock(gc);
140 	for (i = 0; i < gc->num_ct; i++, ct++)
144 	src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off);
147 	sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);
149 	irq_gc_unlock(gc);
158 	struct irq_chip_generic *gc;
183 	gc = irq_get_domain_generic_chip(domain, 0);
184 	gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node));
185 	if (IS_ERR(gc->reg_base)) {
187 		ret = PTR_ERR(gc->reg_base);
191 	gc->chip_types[0].type			= IRQ_TYPE_LEVEL_MASK;
192 	gc->chip_types[0].chip.irq_mask		= irq_gc_mask_clr_bit;
193 	gc->chip_types[0].chip.irq_unmask	= irq_gc_mask_set_bit;
194 	gc->chip_types[0].chip.irq_eoi		= irq_gc_ack_set_bit;
195 	gc->chip_types[0].chip.irq_set_type	= sunxi_sc_nmi_set_type;
196 	gc->chip_types[0].chip.flags		= IRQCHIP_EOI_THREADED |
199 	gc->chip_types[0].regs.ack		= data->reg_offs.pend;
200 	gc->chip_types[0].regs.mask		= data->reg_offs.enable;
201 	gc->chip_types[0].regs.type		= data->reg_offs.ctrl;
203 	gc->chip_types[1].type			= IRQ_TYPE_EDGE_BOTH;
204 	gc->chip_types[1].chip.irq_ack		= irq_gc_ack_set_bit;
205 	gc->chip_types[1].chip.irq_mask		= irq_gc_mask_clr_bit;
206 	gc->chip_types[1].chip.irq_unmask	= irq_gc_mask_set_bit;
207 	gc->chip_types[1].chip.irq_set_type	= sunxi_sc_nmi_set_type;
208 	gc->chip_types[1].regs.ack		= data->reg_offs.pend;
209 	gc->chip_types[1].regs.mask		= data->reg_offs.enable;
210 	gc->chip_types[1].regs.type		= data->reg_offs.ctrl;
211 	gc->chip_types[1].handler		= handle_edge_irq;
214 	sunxi_sc_nmi_write(gc, data->reg_offs.enable, data->enable_val);
217 	sunxi_sc_nmi_write(gc, data->reg_offs.pend, SUNXI_NMI_IRQ_BIT);