Lines Matching +full:sun7i +full:- +full:a20 +full:- +full:sc +full:- +full:nmi

2  * Allwinner A20/A31 SoCs NMI IRQ chip driver.
11 #define DRV_NAME	"sunxi-nmi"
30  * For deprecated sun6i-a31-sc-nmi compatible.
108 	struct irq_chip_type *ct = gc->chip_types;  in sunxi_sc_nmi_set_type()
110 	u32 ctrl_off = ct->regs.type;  in sunxi_sc_nmi_set_type()
114 	guard(raw_spinlock)(&gc->lock);  in sunxi_sc_nmi_set_type()
131 		pr_err("Cannot assign multiple trigger modes to IRQ %d.\n", data->irq);  in sunxi_sc_nmi_set_type()
132 		return -EBADR;  in sunxi_sc_nmi_set_type()
138 	for (i = 0; i < gc->num_ct; i++, ct++)  in sunxi_sc_nmi_set_type()
139 		if (ct->type & flow_type)  in sunxi_sc_nmi_set_type()
140 			ctrl_off = ct->regs.type;  in sunxi_sc_nmi_set_type()
160 		return -ENOMEM;  in sunxi_sc_nmi_irq_init()
174 		ret = -EINVAL;  in sunxi_sc_nmi_irq_init()
179 	gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node));  in sunxi_sc_nmi_irq_init()
180 	if (IS_ERR(gc->reg_base)) {  in sunxi_sc_nmi_irq_init()
182 		ret = PTR_ERR(gc->reg_base);  in sunxi_sc_nmi_irq_init()
186 	gc->chip_types[0].type			= IRQ_TYPE_LEVEL_MASK;  in sunxi_sc_nmi_irq_init()
187 	gc->chip_types[0].chip.irq_mask		= irq_gc_mask_clr_bit;  in sunxi_sc_nmi_irq_init()
188 	gc->chip_types[0].chip.irq_unmask	= irq_gc_mask_set_bit;  in sunxi_sc_nmi_irq_init()
189 	gc->chip_types[0].chip.irq_eoi		= irq_gc_ack_set_bit;  in sunxi_sc_nmi_irq_init()
190 	gc->chip_types[0].chip.irq_set_type	= sunxi_sc_nmi_set_type;  in sunxi_sc_nmi_irq_init()
191 	gc->chip_types[0].chip.flags		= IRQCHIP_EOI_THREADED |  in sunxi_sc_nmi_irq_init()
194 	gc->chip_types[0].regs.ack		= data->reg_offs.pend;  in sunxi_sc_nmi_irq_init()
195 	gc->chip_types[0].regs.mask		= data->reg_offs.enable;  in sunxi_sc_nmi_irq_init()
196 	gc->chip_types[0].regs.type		= data->reg_offs.ctrl;  in sunxi_sc_nmi_irq_init()
198 	gc->chip_types[1].type			= IRQ_TYPE_EDGE_BOTH;  in sunxi_sc_nmi_irq_init()
199 	gc->chip_types[1].chip.irq_ack		= irq_gc_ack_set_bit;  in sunxi_sc_nmi_irq_init()
200 	gc->chip_types[1].chip.irq_mask		= irq_gc_mask_clr_bit;  in sunxi_sc_nmi_irq_init()
201 	gc->chip_types[1].chip.irq_unmask	= irq_gc_mask_set_bit;  in sunxi_sc_nmi_irq_init()
202 	gc->chip_types[1].chip.irq_set_type	= sunxi_sc_nmi_set_type;  in sunxi_sc_nmi_irq_init()
203 	gc->chip_types[1].regs.ack		= data->reg_offs.pend;  in sunxi_sc_nmi_irq_init()
204 	gc->chip_types[1].regs.mask		= data->reg_offs.enable;  in sunxi_sc_nmi_irq_init()
205 	gc->chip_types[1].regs.type		= data->reg_offs.ctrl;  in sunxi_sc_nmi_irq_init()
206 	gc->chip_types[1].handler		= handle_edge_irq;  in sunxi_sc_nmi_irq_init()
209 	sunxi_sc_nmi_write(gc, data->reg_offs.enable, data->enable_val);  in sunxi_sc_nmi_irq_init()
211 	/* Clear any pending NMI interrupts */  in sunxi_sc_nmi_irq_init()
212 	sunxi_sc_nmi_write(gc, data->reg_offs.pend, SUNXI_NMI_IRQ_BIT);  in sunxi_sc_nmi_irq_init()
229 IRQCHIP_DECLARE(sun6i_sc_nmi, "allwinner,sun6i-a31-sc-nmi", sun6i_sc_nmi_irq_init);
236 IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);
243 IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init);
250 IRQCHIP_DECLARE(sun55i_nmi, "allwinner,sun55i-a523-nmi", sun55i_nmi_irq_init);