1 // SPDX-License-Identifier: GPL-2.0
4  * Copyright (C) STMicroelectronics 2017-2024
5  * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
110 	struct stm32_exti_chip_data *chip_data = gc->private;  in stm32_exti_pending()
111 	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;  in stm32_exti_pending()
113 	return irq_reg_readl(gc, stm32_bank->rpr_ofst);  in stm32_exti_pending()
120 	unsigned int nbanks = domain->gc->num_chips;  in stm32_irq_handler()
142 	u32 mask = BIT(d->hwirq % IRQS_PER_BANK);  in stm32_exti_set_type()
158 		return -EINVAL;  in stm32_exti_set_type()
167 	struct stm32_exti_chip_data *chip_data = gc->private;  in stm32_irq_set_type()
168 	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;  in stm32_irq_set_type()
174 	rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);  in stm32_irq_set_type()
175 	ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);  in stm32_irq_set_type()
181 	irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);  in stm32_irq_set_type()
182 	irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);  in stm32_irq_set_type()
193 	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;  in stm32_chip_suspend()
194 	void __iomem *base = chip_data->host_data->base;  in stm32_chip_suspend()
197 	chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);  in stm32_chip_suspend()
198 	chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);  in stm32_chip_suspend()
200 	writel_relaxed(wake_active, base + stm32_bank->imr_ofst);  in stm32_chip_suspend()
206 	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;  in stm32_chip_resume()
207 	void __iomem *base = chip_data->host_data->base;  in stm32_chip_resume()
210 	writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);  in stm32_chip_resume()
211 	writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);  in stm32_chip_resume()
213 	writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);  in stm32_chip_resume()
218 	struct stm32_exti_chip_data *chip_data = gc->private;  in stm32_irq_suspend()
221 	stm32_chip_suspend(chip_data, gc->wake_active);  in stm32_irq_suspend()
227 	struct stm32_exti_chip_data *chip_data = gc->private;  in stm32_irq_resume()
230 	stm32_chip_resume(chip_data, gc->mask_cache);  in stm32_irq_resume()
240 	hwirq = fwspec->param[0];  in stm32_exti_alloc()
265 	struct stm32_exti_chip_data *chip_data = gc->private;  in stm32_irq_ack()
266 	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;  in stm32_irq_ack()
270 	irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);  in stm32_irq_ack()
285 	host_data->drv_data = dd;  in stm32_exti_host_init()
286 	host_data->chips_data = kcalloc(dd->bank_nr,  in stm32_exti_host_init()
289 	if (!host_data->chips_data)  in stm32_exti_host_init()
292 	host_data->base = of_iomap(node, 0);  in stm32_exti_host_init()
293 	if (!host_data->base) {  in stm32_exti_host_init()
301 	kfree(host_data->chips_data);  in stm32_exti_host_init()
315 	void __iomem *base = h_data->base;  in stm32_exti_chip_init()
317 	stm32_bank = h_data->drv_data->exti_banks[bank_idx];  in stm32_exti_chip_init()
318 	chip_data = &h_data->chips_data[bank_idx];  in stm32_exti_chip_init()
319 	chip_data->host_data = h_data;  in stm32_exti_chip_init()
320 	chip_data->reg_bank = stm32_bank;  in stm32_exti_chip_init()
326 	writel_relaxed(0, base + stm32_bank->imr_ofst);  in stm32_exti_chip_init()
327 	writel_relaxed(0, base + stm32_bank->emr_ofst);  in stm32_exti_chip_init()
345 		return -ENOMEM;  in stm32_exti_init()
347 	domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,  in stm32_exti_init()
352 		ret = -ENOMEM;  in stm32_exti_init()
356 	ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",  in stm32_exti_init()
364 	for (i = 0; i < drv_data->bank_nr; i++) {  in stm32_exti_init()
368 		stm32_bank = drv_data->exti_banks[i];  in stm32_exti_init()
373 		gc->reg_base = host_data->base;  in stm32_exti_init()
374 		gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;  in stm32_exti_init()
375 		gc->chip_types->chip.irq_ack = stm32_irq_ack;  in stm32_exti_init()
376 		gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;  in stm32_exti_init()
377 		gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;  in stm32_exti_init()
378 		gc->chip_types->chip.irq_set_type = stm32_irq_set_type;  in stm32_exti_init()
379 		gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;  in stm32_exti_init()
380 		gc->suspend = stm32_irq_suspend;  in stm32_exti_init()
381 		gc->resume = stm32_irq_resume;  in stm32_exti_init()
382 		gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);  in stm32_exti_init()
384 		gc->chip_types->regs.mask = stm32_bank->imr_ofst;  in stm32_exti_init()
385 		gc->private = (void *)chip_data;  in stm32_exti_init()
401 	iounmap(host_data->base);  in stm32_exti_init()
402 	kfree(host_data->chips_data);  in stm32_exti_init()
413 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
421 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);