22 #define REG_INTR_TYPE		(sp_intc.g0)
28 #define REG_INTR_CLEAR		(sp_intc.g1)
58 #define ASSIGN_STATE(irq, idx, v)	assign_bit(STATE_BIT(irq, idx), sp_intc.states, v)
59 #define TEST_STATE(irq, idx)		test_bit(STATE_BIT(irq, idx), sp_intc.states)
77 } sp_intc;  variable
90 	raw_spin_lock_irqsave(&sp_intc.lock, flags);  in sp_intc_assign_bit()
97 	raw_spin_unlock_irqrestore(&sp_intc.lock, flags);  in sp_intc_assign_bit()
180 			generic_handle_domain_irq(sp_intc.domain, hwirq);  in sp_intc_handle_ext_cascaded()
227 	sp_intc.g0 = of_iomap(node, 0);  in sp_intc_init_dt()
228 	if (!sp_intc.g0)  in sp_intc_init_dt()
231 	sp_intc.g1 = of_iomap(node, 1);  in sp_intc_init_dt()
232 	if (!sp_intc.g1) {  in sp_intc_init_dt()
259 	sp_intc.domain = irq_domain_add_linear(node, SP_INTC_NR_IRQS,  in sp_intc_init_dt()
260 					       &sp_intc_dm_ops, &sp_intc);  in sp_intc_init_dt()
261 	if (!sp_intc.domain) {  in sp_intc_init_dt()
266 	raw_spin_lock_init(&sp_intc.lock);  in sp_intc_init_dt()
271 	iounmap(sp_intc.g1);  in sp_intc_init_dt()
273 	iounmap(sp_intc.g0);  in sp_intc_init_dt()
278 IRQCHIP_DECLARE(sp_intc, "sunplus,sp7021-intc", sp_intc_init_dt);