54 	int hw_irq;  member
113 						   int reg, int hw_irq)  in intc_irqpin_hwirq_mask()  argument
115 	return BIT((p->iomem[reg].width - 1) - hw_irq);  in intc_irqpin_hwirq_mask()
119 					       int reg, int hw_irq)  in intc_irqpin_irq_write_hwirq()  argument
121 	intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));  in intc_irqpin_irq_write_hwirq()
174 		str, i->requested_irq, i->hw_irq, i->domain_irq);  in intc_irqpin_dbg()
180 	int hw_irq = irqd_to_hwirq(d);  in intc_irqpin_irq_enable()  local
182 	intc_irqpin_dbg(&p->irq[hw_irq], "enable");  in intc_irqpin_irq_enable()
183 	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);  in intc_irqpin_irq_enable()
189 	int hw_irq = irqd_to_hwirq(d);  in intc_irqpin_irq_disable()  local
191 	intc_irqpin_dbg(&p->irq[hw_irq], "disable");  in intc_irqpin_irq_disable()
192 	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);  in intc_irqpin_irq_disable()
198 	int hw_irq = irqd_to_hwirq(d);  in intc_irqpin_shared_irq_enable()  local
200 	intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");  in intc_irqpin_shared_irq_enable()
201 	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);  in intc_irqpin_shared_irq_enable()
203 	p->shared_irq_mask &= ~BIT(hw_irq);  in intc_irqpin_shared_irq_enable()
209 	int hw_irq = irqd_to_hwirq(d);  in intc_irqpin_shared_irq_disable()  local
211 	intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");  in intc_irqpin_shared_irq_disable()
212 	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);  in intc_irqpin_shared_irq_disable()
214 	p->shared_irq_mask |= BIT(hw_irq);  in intc_irqpin_shared_irq_disable()
270 	int hw_irq = irqd_to_hwirq(d);  in intc_irqpin_irq_set_wake()  local
272 	irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);  in intc_irqpin_irq_set_wake()
288 	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);  in intc_irqpin_irq_handler()
333 	p->irq[hw].hw_irq = hw;  in intc_irqpin_irq_domain_map()