Lines Matching full:sirq

3  * Actions Semi Owl SoCs SIRQ interrupt controller driver
32 /* S500 & S700 SIRQ control register masks */
37 /* S900 SIRQ control register offsets, relative to controller base address */
43 	/* INTC_EXTCTL reg shared for all three SIRQ lines */
139 	 * is edge triggered, so we need per SIRQ based clearing.  in owl_sirq_eoi()
165  * GIC does not handle falling edge or active low, hence SIRQ shall be
200 	.name		= "owl-sirq",
287 		pr_err("%pOF: failed to find sirq parent domain\n", node);  in owl_sirq_init()
301 		pr_err("%pOF: failed to map sirq registers\n", node);  in owl_sirq_init()
350 IRQCHIP_DECLARE(owl_sirq_s500, "actions,s500-sirq", owl_sirq_s500_of_init);
351 IRQCHIP_DECLARE(owl_sirq_s700, "actions,s700-sirq", owl_sirq_s500_of_init);
359 IRQCHIP_DECLARE(owl_sirq_s900, "actions,s900-sirq", owl_sirq_s900_of_init);