Lines Matching full:ompic

11  * The ompic device handles IPI communication between cores in multi-core
16  * For each CPU the ompic has 2 registers. The control register for sending
36  * - The ompic generates a level interrupt to the CPU PIC when a message is
38  * - The ompic does not have any interrupt input lines.
39  * - The ompic is wired to the same irq line on each core.
55  *   | ompic  |<===/    | Device |<===/
156 		pr_err("ompic: duplicate ompic's are not supported");  in ompic_of_init()
161 		pr_err("ompic: reg property requires an address and size");  in ompic_of_init()
166 		pr_err("ompic: reg size, currently %d must be at least %d",  in ompic_of_init()
175 		pr_err("ompic: unable to map registers");  in ompic_of_init()
181 		pr_err("ompic: unable to parse device irq");  in ompic_of_init()
202 IRQCHIP_DECLARE(ompic, "openrisc,ompic", ompic_of_init);