Lines Matching +full:v7m +full:- +full:nvic
1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/irq/irq-nvic.c
9 * ARMv7-M CPUs (Cortex-M3/M4)
24 #include <asm/v7m.h>
36 #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
43 irq_hw_number_t hwirq = (icsr & V7M_SCB_ICSR_VECTACTIVE) - 16; in nvic_handle_irq()
85 pr_warn("unable to map nvic registers\n"); in nvic_of_init()
86 return -ENOMEM; in nvic_of_init()
99 return -ENOMEM; in nvic_of_init()
116 gc->reg_base = nvic_base + 4 * i; in nvic_of_init()
117 gc->chip_types[0].regs.enable = NVIC_ISER; in nvic_of_init()
118 gc->chip_types[0].regs.disable = NVIC_ICER; in nvic_of_init()
119 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in nvic_of_init()
120 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in nvic_of_init()
121 /* This is a no-op as end of interrupt is signaled by the in nvic_of_init()
124 gc->chip_types[0].chip.irq_eoi = irq_gc_noop; in nvic_of_init()
127 writel_relaxed(~0, gc->reg_base + NVIC_ICER); in nvic_of_init()
137 IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);