5  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
27 #define PIC_MAX_IRQ_MASK	((1UL << PIC_MAX_IRQS) - 1)
36 static void mvebu_pic_reset(struct mvebu_pic *pic)  in mvebu_pic_reset()  argument
39 	writel(0, pic->base + PIC_MASK);  in mvebu_pic_reset()
40 	writel(PIC_MAX_IRQ_MASK, pic->base + PIC_CAUSE);  in mvebu_pic_reset()
45 	struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);  in mvebu_pic_eoi_irq()  local
47 	writel(1 << d->hwirq, pic->base + PIC_CAUSE);  in mvebu_pic_eoi_irq()
52 	struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);  in mvebu_pic_mask_irq()  local
55 	reg =  readl(pic->base + PIC_MASK);  in mvebu_pic_mask_irq()
56 	reg |= (1 << d->hwirq);  in mvebu_pic_mask_irq()
57 	writel(reg, pic->base + PIC_MASK);  in mvebu_pic_mask_irq()
62 	struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);  in mvebu_pic_unmask_irq()  local
65 	reg = readl(pic->base + PIC_MASK);  in mvebu_pic_unmask_irq()
66 	reg &= ~(1 << d->hwirq);  in mvebu_pic_unmask_irq()
67 	writel(reg, pic->base + PIC_MASK);  in mvebu_pic_unmask_irq()
72 	struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);  in mvebu_pic_print_chip()  local
74 	seq_puts(p, dev_name(&pic->pdev->dev));  in mvebu_pic_print_chip()
87 	struct mvebu_pic *pic = domain->host_data;  in mvebu_pic_irq_map()  local
90 	irq_set_chip_data(virq, pic);  in mvebu_pic_irq_map()
105 	struct mvebu_pic *pic = irq_desc_get_handler_data(desc);  in mvebu_pic_handle_cascade_irq()  local
109 	irqmap = readl_relaxed(pic->base + PIC_CAUSE);  in mvebu_pic_handle_cascade_irq()
113 		generic_handle_domain_irq(pic->domain, irqn);  in mvebu_pic_handle_cascade_irq()
120 	struct mvebu_pic *pic = data;  in mvebu_pic_enable_percpu_irq()  local
122 	mvebu_pic_reset(pic);  in mvebu_pic_enable_percpu_irq()
123 	enable_percpu_irq(pic->parent_irq, IRQ_TYPE_NONE);  in mvebu_pic_enable_percpu_irq()
128 	struct mvebu_pic *pic = data;  in mvebu_pic_disable_percpu_irq()  local
130 	disable_percpu_irq(pic->parent_irq);  in mvebu_pic_disable_percpu_irq()
135 	struct device_node *node = pdev->dev.of_node;  in mvebu_pic_probe()
136 	struct mvebu_pic *pic;  in mvebu_pic_probe()  local
138 	pic = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pic), GFP_KERNEL);  in mvebu_pic_probe()
139 	if (!pic)  in mvebu_pic_probe()
140 		return -ENOMEM;  in mvebu_pic_probe()
142 	pic->pdev = pdev;  in mvebu_pic_probe()
143 	pic->base = devm_platform_ioremap_resource(pdev, 0);  in mvebu_pic_probe()
144 	if (IS_ERR(pic->base))  in mvebu_pic_probe()
145 		return PTR_ERR(pic->base);  in mvebu_pic_probe()
147 	pic->parent_irq = irq_of_parse_and_map(node, 0);  in mvebu_pic_probe()
148 	if (pic->parent_irq <= 0) {  in mvebu_pic_probe()
149 		dev_err(&pdev->dev, "Failed to parse parent interrupt\n");  in mvebu_pic_probe()
150 		return -EINVAL;  in mvebu_pic_probe()
153 	pic->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), PIC_MAX_IRQS,  in mvebu_pic_probe()
154 					       &mvebu_pic_domain_ops, pic);  in mvebu_pic_probe()
155 	if (!pic->domain) {  in mvebu_pic_probe()
156 		dev_err(&pdev->dev, "Failed to allocate irq domain\n");  in mvebu_pic_probe()
157 		return -ENOMEM;  in mvebu_pic_probe()
160 	irq_set_chained_handler(pic->parent_irq, mvebu_pic_handle_cascade_irq);  in mvebu_pic_probe()
161 	irq_set_handler_data(pic->parent_irq, pic);  in mvebu_pic_probe()
163 	on_each_cpu(mvebu_pic_enable_percpu_irq, pic, 1);  in mvebu_pic_probe()
165 	platform_set_drvdata(pdev, pic);  in mvebu_pic_probe()
172 	struct mvebu_pic *pic = platform_get_drvdata(pdev);  in mvebu_pic_remove()  local
174 	on_each_cpu(mvebu_pic_disable_percpu_irq, pic, 1);  in mvebu_pic_remove()
175 	irq_domain_remove(pic->domain);  in mvebu_pic_remove()
179 	{ .compatible = "marvell,armada-8k-pic", },
188 		.name		= "mvebu-pic",
195 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
196 MODULE_DESCRIPTION("Marvell Armada 7K/8K PIC driver");