1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
28  * struct mchp_eic - EIC private data structure
32  * @irqs: irqs b/w eic and gic
33  * @scfg: backup for scfg registers (necessary for backup and self-refresh mode)
45 static struct mchp_eic *eic;  variable
51 	tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq));  in mchp_eic_irq_mask()
53 	writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq));  in mchp_eic_irq_mask()
62 	tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq));  in mchp_eic_irq_unmask()
64 	writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq));  in mchp_eic_irq_unmask()
74 	tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq));  in mchp_eic_irq_set_type()
93 		return -EINVAL;  in mchp_eic_irq_set_type()
96 	writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq));  in mchp_eic_irq_set_type()
103 	irq_set_irq_wake(eic->irqs[d->hwirq], on);  in mchp_eic_irq_set_wake()
105 		eic->wakeup_source |= BIT(d->hwirq);  in mchp_eic_irq_set_wake()
107 		eic->wakeup_source &= ~BIT(d->hwirq);  in mchp_eic_irq_set_wake()
117 		eic->scfg[hwirq] = readl_relaxed(eic->base +  in mchp_eic_irq_suspend()
120 	if (!eic->wakeup_source)  in mchp_eic_irq_suspend()
121 		clk_disable_unprepare(eic->clk);  in mchp_eic_irq_suspend()
130 	if (!eic->wakeup_source)  in mchp_eic_irq_resume()
131 		clk_prepare_enable(eic->clk);  in mchp_eic_irq_resume()
134 		writel_relaxed(eic->scfg[hwirq], eic->base +  in mchp_eic_irq_resume()
144 	.name		= "eic",
165 		return -EINVAL;  in mchp_eic_domain_alloc()
182 		return -EINVAL;  in mchp_eic_domain_alloc()
185 	irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &mchp_eic_chip, eic);  in mchp_eic_domain_alloc()
187 	parent_fwspec.fwnode = domain->parent->fwnode;  in mchp_eic_domain_alloc()
190 	parent_fwspec.param[1] = eic->irqs[hwirq];  in mchp_eic_domain_alloc()
207 	eic = kzalloc(sizeof(*eic), GFP_KERNEL);  in mchp_eic_init()
208 	if (!eic)  in mchp_eic_init()
209 		return -ENOMEM;  in mchp_eic_init()
211 	eic->base = of_iomap(node, 0);  in mchp_eic_init()
212 	if (!eic->base) {  in mchp_eic_init()
213 		ret = -ENOMEM;  in mchp_eic_init()
219 		ret = -ENODEV;  in mchp_eic_init()
223 	eic->clk = of_clk_get_by_name(node, "pclk");  in mchp_eic_init()
224 	if (IS_ERR(eic->clk)) {  in mchp_eic_init()
225 		ret = PTR_ERR(eic->clk);  in mchp_eic_init()
229 	ret = clk_prepare_enable(eic->clk);  in mchp_eic_init()
237 		writel_relaxed(0UL, eic->base + MCHP_EIC_SCFG(i));  in mchp_eic_init()
244 			ret = -EINVAL;  in mchp_eic_init()
248 		eic->irqs[i] = irq.args[1];  in mchp_eic_init()
251 	eic->domain = irq_domain_add_hierarchy(parent_domain, 0, MCHP_EIC_NIRQ,  in mchp_eic_init()
252 					       node, &mchp_eic_domain_ops, eic);  in mchp_eic_init()
253 	if (!eic->domain) {  in mchp_eic_init()
255 		ret = -ENODEV;  in mchp_eic_init()
261 	pr_info("%pOF: EIC registered, nr_irqs %u\n", node, MCHP_EIC_NIRQ);  in mchp_eic_init()
266 	clk_disable_unprepare(eic->clk);  in mchp_eic_init()
268 	iounmap(eic->base);  in mchp_eic_init()
270 	kfree(eic);  in mchp_eic_init()
275 IRQCHIP_MATCH("microchip,sama7g5-eic", mchp_eic_init)