1 // SPDX-License-Identifier: GPL-2.0
3  * JZ47xx SoCs TCU IRQ driver
11 #include <linux/mfd/ingenic-tcu.h>
26 	struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);  in ingenic_tcu_intc_cascade()
29 	struct regmap *map = gc->private;  in ingenic_tcu_intc_cascade()
52 	struct regmap *map = gc->private;  in ingenic_tcu_gc_unmask_enable_reg()
53 	u32 mask = d->mask;  in ingenic_tcu_gc_unmask_enable_reg()
55 	guard(raw_spinlock)(&gc->lock);  in ingenic_tcu_gc_unmask_enable_reg()
56 	regmap_write(map, ct->regs.ack, mask);  in ingenic_tcu_gc_unmask_enable_reg()
57 	regmap_write(map, ct->regs.enable, mask);  in ingenic_tcu_gc_unmask_enable_reg()
58 	*ct->mask_cache |= mask;  in ingenic_tcu_gc_unmask_enable_reg()
65 	struct regmap *map = gc->private;  in ingenic_tcu_gc_mask_disable_reg()
66 	u32 mask = d->mask;  in ingenic_tcu_gc_mask_disable_reg()
68 	guard(raw_spinlock)(&gc->lock);  in ingenic_tcu_gc_mask_disable_reg()
69 	regmap_write(map, ct->regs.disable, mask);  in ingenic_tcu_gc_mask_disable_reg()
70 	*ct->mask_cache &= ~mask;  in ingenic_tcu_gc_mask_disable_reg()
77 	struct regmap *map = gc->private;  in ingenic_tcu_gc_mask_disable_reg_and_ack()
78 	u32 mask = d->mask;  in ingenic_tcu_gc_mask_disable_reg_and_ack()
80 	guard(raw_spinlock)(&gc->lock);  in ingenic_tcu_gc_mask_disable_reg_and_ack()
81 	regmap_write(map, ct->regs.ack, mask);  in ingenic_tcu_gc_mask_disable_reg_and_ack()
82 	regmap_write(map, ct->regs.disable, mask);  in ingenic_tcu_gc_mask_disable_reg_and_ack()
90 	struct ingenic_tcu *tcu;  in ingenic_tcu_irq_init()  local
99 	tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);  in ingenic_tcu_irq_init()
100 	if (!tcu)  in ingenic_tcu_irq_init()
101 		return -ENOMEM;  in ingenic_tcu_irq_init()
103 	tcu->map = map;  in ingenic_tcu_irq_init()
106 	if (irqs < 0 || irqs > ARRAY_SIZE(tcu->parent_irqs)) {  in ingenic_tcu_irq_init()
108 		ret = -EINVAL;  in ingenic_tcu_irq_init()
112 	tcu->nb_parent_irqs = irqs;  in ingenic_tcu_irq_init()
114 	tcu->domain = irq_domain_create_linear(of_fwnode_handle(np), 32, &irq_generic_chip_ops,  in ingenic_tcu_irq_init()
116 	if (!tcu->domain) {  in ingenic_tcu_irq_init()
117 		ret = -ENOMEM;  in ingenic_tcu_irq_init()
121 	ret = irq_alloc_domain_generic_chips(tcu->domain, 32, 1, "TCU",  in ingenic_tcu_irq_init()
129 	gc = irq_get_domain_generic_chip(tcu->domain, 0);  in ingenic_tcu_irq_init()
130 	ct = gc->chip_types;  in ingenic_tcu_irq_init()
132 	gc->wake_enabled = IRQ_MSK(32);  in ingenic_tcu_irq_init()
133 	gc->private = tcu->map;  in ingenic_tcu_irq_init()
135 	ct->regs.disable = TCU_REG_TMSR;  in ingenic_tcu_irq_init()
136 	ct->regs.enable = TCU_REG_TMCR;  in ingenic_tcu_irq_init()
137 	ct->regs.ack = TCU_REG_TFCR;  in ingenic_tcu_irq_init()
138 	ct->chip.irq_unmask = ingenic_tcu_gc_unmask_enable_reg;  in ingenic_tcu_irq_init()
139 	ct->chip.irq_mask = ingenic_tcu_gc_mask_disable_reg;  in ingenic_tcu_irq_init()
140 	ct->chip.irq_mask_ack = ingenic_tcu_gc_mask_disable_reg_and_ack;  in ingenic_tcu_irq_init()
141 	ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;  in ingenic_tcu_irq_init()
144 	regmap_write(tcu->map, TCU_REG_TMSR, IRQ_MSK(32));  in ingenic_tcu_irq_init()
148 	 * timers 2-7 share one interrupt.  in ingenic_tcu_irq_init()
150 	 * timers 0-4 and 6-7 share one single interrupt.  in ingenic_tcu_irq_init()
157 		tcu->parent_irqs[i] = irq_of_parse_and_map(np, i);  in ingenic_tcu_irq_init()
158 		if (!tcu->parent_irqs[i]) {  in ingenic_tcu_irq_init()
159 			ret = -EINVAL;  in ingenic_tcu_irq_init()
163 		irq_set_chained_handler_and_data(tcu->parent_irqs[i],  in ingenic_tcu_irq_init()
165 						 tcu->domain);  in ingenic_tcu_irq_init()
171 	for (; i > 0; i--)  in ingenic_tcu_irq_init()
172 		irq_dispose_mapping(tcu->parent_irqs[i - 1]);  in ingenic_tcu_irq_init()
174 	irq_domain_remove(tcu->domain);  in ingenic_tcu_irq_init()
176 	kfree(tcu);  in ingenic_tcu_irq_init()
179 IRQCHIP_DECLARE(jz4740_tcu_irq, "ingenic,jz4740-tcu", ingenic_tcu_irq_init);
180 IRQCHIP_DECLARE(jz4725b_tcu_irq, "ingenic,jz4725b-tcu", ingenic_tcu_irq_init);
181 IRQCHIP_DECLARE(jz4760_tcu_irq, "ingenic,jz4760-tcu", ingenic_tcu_irq_init);
182 IRQCHIP_DECLARE(jz4770_tcu_irq, "ingenic,jz4770-tcu", ingenic_tcu_irq_init);
183 IRQCHIP_DECLARE(x1000_tcu_irq, "ingenic,x1000-tcu", ingenic_tcu_irq_init);