Lines Matching +full:1 +full:x64 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
10 * Based on drivers/mailbox/imx-mailbox.c
27 #include "irq-msi-lib.h"
48 IMX_MU_V2 = BIT(1),
52 #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
53 #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
75 iowrite32(val, msi_data->regs + offs);
80 return ioread32(msi_data->regs + offs);
88 raw_spin_lock_irqsave(&msi_data->lock, flags);
89 val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]);
92 imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]);
93 raw_spin_unlock_irqrestore(&msi_data->lock, flags);
102 imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(msi_data, data->hwirq));
109 imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, IMX_MU_xCR_RIEn(msi_data, data->hwirq), 0);
116 imx_mu_read(msi_data, msi_data->cfg->xRR + data->hwirq * 4);
123 u64 addr = msi_data->msiir_addr + 4 * data->hwirq;
125 msg->address_hi = upper_32_bits(addr);
126 msg->address_lo = lower_32_bits(addr);
127 msg->data = data->hwirq;
133 return -EINVAL;
150 struct imx_mu_msi *msi_data = domain->host_data;
154 WARN_ON(nr_irqs != 1);
156 raw_spin_lock_irqsave(&msi_data->lock, flags);
157 pos = find_first_zero_bit(&msi_data->used, IMX_MU_CHANS);
159 __set_bit(pos, &msi_data->used);
161 err = -ENOSPC;
162 raw_spin_unlock_irqrestore(&msi_data->lock, flags);
180 raw_spin_lock_irqsave(&msi_data->lock, flags);
181 __clear_bit(d->hwirq, &msi_data->used);
182 raw_spin_unlock_irqrestore(&msi_data->lock, flags);
198 status = imx_mu_read(msi_data, msi_data->cfg->xSR[IMX_MU_RSR]);
203 generic_handle_domain_irq(msi_data->msi_domain, i);
220 .prefix = "MU-MSI-",
234 return -ENOMEM;
238 parent->dev = parent->pm_dev = dev;
239 parent->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;
240 parent->msi_parent_ops = &imx_mu_msi_parent_ops;
274 [IMX_MU_GIER] = 0x64,
275 [IMX_MU_GCR] = 0x64,
276 [IMX_MU_TCR] = 0x64,
277 [IMX_MU_RCR] = 0x64,
314 dev = &pdev->dev;
316 msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
318 return -ENOMEM;
320 msi_data->cfg = cfg;
322 msi_data->regs = devm_platform_ioremap_resource_byname(pdev, "processor-a-side");
323 if (IS_ERR(msi_data->regs)) {
324 dev_err(&pdev->dev, "failed to initialize 'regs'\n");
325 return PTR_ERR(msi_data->regs);
328 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "processor-b-side");
330 return -EIO;
332 msi_data->msiir_addr = res->start + msi_data->cfg->xTR;
340 msi_data->clk = devm_clk_get(dev, NULL);
341 if (IS_ERR(msi_data->clk))
342 return PTR_ERR(msi_data->clk);
344 pd_a = dev_pm_domain_attach_by_name(dev, "processor-a-side");
348 pd_b = dev_pm_domain_attach_by_name(dev, "processor-b-side");
390 return -EINVAL;
397 clk_disable_unprepare(priv->clk);
407 ret = clk_prepare_enable(priv->clk);
438 IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_of_init)
439 IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_of_init)
440 IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_of_init)