1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2002-2014 ARM Limited.
6  * Copyright (c) 2013-2014 HiSilicon Ltd.
7  * Copyright (c) 2013-2014 Linaro Ltd.
9  * Interrupt architecture for the HIP04 INTC:
11  * o There is one Interrupt Distributor, which receives interrupts
12  *   from system devices and sends them to the Interrupt Controllers.
20  * Note that IRQs 0-31 are special - they are local to each CPU.
22  * registers are banked per-cpu for these sources.
39 #include <linux/interrupt.h>
42 #include <linux/irqchip/arm-gic.h>
48 #include "irq-gic-common.h"
74 	return hip04_data->dist_base;  in hip04_dist_base()
80 	return hip04_data->cpu_base;  in hip04_cpu_base()
85 	return d->hwirq;  in hip04_irq()
93 	u32 mask = 1 << (hip04_irq(d) % 32);  in hip04_mask_irq()  local
96 	writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR +  in hip04_mask_irq()
103 	u32 mask = 1 << (hip04_irq(d) % 32);  in hip04_unmask_irq()  local
106 	writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET +  in hip04_unmask_irq()
122 	/* Interrupt configuration for SGIs can't be changed */  in hip04_irq_set_type()
124 		return -EINVAL;  in hip04_irq_set_type()
129 		return -EINVAL;  in hip04_irq_set_type()
136 		pr_warn("GIC: PPI%d is secure or misconfigured\n", irq - 16);  in hip04_irq_set_type()
152 	u32 val, mask, bit;  in hip04_irq_set_affinity()  local
160 		return -EINVAL;  in hip04_irq_set_affinity()
164 	mask = 0xffff << shift;  in hip04_irq_set_affinity()
166 	val = readl_relaxed(reg) & ~mask;  in hip04_irq_set_affinity()
175 static void hip04_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)  in hip04_ipi_send_mask()  argument
178 	unsigned long flags, map = 0;  in hip04_ipi_send_mask()  local
182 	/* Convert our logical CPU mask into a physical one. */  in hip04_ipi_send_mask()
183 	for_each_cpu(cpu, mask)  in hip04_ipi_send_mask()
184 		map |= hip04_cpu_map[cpu];  in hip04_ipi_send_mask()
193 	writel_relaxed(map << 8 | d->hwirq, hip04_data.dist_base + GIC_DIST_SOFTINT);  in hip04_ipi_send_mask()
230 	void __iomem *base = intc->dist_base;  in hip04_get_cpumask()
231 	u32 mask, i;  in hip04_get_cpumask()  local
233 	for (i = mask = 0; i < 32; i += 2) {  in hip04_get_cpumask()
234 		mask = readl_relaxed(base + GIC_DIST_TARGET + i * 2);  in hip04_get_cpumask()
235 		mask |= mask >> 16;  in hip04_get_cpumask()
236 		if (mask)  in hip04_get_cpumask()
240 	if (!mask)  in hip04_get_cpumask()
241 		pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");  in hip04_get_cpumask()
243 	return mask;  in hip04_get_cpumask()
250 	unsigned int nr_irqs = intc->nr_irqs;  in hip04_irq_dist_init()
251 	void __iomem *base = intc->dist_base;  in hip04_irq_dist_init()
270 	void __iomem *dist_base = intc->dist_base;  in hip04_irq_cpu_init()
271 	void __iomem *base = intc->cpu_base;  in hip04_irq_cpu_init()
276 	 * Get what the GIC says our CPU mask is.  in hip04_irq_cpu_init()
283 	 * Clear our mask from the other map entries in case they're  in hip04_irq_cpu_init()
309 	irq_set_chip_data(irq, d->host_data);  in hip04_irq_domain_map()
320 		return -EINVAL;  in hip04_irq_domain_xlate()
327 		return -EINVAL;  in hip04_irq_domain_xlate()
329 	/* Get the interrupt number and add 16 to skip over SGIs */  in hip04_irq_domain_xlate()
348 	.map	= hip04_irq_domain_map,
358 		return -ENODEV;  in hip04_of_init()
361 	WARN(!hip04_data.dist_base, "fail to map hip04 intc dist registers\n");  in hip04_of_init()
364 	WARN(!hip04_data.cpu_base, "unable to map hip04 intc cpu registers\n");  in hip04_of_init()
367 	 * Initialize the CPU interface map to all CPUs.  in hip04_of_init()
375 	 * The HIP04 INTC only supports up to 510 interrupt sources.  in hip04_of_init()
383 	irq_base = irq_alloc_descs(-1, 0, nr_irqs, numa_node_id());  in hip04_of_init()
386 		return -EINVAL;  in hip04_of_init()
394 		return -EINVAL;  in hip04_of_init()
406 IRQCHIP_DECLARE(hip04_intc, "hisilicon,hip04-intc", hip04_of_init);