Lines Matching +full:gic +full:- +full:v5
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2024-2025 ARM Limited, All Rights Reserved.
15 #include <linux/irqchip/arm-gic-v5.h>
16 #include <linux/irqchip/arm-vgic-info.h>
24 #define GICV5_IRQ_PRI_MI (GICV5_IRQ_PRI_MASK & GENMASK(4, 5 - pri_bits))
51 return -ENOSPC; in alloc_lpi()
53 return ida_alloc_max(&lpi_ida, num_lpis - 1, GFP_KERNEL); in alloc_lpi()
123 u64 hwirq_id_bit = BIT_ULL(d->hwirq % 64); in gicv5_ppi_irq_mask()
125 if (d->hwirq < 64) in gicv5_ppi_irq_mask()
132 * guarantee that the lazy-disabled IRQ mechanism works. in gicv5_ppi_irq_mask()
134 * Reference: I_ZLTKB/R_YRGMH GICv5 specification - section 2.9.1. in gicv5_ppi_irq_mask()
143 cddis = FIELD_PREP(GICV5_GIC_CDDIS_ID_MASK, d->hwirq) | in gicv5_iri_irq_mask()
148 * We must make sure that GIC CDDIS write effects are propagated in gicv5_iri_irq_mask()
150 * that the lazy-disabled IRQ mechanism works. in gicv5_iri_irq_mask()
151 * Rule R_XCLJC states that the effects of a GIC system instruction in gicv5_iri_irq_mask()
153 * The GSB ensures completion of the GIC instruction and prevents in gicv5_iri_irq_mask()
154 * loads, stores and GIC instructions from executing part of their in gicv5_iri_irq_mask()
172 u64 hwirq_id_bit = BIT_ULL(d->hwirq % 64); in gicv5_ppi_irq_unmask()
174 if (d->hwirq < 64) in gicv5_ppi_irq_unmask()
179 * We must ensure that the enable takes effect in finite time - a in gicv5_ppi_irq_unmask()
183 * Reference: I_ZLTKB/R_YRGMH GICv5 specification - section 2.9.1. in gicv5_ppi_irq_unmask()
192 cden = FIELD_PREP(GICV5_GIC_CDEN_ID_MASK, d->hwirq) | in gicv5_iri_irq_unmask()
195 * Rule R_XCLJC states that the effects of a GIC system instruction in gicv5_iri_irq_unmask()
232 gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_PPI); in gicv5_ppi_irq_eoi()
237 gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_SPI); in gicv5_spi_irq_eoi()
242 gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_LPI); in gicv5_lpi_irq_eoi()
264 FIELD_PREP(GICV5_GIC_CDAFF_ID_MASK, d->hwirq); in gicv5_iri_irq_set_affinity()
353 u64 hwirq_id_bit = BIT_ULL(d->hwirq % 64); in gicv5_ppi_irq_get_irqchip_state()
357 *state = !!(read_ppi_sysreg_s(d->hwirq, PPI_PENDING) & hwirq_id_bit); in gicv5_ppi_irq_get_irqchip_state()
360 *state = !!(read_ppi_sysreg_s(d->hwirq, PPI_ACTIVE) & hwirq_id_bit); in gicv5_ppi_irq_get_irqchip_state()
364 return -EINVAL; in gicv5_ppi_irq_get_irqchip_state()
374 cdrcfg = d->hwirq | FIELD_PREP(GICV5_GIC_CDRCFG_TYPE_MASK, hwirq_type); in gicv5_iri_irq_get_irqchip_state()
382 return -EINVAL; in gicv5_iri_irq_get_irqchip_state()
396 return -EINVAL; in gicv5_iri_irq_get_irqchip_state()
422 write_ppi_sysreg_s(d->hwirq, state, PPI_PENDING); in gicv5_ppi_irq_set_irqchip_state()
425 write_ppi_sysreg_s(d->hwirq, state, PPI_ACTIVE); in gicv5_ppi_irq_set_irqchip_state()
429 return -EINVAL; in gicv5_ppi_irq_set_irqchip_state()
439 FIELD_PREP(GICV5_GIC_CDPEND_ID_MASK, d->hwirq) | in gicv5_iri_irq_write_pending_state()
465 return -EINVAL; in gicv5_spi_irq_set_irqchip_state()
482 return -EINVAL; in gicv5_lpi_irq_set_irqchip_state()
524 .name = "GICv5-PPI",
536 .name = "GICv5-SPI",
551 .name = "GICv5-LPI",
564 .name = "GICv5-IPI",
582 if (!is_of_node(fwspec->fwnode)) in gicv5_irq_domain_translate()
583 return -EINVAL; in gicv5_irq_domain_translate()
585 if (fwspec->param_count < 3) in gicv5_irq_domain_translate()
586 return -EINVAL; in gicv5_irq_domain_translate()
588 if (fwspec->param[0] != hwirq_type) in gicv5_irq_domain_translate()
589 return -EINVAL; in gicv5_irq_domain_translate()
591 *hwirq = fwspec->param[1]; in gicv5_irq_domain_translate()
603 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in gicv5_irq_domain_translate()
630 return -EINVAL; in gicv5_irq_ppi_domain_alloc()
663 if (fwspec->fwnode != d->fwnode) in gicv5_irq_ppi_domain_select()
666 if (fwspec->param[0] != GICV5_HWIRQ_TYPE_PPI) in gicv5_irq_ppi_domain_select()
699 return -EINVAL; in gicv5_irq_spi_domain_alloc()
721 if (fwspec->fwnode != d->fwnode) in gicv5_irq_spi_domain_select()
724 if (fwspec->param[0] != GICV5_HWIRQ_TYPE_SPI) in gicv5_irq_spi_domain_select()
748 FIELD_PREP(GICV5_GIC_CDHM_ID_MASK, d->hwirq); in gicv5_lpi_config_reset()
763 return -EINVAL; in gicv5_irq_lpi_domain_alloc()
847 gicv5_free_lpi(d->parent_data->hwirq); in gicv5_irq_ipi_domain_free()
946 return -ENODEV; in gicv5_starting_cpu()
990 return -ENOMEM; in gicv5_init_domains()
1001 return -ENOMEM; in gicv5_init_domains()
1017 return -ENOMEM; in gicv5_init_domains()
1076 /* GIC Virtual CPU interface maintenance interrupt */ in gic_of_setup_kvm_info()
1137 IRQCHIP_DECLARE(gic_v5, "arm,gic-v5", gicv5_of_init);