Lines Matching +full:col +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
37 #include <linux/irqchip/arm-gic-v3.h>
38 #include <linux/irqchip/arm-gic-v4.h>
43 #include "irq-gic-common.h"
44 #include "irq-msi-lib.h"
71 * Collection structure - just an ID, and a redistributor address to
81 * The ITS_BASER structure - contains memory information, cached
94 * The ITS structure - contains most of the infrastructure, with the
95 * top-level MSI domain, the command queue, the collections, and the
128 #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
129 #define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP))
130 #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
138 if (gic_rdists->has_rvpeid && \
139 gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \
140 nvpeid = 1 + (gic_rdists->gicd_typer2 & \
162 * The ITS view of a device - belongs to an ITS, owns an interrupt
203 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
204 #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
205 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
295 return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]); in require_its_list_vmovp()
300 return !(gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE); in rdists_support_shareable()
313 __set_bit(its->list_nr, &its_list); in get_its_list()
322 return d->hwirq - its_dev->event_map.lpi_base; in its_get_event_id()
328 struct its_node *its = its_dev->its; in dev_event_to_col()
330 return its->collections + its_dev->event_map.col_map[event]; in dev_event_to_col()
336 if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis)) in dev_event_to_vlpi_map()
339 return &its_dev->event_map.vlpi_maps[event]; in dev_event_to_vlpi_map()
356 raw_spin_lock_irqsave(&vpe->vpe_lock, *flags); in vpe_to_cpuid_lock()
357 return vpe->col_idx; in vpe_to_cpuid_lock()
362 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags); in vpe_to_cpuid_unlock()
372 if (d->chip == &its_vpe_irq_chip) { in irq_to_cpuid_lock()
377 vpe = map->vpe; in irq_to_cpuid_lock()
385 cpu = its_dev->event_map.col_map[its_get_event_id(d)]; in irq_to_cpuid_lock()
397 if (d->chip == &its_vpe_irq_chip) { in irq_to_cpuid_unlock()
402 vpe = map->vpe; in irq_to_cpuid_unlock()
409 static struct its_collection *valid_col(struct its_collection *col) in valid_col() argument
411 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0))) in valid_col()
414 return col; in valid_col()
419 if (valid_col(its->collections + vpe->col_idx)) in valid_vpe()
426 * ITS command descriptors - parameters to be encoded in a command
452 struct its_collection *col; member
464 struct its_collection *col; member
474 struct its_collection *col; member
483 struct its_collection *col; member
504 struct its_collection *col; member
554 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); in its_encode_cmd()
559 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); in its_encode_devid()
564 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); in its_encode_event_id()
569 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); in its_encode_phys_id()
574 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); in its_encode_size()
579 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8); in its_encode_itt()
584 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); in its_encode_valid()
589 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16); in its_encode_target()
592 static void its_encode_collection(struct its_cmd_block *cmd, u16 col) in its_encode_collection() argument
594 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); in its_encode_collection()
599 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32); in its_encode_vpeid()
604 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0); in its_encode_virt_id()
609 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32); in its_encode_db_phys_id()
614 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0); in its_encode_db_valid()
619 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32); in its_encode_seq_num()
624 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0); in its_encode_its_list()
629 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16); in its_encode_vpt_addr()
634 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0); in its_encode_vpt_size()
639 its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16); in its_encode_vconf_addr()
644 its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8); in its_encode_alloc()
649 its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9); in its_encode_ptz()
655 its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0); in its_encode_vmapp_default_db()
661 its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0); in its_encode_vmovp_default_db()
666 its_mask_encode(&cmd->raw_cmd[2], db, 63, 63); in its_encode_db()
671 its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32); in its_encode_sgi_intid()
676 its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20); in its_encode_sgi_priority()
681 its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10); in its_encode_sgi_group()
686 its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9); in its_encode_sgi_clear()
691 its_mask_encode(&cmd->raw_cmd[0], en, 8, 8); in its_encode_sgi_enable()
697 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]); in its_fixup_cmd()
698 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]); in its_fixup_cmd()
699 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]); in its_fixup_cmd()
700 cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]); in its_fixup_cmd()
708 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); in its_build_mapd_cmd()
710 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); in its_build_mapd_cmd()
713 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); in its_build_mapd_cmd()
714 its_encode_size(cmd, size - 1); in its_build_mapd_cmd()
716 its_encode_valid(cmd, desc->its_mapd_cmd.valid); in its_build_mapd_cmd()
728 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); in its_build_mapc_cmd()
729 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); in its_build_mapc_cmd()
730 its_encode_valid(cmd, desc->its_mapc_cmd.valid); in its_build_mapc_cmd()
734 return desc->its_mapc_cmd.col; in its_build_mapc_cmd()
741 struct its_collection *col; in its_build_mapti_cmd() local
743 col = dev_event_to_col(desc->its_mapti_cmd.dev, in its_build_mapti_cmd()
744 desc->its_mapti_cmd.event_id); in its_build_mapti_cmd()
747 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); in its_build_mapti_cmd()
748 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); in its_build_mapti_cmd()
749 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); in its_build_mapti_cmd()
750 its_encode_collection(cmd, col->col_id); in its_build_mapti_cmd()
754 return valid_col(col); in its_build_mapti_cmd()
761 struct its_collection *col; in its_build_movi_cmd() local
763 col = dev_event_to_col(desc->its_movi_cmd.dev, in its_build_movi_cmd()
764 desc->its_movi_cmd.event_id); in its_build_movi_cmd()
767 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); in its_build_movi_cmd()
768 its_encode_event_id(cmd, desc->its_movi_cmd.event_id); in its_build_movi_cmd()
769 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); in its_build_movi_cmd()
773 return valid_col(col); in its_build_movi_cmd()
780 struct its_collection *col; in its_build_discard_cmd() local
782 col = dev_event_to_col(desc->its_discard_cmd.dev, in its_build_discard_cmd()
783 desc->its_discard_cmd.event_id); in its_build_discard_cmd()
786 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); in its_build_discard_cmd()
787 its_encode_event_id(cmd, desc->its_discard_cmd.event_id); in its_build_discard_cmd()
791 return valid_col(col); in its_build_discard_cmd()
798 struct its_collection *col; in its_build_inv_cmd() local
800 col = dev_event_to_col(desc->its_inv_cmd.dev, in its_build_inv_cmd()
801 desc->its_inv_cmd.event_id); in its_build_inv_cmd()
804 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); in its_build_inv_cmd()
805 its_encode_event_id(cmd, desc->its_inv_cmd.event_id); in its_build_inv_cmd()
809 return valid_col(col); in its_build_inv_cmd()
816 struct its_collection *col; in its_build_int_cmd() local
818 col = dev_event_to_col(desc->its_int_cmd.dev, in its_build_int_cmd()
819 desc->its_int_cmd.event_id); in its_build_int_cmd()
822 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); in its_build_int_cmd()
823 its_encode_event_id(cmd, desc->its_int_cmd.event_id); in its_build_int_cmd()
827 return valid_col(col); in its_build_int_cmd()
834 struct its_collection *col; in its_build_clear_cmd() local
836 col = dev_event_to_col(desc->its_clear_cmd.dev, in its_build_clear_cmd()
837 desc->its_clear_cmd.event_id); in its_build_clear_cmd()
840 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); in its_build_clear_cmd()
841 its_encode_event_id(cmd, desc->its_clear_cmd.event_id); in its_build_clear_cmd()
845 return valid_col(col); in its_build_clear_cmd()
853 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id); in its_build_invall_cmd()
857 return desc->its_invall_cmd.col; in its_build_invall_cmd()
865 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id); in its_build_vinvall_cmd()
869 return valid_vpe(its, desc->its_vinvall_cmd.vpe); in its_build_vinvall_cmd()
876 struct its_vpe *vpe = valid_vpe(its, desc->its_vmapp_cmd.vpe); in its_build_vmapp_cmd()
882 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id); in its_build_vmapp_cmd()
883 its_encode_valid(cmd, desc->its_vmapp_cmd.valid); in its_build_vmapp_cmd()
885 if (!desc->its_vmapp_cmd.valid) { in its_build_vmapp_cmd()
886 alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count); in its_build_vmapp_cmd()
890 * Unmapping a VPE is self-synchronizing on GICv4.1, in its_build_vmapp_cmd()
899 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page)); in its_build_vmapp_cmd()
900 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset; in its_build_vmapp_cmd()
904 its_encode_vpt_size(cmd, LPI_NRBITS - 1); in its_build_vmapp_cmd()
906 alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count); in its_build_vmapp_cmd()
911 vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page)); in its_build_vmapp_cmd()
923 its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi); in its_build_vmapp_cmd()
937 if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled) in its_build_vmapti_cmd()
938 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi; in its_build_vmapti_cmd()
943 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id); in its_build_vmapti_cmd()
944 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id); in its_build_vmapti_cmd()
945 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id); in its_build_vmapti_cmd()
947 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id); in its_build_vmapti_cmd()
951 return valid_vpe(its, desc->its_vmapti_cmd.vpe); in its_build_vmapti_cmd()
960 if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled) in its_build_vmovi_cmd()
961 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi; in its_build_vmovi_cmd()
966 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id); in its_build_vmovi_cmd()
967 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id); in its_build_vmovi_cmd()
968 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id); in its_build_vmovi_cmd()
974 return valid_vpe(its, desc->its_vmovi_cmd.vpe); in its_build_vmovi_cmd()
983 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset; in its_build_vmovp_cmd()
985 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num); in its_build_vmovp_cmd()
986 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list); in its_build_vmovp_cmd()
987 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id); in its_build_vmovp_cmd()
992 its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi); in its_build_vmovp_cmd()
997 return valid_vpe(its, desc->its_vmovp_cmd.vpe); in its_build_vmovp_cmd()
1006 map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev, in its_build_vinv_cmd()
1007 desc->its_inv_cmd.event_id); in its_build_vinv_cmd()
1010 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); in its_build_vinv_cmd()
1011 its_encode_event_id(cmd, desc->its_inv_cmd.event_id); in its_build_vinv_cmd()
1015 return valid_vpe(its, map->vpe); in its_build_vinv_cmd()
1024 map = dev_event_to_vlpi_map(desc->its_int_cmd.dev, in its_build_vint_cmd()
1025 desc->its_int_cmd.event_id); in its_build_vint_cmd()
1028 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); in its_build_vint_cmd()
1029 its_encode_event_id(cmd, desc->its_int_cmd.event_id); in its_build_vint_cmd()
1033 return valid_vpe(its, map->vpe); in its_build_vint_cmd()
1042 map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev, in its_build_vclear_cmd()
1043 desc->its_clear_cmd.event_id); in its_build_vclear_cmd()
1046 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); in its_build_vclear_cmd()
1047 its_encode_event_id(cmd, desc->its_clear_cmd.event_id); in its_build_vclear_cmd()
1051 return valid_vpe(its, map->vpe); in its_build_vclear_cmd()
1062 its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id); in its_build_invdb_cmd()
1066 return valid_vpe(its, desc->its_invdb_cmd.vpe); in its_build_invdb_cmd()
1077 its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id); in its_build_vsgi_cmd()
1078 its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi); in its_build_vsgi_cmd()
1079 its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority); in its_build_vsgi_cmd()
1080 its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group); in its_build_vsgi_cmd()
1081 its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear); in its_build_vsgi_cmd()
1082 its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable); in its_build_vsgi_cmd()
1086 return valid_vpe(its, desc->its_vsgi_cmd.vpe); in its_build_vsgi_cmd()
1092 return (ptr - its->cmd_base) * sizeof(*ptr); in its_cmd_ptr_to_offset()
1100 widx = its->cmd_write - its->cmd_base; in its_queue_full()
1101 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); in its_queue_full()
1116 count--; in its_allocate_entry()
1125 cmd = its->cmd_write++; in its_allocate_entry()
1128 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) in its_allocate_entry()
1129 its->cmd_write = its->cmd_base; in its_allocate_entry()
1132 cmd->raw_cmd[0] = 0; in its_allocate_entry()
1133 cmd->raw_cmd[1] = 0; in its_allocate_entry()
1134 cmd->raw_cmd[2] = 0; in its_allocate_entry()
1135 cmd->raw_cmd[3] = 0; in its_allocate_entry()
1142 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); in its_post_commands()
1144 writel_relaxed(wr, its->base + GITS_CWRITER); in its_post_commands()
1146 return its->cmd_write; in its_post_commands()
1155 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) in its_flush_cmd()
1178 rd_idx = readl_relaxed(its->base + GITS_CREADR); in its_wait_for_range_completion()
1182 * potential wrap-around into account. in its_wait_for_range_completion()
1184 delta = rd_idx - prev_idx; in its_wait_for_range_completion()
1192 count--; in its_wait_for_range_completion()
1196 return -1; in its_wait_for_range_completion()
1217 raw_spin_lock_irqsave(&its->lock, flags); \
1221 raw_spin_unlock_irqrestore(&its->lock, flags); \
1237 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
1239 raw_spin_unlock_irqrestore(&its->lock, flags); \
1250 its_encode_target(sync_cmd, sync_col->target_address); in its_build_sync_cmd()
1263 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id); in BUILD_SINGLE_CMD_FUNC()
1278 its_send_single_command(dev->its, its_build_int_cmd, &desc); in BUILD_SINGLE_CMD_FUNC()
1288 its_send_single_command(dev->its, its_build_clear_cmd, &desc); in its_send_clear()
1298 its_send_single_command(dev->its, its_build_inv_cmd, &desc); in its_send_inv()
1308 its_send_single_command(dev->its, its_build_mapd_cmd, &desc); in its_send_mapd()
1311 static void its_send_mapc(struct its_node *its, struct its_collection *col, in its_send_mapc() argument
1316 desc.its_mapc_cmd.col = col; in its_send_mapc()
1330 its_send_single_command(dev->its, its_build_mapti_cmd, &desc); in its_send_mapti()
1334 struct its_collection *col, u32 id) in its_send_movi() argument
1339 desc.its_movi_cmd.col = col; in its_send_movi()
1342 its_send_single_command(dev->its, its_build_movi_cmd, &desc); in its_send_movi()
1352 its_send_single_command(dev->its, its_build_discard_cmd, &desc); in its_send_discard()
1355 static void its_send_invall(struct its_node *its, struct its_collection *col) in its_send_invall() argument
1359 desc.its_invall_cmd.col = col; in its_send_invall()
1369 desc.its_vmapti_cmd.vpe = map->vpe; in its_send_vmapti()
1371 desc.its_vmapti_cmd.virt_id = map->vintid; in its_send_vmapti()
1373 desc.its_vmapti_cmd.db_enabled = map->db_enabled; in its_send_vmapti()
1375 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc); in its_send_vmapti()
1383 desc.its_vmovi_cmd.vpe = map->vpe; in its_send_vmovi()
1386 desc.its_vmovi_cmd.db_enabled = map->db_enabled; in its_send_vmovi()
1388 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc); in its_send_vmovi()
1398 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx]; in its_send_vmapp()
1407 int col_id = vpe->col_idx; in its_send_vmovp()
1413 desc.its_vmovp_cmd.col = &its->collections[col_id]; in its_send_vmovp()
1424 * Wall <-- Head. in its_send_vmovp()
1428 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm); in its_send_vmovp()
1435 if (!require_its_list_vmovp(vpe->its_vm, its)) in its_send_vmovp()
1438 desc.its_vmovp_cmd.col = &its->collections[col_id]; in its_send_vmovp()
1462 its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc); in its_send_vinv()
1476 its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc); in its_send_vint()
1490 its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc); in its_send_vclear()
1502 * irqchip functions - assumes MSI, mostly.
1512 va = page_address(map->vm->vprop_page); in lpi_write_config()
1513 hwirq = map->vintid; in lpi_write_config()
1516 map->properties &= ~clr; in lpi_write_config()
1517 map->properties |= set | LPI_PROP_GROUP1; in lpi_write_config()
1519 va = gic_rdists->prop_table_va; in lpi_write_config()
1520 hwirq = d->hwirq; in lpi_write_config()
1523 cfg = va + hwirq - 8192; in lpi_write_config()
1532 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) in lpi_write_config()
1552 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); in __direct_lpi_inv()
1554 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; in __direct_lpi_inv()
1558 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); in __direct_lpi_inv()
1570 WARN_ON(!is_v4_1(its_dev->its)); in direct_lpi_inv()
1573 val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id); in direct_lpi_inv()
1574 val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid); in direct_lpi_inv()
1576 val = d->hwirq; in direct_lpi_inv()
1587 if (gic_rdists->has_direct_lpi && in lpi_update_config()
1588 (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d))) in lpi_update_config()
1603 * GICv4.1 does away with the per-LPI nonsense, nothing to do in its_vlpi_set_doorbell()
1606 if (is_v4_1(its_dev->its)) in its_vlpi_set_doorbell()
1611 if (map->db_enabled == enable) in its_vlpi_set_doorbell()
1614 map->db_enabled = enable; in its_vlpi_set_doorbell()
1648 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); in its_read_lpi_count()
1650 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); in its_read_lpi_count()
1656 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); in its_inc_lpi_count()
1658 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); in its_inc_lpi_count()
1664 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); in its_dec_lpi_count()
1666 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); in its_dec_lpi_count()
1699 node = its_dev->its->numa_node; in its_select_cpu()
1731 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)) in its_select_cpu()
1749 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) && in its_select_cpu()
1758 pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu); in its_select_cpu()
1772 return -EINVAL; in its_set_affinity()
1774 prev_cpu = its_dev->event_map.col_map[id]; in its_set_affinity()
1787 target_col = &its_dev->its->collections[cpu]; in its_set_affinity()
1789 its_dev->event_map.col_map[id] = cpu; in its_set_affinity()
1799 return -EINVAL; in its_set_affinity()
1804 struct its_node *its = its_dev->its; in its_irq_get_msi_base()
1806 return its->phys_base + GITS_TRANSLATER; in its_irq_get_msi_base()
1815 its = its_dev->its; in its_irq_compose_msi_msg()
1816 addr = its->get_msi_base(its_dev); in its_irq_compose_msi_msg()
1818 msg->address_lo = lower_32_bits(addr); in its_irq_compose_msi_msg()
1819 msg->address_hi = upper_32_bits(addr); in its_irq_compose_msi_msg()
1820 msg->data = its_get_event_id(d); in its_irq_compose_msi_msg()
1833 return -EINVAL; in its_irq_set_irqchip_state()
1869 if (!its_list_map || gic_rdists->has_rvpeid) in gic_requires_eager_mapping()
1880 guard(raw_spinlock_irqsave)(&vm->vmapp_lock); in its_map_vm()
1886 vm->vlpi_count[its->list_nr]++; in its_map_vm()
1888 if (vm->vlpi_count[its->list_nr] == 1) { in its_map_vm()
1891 for (i = 0; i < vm->nr_vpes; i++) { in its_map_vm()
1892 struct its_vpe *vpe = vm->vpes[i]; in its_map_vm()
1894 scoped_guard(raw_spinlock, &vpe->vpe_lock) in its_map_vm()
1908 guard(raw_spinlock_irqsave)(&vm->vmapp_lock); in its_unmap_vm()
1910 if (!--vm->vlpi_count[its->list_nr]) { in its_unmap_vm()
1913 for (i = 0; i < vm->nr_vpes; i++) { in its_unmap_vm()
1914 guard(raw_spinlock)(&vm->vpes[i]->vpe_lock); in its_unmap_vm()
1915 its_send_vmapp(its, vm->vpes[i], false); in its_unmap_vm()
1925 if (!info->map) in its_vlpi_map()
1926 return -EINVAL; in its_vlpi_map()
1928 if (!its_dev->event_map.vm) { in its_vlpi_map()
1931 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps), in its_vlpi_map()
1934 return -ENOMEM; in its_vlpi_map()
1936 its_dev->event_map.vm = info->map->vm; in its_vlpi_map()
1937 its_dev->event_map.vlpi_maps = maps; in its_vlpi_map()
1938 } else if (its_dev->event_map.vm != info->map->vm) { in its_vlpi_map()
1939 return -EINVAL; in its_vlpi_map()
1943 its_dev->event_map.vlpi_maps[event] = *info->map; in its_vlpi_map()
1950 its_map_vm(its_dev->its, info->map->vm); in its_vlpi_map()
1959 lpi_write_config(d, 0xff, info->map->properties); in its_vlpi_map()
1968 its_dev->event_map.nr_vlpis++; in its_vlpi_map()
1981 if (!its_dev->event_map.vm || !map) in its_vlpi_get()
1982 return -EINVAL; in its_vlpi_get()
1985 *info->map = *map; in its_vlpi_get()
1995 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) in its_vlpi_unmap()
1996 return -EINVAL; in its_vlpi_unmap()
2003 its_send_mapti(its_dev, d->hwirq, event); in its_vlpi_unmap()
2009 its_unmap_vm(its_dev->its, its_dev->event_map.vm); in its_vlpi_unmap()
2015 if (!--its_dev->event_map.nr_vlpis) { in its_vlpi_unmap()
2016 its_dev->event_map.vm = NULL; in its_vlpi_unmap()
2017 kfree(its_dev->event_map.vlpi_maps); in its_vlpi_unmap()
2027 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) in its_vlpi_prop_update()
2028 return -EINVAL; in its_vlpi_prop_update()
2030 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI) in its_vlpi_prop_update()
2031 lpi_update_config(d, 0xff, info->config); in its_vlpi_prop_update()
2033 lpi_write_config(d, 0xff, info->config); in its_vlpi_prop_update()
2034 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED)); in its_vlpi_prop_update()
2045 if (!is_v4(its_dev->its)) in its_irq_set_vcpu_affinity()
2046 return -EINVAL; in its_irq_set_vcpu_affinity()
2048 guard(raw_spinlock_irq)(&its_dev->event_map.vlpi_lock); in its_irq_set_vcpu_affinity()
2054 switch (info->cmd_type) { in its_irq_set_vcpu_affinity()
2066 return -EINVAL; in its_irq_set_vcpu_affinity()
2115 range->base_id = base; in mk_lpi_range()
2116 range->span = span; in mk_lpi_range()
2125 int err = -ENOSPC; in alloc_lpi_range()
2130 if (range->span >= nr_lpis) { in alloc_lpi_range()
2131 *base = range->base_id; in alloc_lpi_range()
2132 range->base_id += nr_lpis; in alloc_lpi_range()
2133 range->span -= nr_lpis; in alloc_lpi_range()
2135 if (range->span == 0) { in alloc_lpi_range()
2136 list_del(&range->entry); in alloc_lpi_range()
2153 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list) in merge_lpi_ranges()
2155 if (a->base_id + a->span != b->base_id) in merge_lpi_ranges()
2157 b->base_id = a->base_id; in merge_lpi_ranges()
2158 b->span += a->span; in merge_lpi_ranges()
2159 list_del(&a->entry); in merge_lpi_ranges()
2169 return -ENOMEM; in free_lpi_range()
2174 if (old->base_id < base) in free_lpi_range()
2178 * old is the last element with ->base_id smaller than base, in free_lpi_range()
2180 * ->base_id smaller than base, &old->entry ends up pointing in free_lpi_range()
2184 list_add(&new->entry, &old->entry); in free_lpi_range()
2198 u32 lpis = (1UL << id_bits) - 8192; in its_lpi_init()
2202 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer); in its_lpi_init()
2233 err = -ENOSPC; in its_lpi_alloc()
2259 /* Regular IRQ priority, Group-1, disabled */ in gic_reset_prop_table()
2298 addr_end = addr + size - 1; in gic_check_reserved_range()
2322 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) { in its_setup_lpi_prop_table()
2328 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12); in its_setup_lpi_prop_table()
2329 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa, in its_setup_lpi_prop_table()
2332 gic_reset_prop_table(gic_rdists->prop_table_va); in its_setup_lpi_prop_table()
2337 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer), in its_setup_lpi_prop_table()
2342 return -ENOMEM; in its_setup_lpi_prop_table()
2345 gic_rdists->prop_table_pa = page_to_phys(page); in its_setup_lpi_prop_table()
2346 gic_rdists->prop_table_va = page_address(page); in its_setup_lpi_prop_table()
2347 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa, in its_setup_lpi_prop_table()
2352 &gic_rdists->prop_table_pa); in its_setup_lpi_prop_table()
2369 u32 idx = baser - its->tables; in its_read_baser()
2371 return gits_read_baser(its->base + GITS_BASER + (idx << 3)); in its_read_baser()
2377 u32 idx = baser - its->tables; in its_write_baser()
2379 gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); in its_write_baser()
2380 baser->val = its_read_baser(its, baser); in its_write_baser()
2394 psz = baser->psz; in its_setup_baser()
2397 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", in its_setup_baser()
2398 &its->phys_base, its_base_type_string[type], in its_setup_baser()
2404 page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); in its_setup_baser()
2406 return -ENOMEM; in its_setup_baser()
2418 return -ENXIO; in its_setup_baser()
2428 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | in its_setup_baser()
2429 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | in its_setup_baser()
2452 tmp = baser->val; in its_setup_baser()
2460 * non-cacheable as well. in its_setup_baser()
2471 &its->phys_base, its_base_type_string[type], in its_setup_baser()
2474 return -ENXIO; in its_setup_baser()
2477 baser->order = order; in its_setup_baser()
2478 baser->base = base; in its_setup_baser()
2479 baser->psz = psz; in its_setup_baser()
2483 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), in its_setup_baser()
2501 u32 psz = baser->psz; in its_parse_indirect_baser()
2507 * Find out whether hw supports a single or two-level table by in its_parse_indirect_baser()
2508 * table by reading bit at offset '62' after writing '1' to it. in its_parse_indirect_baser()
2511 indirect = !!(baser->val & GITS_BASER_INDIRECT); in its_parse_indirect_baser()
2521 ids -= ilog2(psz / (int)esz); in its_parse_indirect_baser()
2530 * massive waste of memory if two-level device table in its_parse_indirect_baser()
2537 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n", in its_parse_indirect_baser()
2538 &its->phys_base, its_base_type_string[type], in its_parse_indirect_baser()
2567 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer); in compute_its_aff()
2569 val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr); in compute_its_aff()
2578 if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer)) in find_sibling_its()
2589 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) in find_sibling_its()
2596 baser = its->tables[2].val; in find_sibling_its()
2611 if (its->tables[i].base) { in its_free_tables()
2612 its_free_pages(its->tables[i].base, its->tables[i].order); in its_free_tables()
2613 its->tables[i].base = NULL; in its_free_tables()
2646 if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz) in its_probe_baser_psz()
2658 return -1; in its_probe_baser_psz()
2662 baser->psz = psz; in its_probe_baser_psz()
2672 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) in its_alloc_tables()
2676 if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) { in its_alloc_tables()
2682 struct its_baser *baser = its->tables + i; in its_alloc_tables()
2693 return -ENXIO; in its_alloc_tables()
2696 order = get_order(baser->psz); in its_alloc_tables()
2710 *baser = sibling->tables[2]; in its_alloc_tables()
2711 its_write_baser(its, baser, baser->val); in its_alloc_tables()
2728 cache = baser->val & GITS_BASER_CACHEABILITY_MASK; in its_alloc_tables()
2729 shr = baser->val & GITS_BASER_SHAREABILITY_MASK; in its_alloc_tables()
2750 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) in inherit_vpe_l1_table_from_its()
2757 baser = its->tables[2].val; in inherit_vpe_l1_table_from_its()
2762 gic_data_rdist()->vpe_l1_base = its->tables[2].base; in inherit_vpe_l1_table_from_its()
2784 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1); in inherit_vpe_l1_table_from_its()
2802 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base; in inherit_vpe_l1_table_from_rd()
2820 gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base; in inherit_vpe_l1_table_from_rd()
2821 *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask; in inherit_vpe_l1_table_from_rd()
2831 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base; in allocate_vpe_l2_table()
2837 if (!gic_rdists->has_rvpeid) in allocate_vpe_l2_table()
2840 /* Skip non-present CPUs */ in allocate_vpe_l2_table()
2874 table = gic_data_rdist_cpu(cpu)->vpe_l1_base; in allocate_vpe_l2_table()
2907 if (!gic_rdists->has_rvpeid) in allocate_vpe_l1_table()
2926 val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask); in allocate_vpe_l1_table()
2930 gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC); in allocate_vpe_l1_table()
2931 if (!gic_data_rdist()->vpe_table_mask) in allocate_vpe_l1_table()
2932 return -ENOMEM; in allocate_vpe_l1_table()
2990 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1); in allocate_vpe_l1_table()
2999 return -ENOMEM; in allocate_vpe_l1_table()
3001 gic_data_rdist()->vpe_l1_base = page_address(page); in allocate_vpe_l1_table()
3015 cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask); in allocate_vpe_l1_table()
3019 cpumask_pr_args(gic_data_rdist()->vpe_table_mask)); in allocate_vpe_l1_table()
3028 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections), in its_alloc_collections()
3030 if (!its->collections) in its_alloc_collections()
3031 return -ENOMEM; in its_alloc_collections()
3034 its->collections[i].target_address = ~0ULL; in its_alloc_collections()
3047 /* Make sure the GIC will observe the zero-ed page */ in its_allocate_pending_table()
3081 * flag the RD tables as pre-allocated if the stars do align. in allocate_lpi_tables()
3085 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED | in allocate_lpi_tables()
3105 return -ENOMEM; in allocate_lpi_tables()
3108 gic_data_rdist_cpu(cpu)->pend_page = pend_page; in allocate_lpi_tables()
3124 count--; in read_vpend_dirty_clear()
3161 if (gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED) in its_cpu_init_lpis()
3165 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) && in its_cpu_init_lpis()
3173 if (WARN_ON(gic_rdists->prop_table_pa != paddr)) in its_cpu_init_lpis()
3180 gic_data_rdist()->flags |= RD_LOCAL_PENDTABLE_PREALLOCATED; in its_cpu_init_lpis()
3185 pend_page = gic_data_rdist()->pend_page; in its_cpu_init_lpis()
3189 val = (gic_rdists->prop_table_pa | in its_cpu_init_lpis()
3192 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); in its_cpu_init_lpis()
3203 * The HW reports non-shareable, we must in its_cpu_init_lpis()
3213 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; in its_cpu_init_lpis()
3229 * The HW reports non-shareable, we must remove the in its_cpu_init_lpis()
3244 if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) { in its_cpu_init_lpis()
3254 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; in its_cpu_init_lpis()
3273 gic_rdists->has_rvpeid = false; in its_cpu_init_lpis()
3274 gic_rdists->has_vlpis = false; in its_cpu_init_lpis()
3279 gic_data_rdist()->flags |= RD_LOCAL_LPI_ENABLED; in its_cpu_init_lpis()
3282 gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED ? in its_cpu_init_lpis()
3293 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { in its_cpu_init_collection()
3297 if (its->numa_node != NUMA_NO_NODE && in its_cpu_init_collection()
3298 its->numa_node != of_node_to_nid(cpu_node)) in its_cpu_init_collection()
3306 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { in its_cpu_init_collection()
3311 target = gic_data_rdist()->phys_base; in its_cpu_init_collection()
3319 its->collections[cpu].target_address = target; in its_cpu_init_collection()
3320 its->collections[cpu].col_id = cpu; in its_cpu_init_collection()
3322 its_send_mapc(its, &its->collections[cpu], 1); in its_cpu_init_collection()
3323 its_send_invall(its, &its->collections[cpu]); in its_cpu_init_collection()
3343 raw_spin_lock_irqsave(&its->lock, flags); in its_find_device()
3345 list_for_each_entry(tmp, &its->its_device_list, entry) { in its_find_device()
3346 if (tmp->device_id == dev_id) { in its_find_device()
3352 raw_spin_unlock_irqrestore(&its->lock, flags); in its_find_device()
3362 if (GITS_BASER_TYPE(its->tables[i].val) == type) in its_get_baser()
3363 return &its->tables[i]; in its_get_baser()
3377 esz = GITS_BASER_ENTRY_SIZE(baser->val); in its_alloc_table_entry()
3378 if (!(baser->val & GITS_BASER_INDIRECT)) in its_alloc_table_entry()
3379 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); in its_alloc_table_entry()
3382 idx = id >> ilog2(baser->psz / esz); in its_alloc_table_entry()
3383 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) in its_alloc_table_entry()
3386 table = baser->base; in its_alloc_table_entry()
3390 page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, in its_alloc_table_entry()
3391 get_order(baser->psz)); in its_alloc_table_entry()
3396 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) in its_alloc_table_entry()
3397 gic_flush_dcache_to_poc(page_address(page), baser->psz); in its_alloc_table_entry()
3402 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) in its_alloc_table_entry()
3452 if (!gic_rdists->has_rvpeid) in its_alloc_vpe_table()
3491 sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); in its_create_device()
3494 itt = itt_alloc_pool(its->numa_node, sz); in its_create_device()
3519 dev->its = its; in its_create_device()
3520 dev->itt = itt; in its_create_device()
3521 dev->itt_sz = sz; in its_create_device()
3522 dev->nr_ites = nr_ites; in its_create_device()
3523 dev->event_map.lpi_map = lpi_map; in its_create_device()
3524 dev->event_map.col_map = col_map; in its_create_device()
3525 dev->event_map.lpi_base = lpi_base; in its_create_device()
3526 dev->event_map.nr_lpis = nr_lpis; in its_create_device()
3527 raw_spin_lock_init(&dev->event_map.vlpi_lock); in its_create_device()
3528 dev->device_id = dev_id; in its_create_device()
3529 INIT_LIST_HEAD(&dev->entry); in its_create_device()
3531 raw_spin_lock_irqsave(&its->lock, flags); in its_create_device()
3532 list_add(&dev->entry, &its->its_device_list); in its_create_device()
3533 raw_spin_unlock_irqrestore(&its->lock, flags); in its_create_device()
3545 raw_spin_lock_irqsave(&its_dev->its->lock, flags); in its_free_device()
3546 list_del(&its_dev->entry); in its_free_device()
3547 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); in its_free_device()
3548 kfree(its_dev->event_map.col_map); in its_free_device()
3549 itt_free_pool(its_dev->itt, its_dev->itt_sz); in its_free_device()
3558 idx = bitmap_find_free_region(dev->event_map.lpi_map, in its_alloc_device_irq()
3559 dev->event_map.nr_lpis, in its_alloc_device_irq()
3562 return -ENOSPC; in its_alloc_device_irq()
3564 *hwirq = dev->event_map.lpi_base + idx; in its_alloc_device_irq()
3584 dev_id = info->scratchpad[0].ul; in its_msi_prepare()
3587 its = msi_info->data; in its_msi_prepare()
3589 if (!gic_rdists->has_direct_lpi && in its_msi_prepare()
3591 vpe_proxy.dev->its == its && in its_msi_prepare()
3592 dev_id == vpe_proxy.dev->device_id) { in its_msi_prepare()
3596 return -EINVAL; in its_msi_prepare()
3599 mutex_lock(&its->dev_alloc_lock); in its_msi_prepare()
3607 its_dev->shared = true; in its_msi_prepare()
3614 err = -ENOMEM; in its_msi_prepare()
3618 if (info->flags & MSI_ALLOC_FLAGS_PROXY_DEVICE) in its_msi_prepare()
3619 its_dev->shared = true; in its_msi_prepare()
3623 mutex_unlock(&its->dev_alloc_lock); in its_msi_prepare()
3624 info->scratchpad[0].ptr = its_dev; in its_msi_prepare()
3638 if (irq_domain_get_of_node(domain->parent)) { in its_irq_gic_domain_alloc()
3639 fwspec.fwnode = domain->parent->fwnode; in its_irq_gic_domain_alloc()
3644 } else if (is_fwnode_irqchip(domain->parent->fwnode)) { in its_irq_gic_domain_alloc()
3645 fwspec.fwnode = domain->parent->fwnode; in its_irq_gic_domain_alloc()
3650 return -EINVAL; in its_irq_gic_domain_alloc()
3660 struct its_device *its_dev = info->scratchpad[0].ptr; in its_irq_domain_alloc()
3661 struct its_node *its = its_dev->its; in its_irq_domain_alloc()
3671 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev)); in its_irq_domain_alloc()
3687 (int)(hwirq + i - its_dev->event_map.lpi_base), in its_irq_domain_alloc()
3703 return -EINVAL; in its_irq_domain_activate()
3706 its_dev->event_map.col_map[event] = cpu; in its_irq_domain_activate()
3710 its_send_mapti(its_dev, d->hwirq, event); in its_irq_domain_activate()
3720 its_dec_lpi_count(d, its_dev->event_map.col_map[event]); in its_irq_domain_deactivate()
3730 struct its_node *its = its_dev->its; in its_irq_domain_free()
3733 bitmap_release_region(its_dev->event_map.lpi_map, in its_irq_domain_free()
3744 mutex_lock(&its->dev_alloc_lock); in its_irq_domain_free()
3750 if (!its_dev->shared && in its_irq_domain_free()
3751 bitmap_empty(its_dev->event_map.lpi_map, in its_irq_domain_free()
3752 its_dev->event_map.nr_lpis)) { in its_irq_domain_free()
3753 its_lpi_free(its_dev->event_map.lpi_map, in its_irq_domain_free()
3754 its_dev->event_map.lpi_base, in its_irq_domain_free()
3755 its_dev->event_map.nr_lpis); in its_irq_domain_free()
3762 mutex_unlock(&its->dev_alloc_lock); in its_irq_domain_free()
3797 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_unmap_locked()
3801 if (vpe->vpe_proxy_event == -1) in its_vpe_db_proxy_unmap_locked()
3804 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event); in its_vpe_db_proxy_unmap_locked()
3805 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL; in its_vpe_db_proxy_unmap_locked()
3815 vpe_proxy.next_victim = vpe->vpe_proxy_event; in its_vpe_db_proxy_unmap_locked()
3817 vpe->vpe_proxy_event = -1; in its_vpe_db_proxy_unmap_locked()
3823 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_unmap()
3826 if (!gic_rdists->has_direct_lpi) { in its_vpe_db_proxy_unmap()
3838 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_map_locked()
3842 if (vpe->vpe_proxy_event != -1) in its_vpe_db_proxy_map_locked()
3851 vpe->vpe_proxy_event = vpe_proxy.next_victim; in its_vpe_db_proxy_map_locked()
3852 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites; in its_vpe_db_proxy_map_locked()
3854 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx; in its_vpe_db_proxy_map_locked()
3855 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event); in its_vpe_db_proxy_map_locked()
3864 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_move()
3867 if (gic_rdists->has_direct_lpi) { in its_vpe_db_proxy_move()
3870 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base; in its_vpe_db_proxy_move()
3871 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); in its_vpe_db_proxy_move()
3881 target_col = &vpe_proxy.dev->its->collections[to]; in its_vpe_db_proxy_move()
3882 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event); in its_vpe_db_proxy_move()
3883 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to; in its_vpe_db_proxy_move()
3894 val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id); in its_vpe_4_1_invall_locked()
3896 guard(raw_spinlock)(&gic_data_rdist_cpu(cpu)->rd_lock); in its_vpe_4_1_invall_locked()
3897 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; in its_vpe_4_1_invall_locked()
3916 if (!atomic_read(&vpe->vmapp_count)) { in its_vpe_set_affinity()
3918 return -EINVAL; in its_vpe_set_affinity()
3938 * protect us, and that we must ensure nobody samples vpe->col_idx in its_vpe_set_affinity()
3940 * taken on any vLPI handling path that evaluates vpe->col_idx. in its_vpe_set_affinity()
3947 raw_spin_lock(&vpe->its_vm->vmapp_lock); in its_vpe_set_affinity()
3950 table_mask = gic_data_rdist_cpu(from)->vpe_table_mask; in its_vpe_set_affinity()
3969 vpe->col_idx = cpu; in its_vpe_set_affinity()
3974 if (its && its->flags & ITS_FLAGS_WORKAROUND_HISILICON_162100801) in its_vpe_set_affinity()
3984 raw_spin_unlock(&vpe->its_vm->vmapp_lock); in its_vpe_set_affinity()
3994 if (!gic_rdists->has_vpend_valid_dirty) in its_wait_vpt_parse_complete()
4009 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) & in its_vpe_schedule()
4011 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; in its_vpe_schedule()
4018 val = virt_to_phys(page_address(vpe->vpt_page)) & in its_vpe_schedule()
4027 * easily. So in the end, vpe->pending_last is only an in its_vpe_schedule()
4034 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0; in its_vpe_schedule()
4046 vpe->idai = !!(val & GICR_VPENDBASER_IDAI); in its_vpe_deschedule()
4047 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); in its_vpe_deschedule()
4054 guard(raw_spinlock_irqsave)(&vpe->its_vm->vmapp_lock); in its_vpe_invall()
4060 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr]) in its_vpe_invall()
4077 switch (info->cmd_type) { in its_vpe_set_vcpu_affinity()
4095 return -EINVAL; in its_vpe_set_vcpu_affinity()
4107 cmd(vpe_proxy.dev, vpe->vpe_proxy_event); in its_vpe_send_cmd()
4116 if (gic_rdists->has_direct_lpi) in its_vpe_send_inv()
4117 __direct_lpi_inv(d, d->parent_data->hwirq); in its_vpe_send_inv()
4130 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); in its_vpe_mask_irq()
4137 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); in its_vpe_unmask_irq()
4148 return -EINVAL; in its_vpe_set_irqchip_state()
4150 if (gic_rdists->has_direct_lpi) { in its_vpe_set_irqchip_state()
4153 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; in its_vpe_set_irqchip_state()
4155 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR); in its_vpe_set_irqchip_state()
4157 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); in its_vpe_set_irqchip_state()
4176 .name = "GICv4-vpe",
4220 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); in its_vpe_4_1_mask_irq()
4226 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); in its_vpe_4_1_unmask_irq()
4238 val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0; in its_vpe_4_1_schedule()
4239 val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0; in its_vpe_4_1_schedule()
4240 val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id); in its_vpe_4_1_schedule()
4251 if (info->req_db) { in its_vpe_4_1_deschedule()
4255 * vPE is going to block: make the vPE non-resident with in its_vpe_4_1_deschedule()
4257 * we read-back PendingLast clear, then a doorbell will be in its_vpe_4_1_deschedule()
4264 raw_spin_lock_irqsave(&vpe->vpe_lock, flags); in its_vpe_4_1_deschedule()
4268 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); in its_vpe_4_1_deschedule()
4269 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags); in its_vpe_4_1_deschedule()
4272 * We're not blocking, so just make the vPE non-resident in its_vpe_4_1_deschedule()
4278 vpe->pending_last = true; in its_vpe_4_1_deschedule()
4298 switch (info->cmd_type) { in its_vpe_4_1_set_vcpu_affinity()
4316 return -EINVAL; in its_vpe_4_1_set_vcpu_affinity()
4321 .name = "GICv4.1-vpe",
4335 desc.its_vsgi_cmd.sgi = d->hwirq; in its_configure_sgi()
4336 desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority; in its_configure_sgi()
4337 desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled; in its_configure_sgi()
4338 desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group; in its_configure_sgi()
4353 vpe->sgi_config[d->hwirq].enabled = false; in its_sgi_mask_irq()
4361 vpe->sgi_config[d->hwirq].enabled = true; in its_sgi_unmask_irq()
4383 return -EINVAL; in its_sgi_set_irqchip_state()
4390 val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id); in its_sgi_set_irqchip_state()
4391 val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq); in its_sgi_set_irqchip_state()
4392 writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K); in its_sgi_set_irqchip_state()
4411 return -EINVAL; in its_sgi_get_irqchip_state()
4416 * - Concurrent vPE affinity change: we must make sure it cannot in its_sgi_get_irqchip_state()
4420 * - Concurrent VSGIPENDR access: As it involves accessing two in its_sgi_get_irqchip_state()
4424 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_sgi_get_irqchip_state()
4425 base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K; in its_sgi_get_irqchip_state()
4426 writel_relaxed(vpe->vpe_id, base + GICR_VSGIR); in its_sgi_get_irqchip_state()
4432 count--; in its_sgi_get_irqchip_state()
4442 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_sgi_get_irqchip_state()
4446 return -ENXIO; in its_sgi_get_irqchip_state()
4448 *val = !!(status & (1 << d->hwirq)); in its_sgi_get_irqchip_state()
4458 switch (info->cmd_type) { in its_sgi_set_vcpu_affinity()
4460 vpe->sgi_config[d->hwirq].priority = info->priority; in its_sgi_set_vcpu_affinity()
4461 vpe->sgi_config[d->hwirq].group = info->group; in its_sgi_set_vcpu_affinity()
4466 return -EINVAL; in its_sgi_set_vcpu_affinity()
4471 .name = "GICv4.1-sgi",
4491 vpe->sgi_config[i].priority = 0; in its_sgi_irq_domain_alloc()
4492 vpe->sgi_config[i].enabled = false; in its_sgi_irq_domain_alloc()
4493 vpe->sgi_config[i].group = false; in its_sgi_irq_domain_alloc()
4526 * - To change the configuration, CLEAR must be set to false, in its_sgi_irq_domain_deactivate()
4528 * - To clear the pending bit, CLEAR must be set to true, leaving in its_sgi_irq_domain_deactivate()
4533 vpe->sgi_config[d->hwirq].enabled = false; in its_sgi_irq_domain_deactivate()
4547 return ida_alloc_max(&its_vpeid_ida, ITS_MAX_VPEID - 1, GFP_KERNEL); in its_vpe_id_alloc()
4569 return -ENOMEM; in its_vpe_init()
4575 return -ENOMEM; in its_vpe_init()
4578 raw_spin_lock_init(&vpe->vpe_lock); in its_vpe_init()
4579 vpe->vpe_id = vpe_id; in its_vpe_init()
4580 vpe->vpt_page = vpt_page; in its_vpe_init()
4581 atomic_set(&vpe->vmapp_count, 0); in its_vpe_init()
4582 if (!gic_rdists->has_rvpeid) in its_vpe_init()
4583 vpe->vpe_proxy_event = -1; in its_vpe_init()
4591 its_vpe_id_free(vpe->vpe_id); in its_vpe_teardown()
4592 its_free_pending_table(vpe->vpt_page); in its_vpe_teardown()
4599 struct its_vm *vm = domain->host_data; in its_vpe_irq_domain_free()
4609 BUG_ON(vm != vpe->its_vm); in its_vpe_irq_domain_free()
4611 clear_bit(data->hwirq, vm->db_bitmap); in its_vpe_irq_domain_free()
4616 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) { in its_vpe_irq_domain_free()
4617 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis); in its_vpe_irq_domain_free()
4618 its_free_prop_table(vm->vprop_page); in its_vpe_irq_domain_free()
4633 return -ENOMEM; in its_vpe_irq_domain_alloc()
4637 return -ENOMEM; in its_vpe_irq_domain_alloc()
4643 return -ENOMEM; in its_vpe_irq_domain_alloc()
4646 vm->db_bitmap = bitmap; in its_vpe_irq_domain_alloc()
4647 vm->db_lpi_base = base; in its_vpe_irq_domain_alloc()
4648 vm->nr_db_lpis = nr_ids; in its_vpe_irq_domain_alloc()
4649 vm->vprop_page = vprop_page; in its_vpe_irq_domain_alloc()
4650 raw_spin_lock_init(&vm->vmapp_lock); in its_vpe_irq_domain_alloc()
4652 if (gic_rdists->has_rvpeid) in its_vpe_irq_domain_alloc()
4656 vm->vpes[i]->vpe_db_lpi = base + i; in its_vpe_irq_domain_alloc()
4657 err = its_vpe_init(vm->vpes[i]); in its_vpe_irq_domain_alloc()
4661 vm->vpes[i]->vpe_db_lpi); in its_vpe_irq_domain_alloc()
4665 irqchip, vm->vpes[i]); in its_vpe_irq_domain_alloc()
4683 vpe->col_idx = cpumask_first(cpu_online_mask); in its_vpe_irq_domain_activate()
4684 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); in its_vpe_irq_domain_activate()
4730 if (find_4_1_its() && !atomic_read(&vpe->vmapp_count)) in its_vpe_irq_domain_deactivate()
4731 gic_flush_dcache_to_poc(page_address(vpe->vpt_page), in its_vpe_irq_domain_deactivate()
4766 count--; in its_force_quiescent()
4768 return -EBUSY; in its_force_quiescent()
4780 its->typer &= ~GITS_TYPER_DEVBITS; in its_enable_quirk_cavium_22375()
4781 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1); in its_enable_quirk_cavium_22375()
4782 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; in its_enable_quirk_cavium_22375()
4791 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; in its_enable_quirk_cavium_23144()
4801 its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE; in its_enable_quirk_qdf2400_e0065()
4802 its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1); in its_enable_quirk_qdf2400_e0065()
4809 struct its_node *its = its_dev->its; in its_irq_get_msi_base_pre_its()
4812 * The Socionext Synquacer SoC has a so-called 'pre-ITS', in its_irq_get_msi_base_pre_its()
4813 * which maps 32-bit writes targeted at a separate window of in its_irq_get_msi_base_pre_its()
4816 * the window offset. in its_irq_get_msi_base_pre_its()
4818 return its->pre_its_base + (its_dev->device_id << 2); in its_irq_get_msi_base_pre_its()
4827 if (!fwnode_property_read_u32_array(its->fwnode_handle, in its_enable_quirk_socionext_synquacer()
4828 "socionext,synquacer-pre-its", in its_enable_quirk_socionext_synquacer()
4832 its->pre_its_base = pre_its_window[0]; in its_enable_quirk_socionext_synquacer()
4833 its->get_msi_base = its_irq_get_msi_base_pre_its; in its_enable_quirk_socionext_synquacer()
4835 ids = ilog2(pre_its_window[1]) - 2; in its_enable_quirk_socionext_synquacer()
4837 its->typer &= ~GITS_TYPER_DEVBITS; in its_enable_quirk_socionext_synquacer()
4838 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1); in its_enable_quirk_socionext_synquacer()
4841 /* the pre-ITS breaks isolation, so disable MSI remapping */ in its_enable_quirk_socionext_synquacer()
4842 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_ISOLATED_MSI; in its_enable_quirk_socionext_synquacer()
4856 its->vlpi_redist_offset = SZ_128K; in its_enable_quirk_hip07_161600802()
4868 its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE; in its_enable_rk3588001()
4869 gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE; in its_enable_rk3588001()
4878 its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE; in its_set_non_coherent()
4886 its->flags |= ITS_FLAGS_WORKAROUND_HISILICON_162100801; in its_enable_quirk_hip09_162100801()
4918 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4919 * implementation, but with a 'pre-ITS' added that requires
4922 .desc = "ITS: Socionext Synquacer pre-ITS",
4953 .desc = "ITS: non-coherent attribute",
4954 .property = "dma-noncoherent",
4963 u32 iidr = readl_relaxed(its->base + GITS_IIDR); in its_enable_quirks()
4967 if (is_of_node(its->fwnode_handle)) in its_enable_quirks()
4968 gic_enable_of_quirks(to_of_node(its->fwnode_handle), in its_enable_quirks()
4981 base = its->base; in its_save_disable()
4982 its->ctlr_save = readl_relaxed(base + GITS_CTLR); in its_save_disable()
4986 &its->phys_base, err); in its_save_disable()
4987 writel_relaxed(its->ctlr_save, base + GITS_CTLR); in its_save_disable()
4991 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER); in its_save_disable()
4999 base = its->base; in its_save_disable()
5000 writel_relaxed(its->ctlr_save, base + GITS_CTLR); in its_save_disable()
5018 base = its->base; in its_restore_enable()
5032 &its->phys_base, ret); in its_restore_enable()
5036 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER); in its_restore_enable()
5042 its->cmd_write = its->cmd_base; in its_restore_enable()
5047 struct its_baser *baser = &its->tables[i]; in its_restore_enable()
5049 if (!(baser->val & GITS_BASER_VALID)) in its_restore_enable()
5052 its_write_baser(its, baser, baser->val); in its_restore_enable()
5054 writel_relaxed(its->ctlr_save, base + GITS_CTLR); in its_restore_enable()
5061 if (its->collections[smp_processor_id()].col_id < in its_restore_enable()
5078 its_base = ioremap(res->start, SZ_64K); in its_map_one()
5080 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); in its_map_one()
5081 *err = -ENOMEM; in its_map_one()
5087 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); in its_map_one()
5088 *err = -ENODEV; in its_map_one()
5094 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); in its_map_one()
5112 return -ENOMEM; in its_init_domain()
5114 info->ops = &its_msi_domain_ops; in its_init_domain()
5115 info->data = its; in its_init_domain()
5118 its->msi_domain_flags, 0, in its_init_domain()
5119 its->fwnode_handle, &its_domain_ops, in its_init_domain()
5123 return -ENOMEM; in its_init_domain()
5128 inner_domain->msi_parent_ops = &gic_v3_its_msi_parent_ops; in its_init_domain()
5129 inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; in its_init_domain()
5140 if (gic_rdists->has_direct_lpi) { in its_init_vpe_domain()
5152 return -ENOMEM; in its_init_vpe_domain()
5155 devid = GENMASK(device_ids(its) - 1, 0); in its_init_vpe_domain()
5160 return -ENOMEM; in its_init_vpe_domain()
5163 BUG_ON(entries > vpe_proxy.dev->nr_ites); in its_init_vpe_domain()
5168 devid, vpe_proxy.dev->nr_ites); in its_init_vpe_domain()
5180 * guaranteed to be single-threaded, hence no in its_compute_its_list_map()
5187 &its->phys_base); in its_compute_its_list_map()
5188 return -EINVAL; in its_compute_its_list_map()
5191 ctlr = readl_relaxed(its->base + GITS_CTLR); in its_compute_its_list_map()
5194 writel_relaxed(ctlr, its->base + GITS_CTLR); in its_compute_its_list_map()
5195 ctlr = readl_relaxed(its->base + GITS_CTLR); in its_compute_its_list_map()
5203 &its->phys_base, its_number); in its_compute_its_list_map()
5204 return -EINVAL; in its_compute_its_list_map()
5220 if (!(its->typer & GITS_TYPER_VMOVP)) { in its_probe_one()
5225 its->list_nr = err; in its_probe_one()
5228 &its->phys_base, err); in its_probe_one()
5230 pr_info("ITS@%pa: Single VMOVP capable\n", &its->phys_base); in its_probe_one()
5234 u32 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer); in its_probe_one()
5236 its->sgir_base = ioremap(its->phys_base + SZ_128K, SZ_64K); in its_probe_one()
5237 if (!its->sgir_base) { in its_probe_one()
5238 err = -ENOMEM; in its_probe_one()
5242 its->mpidr = readl_relaxed(its->base + GITS_MPIDR); in its_probe_one()
5245 &its->phys_base, its->mpidr, svpet); in its_probe_one()
5249 page = its_alloc_pages_node(its->numa_node, in its_probe_one()
5253 err = -ENOMEM; in its_probe_one()
5256 its->cmd_base = (void *)page_address(page); in its_probe_one()
5257 its->cmd_write = its->cmd_base; in its_probe_one()
5267 baser = (virt_to_phys(its->cmd_base) | in its_probe_one()
5270 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | in its_probe_one()
5273 gits_write_cbaser(baser, its->base + GITS_CBASER); in its_probe_one()
5274 tmp = gits_read_cbaser(its->base + GITS_CBASER); in its_probe_one()
5276 if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) in its_probe_one()
5282 * The HW reports non-shareable, we must in its_probe_one()
5289 gits_write_cbaser(baser, its->base + GITS_CBASER); in its_probe_one()
5292 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; in its_probe_one()
5295 gits_write_cwriter(0, its->base + GITS_CWRITER); in its_probe_one()
5296 ctlr = readl_relaxed(its->base + GITS_CTLR); in its_probe_one()
5300 writel_relaxed(ctlr, its->base + GITS_CTLR); in its_probe_one()
5307 list_add(&its->entry, &its_nodes); in its_probe_one()
5315 its_free_pages(its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); in its_probe_one()
5317 if (its->sgir_base) in its_probe_one()
5318 iounmap(its->sgir_base); in its_probe_one()
5320 pr_err("ITS@%pa: failed probing (%d)\n", &its->phys_base, err); in its_probe_one()
5337 return -ENXIO; in redist_disable_lpis()
5346 * LPIs before trying to re-enable them. They are already in redist_disable_lpis()
5351 if ((gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED) || in redist_disable_lpis()
5352 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED)) in redist_disable_lpis()
5378 return -ETIMEDOUT; in redist_disable_lpis()
5381 timeout--; in redist_disable_lpis()
5391 return -EBUSY; in redist_disable_lpis()
5415 cpuhp_remove_state_nocalls(gic_rdists->cpuhp_memreserve_state); in rdist_memreserve_cpuhp_cleanup_workfn()
5416 gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID; in rdist_memreserve_cpuhp_cleanup_workfn()
5428 if (gic_data_rdist()->flags & RD_LOCAL_MEMRESERVE_DONE) in its_cpu_memreserve_lpi()
5431 pend_page = gic_data_rdist()->pend_page; in its_cpu_memreserve_lpi()
5433 ret = -ENOMEM; in its_cpu_memreserve_lpi()
5437 * If the pending table was pre-programmed, free the memory we in its_cpu_memreserve_lpi()
5441 if (gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED) { in its_cpu_memreserve_lpi()
5443 gic_data_rdist()->pend_page = NULL; in its_cpu_memreserve_lpi()
5455 gic_data_rdist()->flags |= RD_LOCAL_MEMRESERVE_DONE; in its_cpu_memreserve_lpi()
5477 { .compatible = "arm,gic-v3-its", },
5498 raw_spin_lock_init(&its->lock); in its_node_init()
5499 mutex_init(&its->dev_alloc_lock); in its_node_init()
5500 INIT_LIST_HEAD(&its->entry); in its_node_init()
5501 INIT_LIST_HEAD(&its->its_device_list); in its_node_init()
5503 its->typer = gic_read_typer(its_base + GITS_TYPER); in its_node_init()
5504 its->base = its_base; in its_node_init()
5505 its->phys_base = res->start; in its_node_init()
5506 its->get_msi_base = its_irq_get_msi_base; in its_node_init()
5507 its->msi_domain_flags = IRQ_DOMAIN_FLAG_ISOLATED_MSI; in its_node_init()
5509 its->numa_node = numa_node; in its_node_init()
5510 its->fwnode_handle = handle; in its_node_init()
5521 iounmap(its->base); in its_node_destroy()
5540 !of_property_read_bool(np, "msi-controller") || in its_of_probe()
5555 if (!of_property_read_bool(np, "msi-controller")) { in its_of_probe()
5556 pr_warn("%pOF: no msi-controller property, ITS ignored\n", in its_of_probe()
5567 its = its_node_init(&res, &np->fwnode, of_node_to_nid(np)); in its_of_probe()
5569 return -ENOMEM; in its_of_probe()
5620 return -EINVAL; in gic_acpi_parse_srat_its()
5622 if (its_affinity->header.length < sizeof(*its_affinity)) { in gic_acpi_parse_srat_its()
5624 its_affinity->header.length); in gic_acpi_parse_srat_its()
5625 return -EINVAL; in gic_acpi_parse_srat_its()
5633 node = pxm_to_node(its_affinity->proximity_domain); in gic_acpi_parse_srat_its()
5641 its_srat_maps[its_in_srat].its_id = its_affinity->its_id; in gic_acpi_parse_srat_its()
5643 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n", in gic_acpi_parse_srat_its()
5644 its_affinity->proximity_domain, its_affinity->its_id, node); in gic_acpi_parse_srat_its()
5693 res.start = its_entry->base_address; in gic_acpi_parse_madt_its()
5694 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; in gic_acpi_parse_madt_its()
5701 return -ENOMEM; in gic_acpi_parse_madt_its()
5704 err = iort_register_domain_token(its_entry->translation_id, res.start, in gic_acpi_parse_madt_its()
5708 &res.start, its_entry->translation_id); in gic_acpi_parse_madt_its()
5713 acpi_get_its_numa_node(its_entry->translation_id)); in gic_acpi_parse_madt_its()
5715 err = -ENOMEM; in gic_acpi_parse_madt_its()
5720 (its_entry->flags & ACPI_MADT_ITS_NON_COHERENT)) in gic_acpi_parse_madt_its()
5721 its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE; in gic_acpi_parse_madt_its()
5728 iort_deregister_domain_token(its_entry->translation_id); in gic_acpi_parse_madt_its()
5742 .start = its_entry->base_address, in its_acpi_reset()
5743 .end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1, in its_acpi_reset()
5779 gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID; in its_lpi_memreserve_init()
5787 gic_rdists->cpuhp_memreserve_state = state; in its_lpi_memreserve_init()
5801 itt_pool = gen_pool_create(get_order(ITS_ITT_ALIGN), -1); in its_init()
5803 return -ENOMEM; in its_init()
5817 return -ENXIO; in its_init()
5830 if (WARN_ON(!has_v4_1 && rdists->has_rvpeid)) in its_init()
5831 rdists->has_rvpeid = false; in its_init()
5833 if (has_v4 & rdists->has_vlpis) { in its_init()
5843 rdists->has_vlpis = false; in its_init()