89 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_mask()  local
96 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_mask()
97 	irq_reg_writel(gc, 1, AT91_AIC5_IDCR);  in aic5_mask()
98 	gc->mask_cache &= ~d->mask;  in aic5_mask()
105 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_unmask()  local
112 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_unmask()
113 	irq_reg_writel(gc, 1, AT91_AIC5_IECR);  in aic5_unmask()
114 	gc->mask_cache |= d->mask;  in aic5_unmask()
151 	struct irq_domain_chip_generic *dgc = domain->gc;  in aic5_suspend()
153 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_suspend()  local
166 		if ((mask & gc->mask_cache) == (mask & gc->wake_active))  in aic5_suspend()
169 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_suspend()
170 		if (mask & gc->wake_active)  in aic5_suspend()
180 	struct irq_domain_chip_generic *dgc = domain->gc;  in aic5_resume()
182 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_resume()  local
201 		    ((mask & gc->mask_cache) == (mask & gc->wake_active)))  in aic5_resume()
204 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_resume()
205 		if (mask & gc->mask_cache)  in aic5_resume()
215 	struct irq_domain_chip_generic *dgc = domain->gc;  in aic5_pm_shutdown()
217 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_pm_shutdown()  local
222 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_pm_shutdown()
235 	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);  in aic5_hw_init()  local
243 		irq_reg_writel(gc, 0, AT91_AIC5_EOICR);  in aic5_hw_init()
250 	irq_reg_writel(gc, 0xffffffff, AT91_AIC5_SPU);  in aic5_hw_init()
253 	irq_reg_writel(gc, 0, AT91_AIC5_DCR);  in aic5_hw_init()
257 		irq_reg_writel(gc, i, AT91_AIC5_SSR);  in aic5_hw_init()
258 		irq_reg_writel(gc, i, AT91_AIC5_SVR);  in aic5_hw_init()
259 		irq_reg_writel(gc, 1, AT91_AIC5_IDCR);  in aic5_hw_init()
260 		irq_reg_writel(gc, 1, AT91_AIC5_ICCR);  in aic5_hw_init()
318 	struct irq_chip_generic *gc;  in aic5_of_init()  local
337 		gc = irq_get_domain_generic_chip(domain, i * 32);  in aic5_of_init()
339 		gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR;  in aic5_of_init()
340 		gc->chip_types[0].chip.irq_mask = aic5_mask;  in aic5_of_init()
341 		gc->chip_types[0].chip.irq_unmask = aic5_unmask;  in aic5_of_init()
342 		gc->chip_types[0].chip.irq_retrigger = aic5_retrigger;  in aic5_of_init()
343 		gc->chip_types[0].chip.irq_set_type = aic5_set_type;  in aic5_of_init()
344 		gc->chip_types[0].chip.irq_suspend = aic5_suspend;  in aic5_of_init()
345 		gc->chip_types[0].chip.irq_resume = aic5_resume;  in aic5_of_init()
346 		gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown;  in aic5_of_init()