1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Aspeed AST24XX, AST25XX, AST26XX, and AST27XX SCU Interrupt Controller
41 	SCU_VARIANT("aspeed,ast2400-scu-ic",	0, GENMASK(15, 0),	7, 0x00, 0x00),
42 	SCU_VARIANT("aspeed,ast2500-scu-ic",	0, GENMASK(15, 0),	7, 0x00, 0x00),
43 	SCU_VARIANT("aspeed,ast2600-scu-ic0",	0, GENMASK(5, 0),	6, 0x00, 0x00),
44 	SCU_VARIANT("aspeed,ast2600-scu-ic1",	4, GENMASK(5, 4),	2, 0x00, 0x00),
45 	SCU_VARIANT("aspeed,ast2700-scu-ic0",	0, GENMASK(3, 0),	4, 0x00, 0x04),
46 	SCU_VARIANT("aspeed,ast2700-scu-ic1",	0, GENMASK(3, 0),	4, 0x00, 0x04),
47 	SCU_VARIANT("aspeed,ast2700-scu-ic2",	0, GENMASK(3, 0),	4, 0x04, 0x00),
48 	SCU_VARIANT("aspeed,ast2700-scu-ic3",	0, GENMASK(1, 0),	2, 0x04, 0x00),
61 static inline bool scu_has_split_isr(struct aspeed_scu_ic *scu)  in scu_has_split_isr()  argument
63 	return scu->ier != scu->isr;  in scu_has_split_isr()
75 	mask = scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT;  in aspeed_scu_ic_irq_handler_combined()
77 	 * The SCU IC has just one register to control its operation and read  in aspeed_scu_ic_irq_handler_combined()
86 	sts = readl(scu_ic->base);  in aspeed_scu_ic_irq_handler_combined()
87 	enabled = sts & scu_ic->irq_enable;  in aspeed_scu_ic_irq_handler_combined()
90 	bit = scu_ic->irq_shift;  in aspeed_scu_ic_irq_handler_combined()
91 	max = scu_ic->num_irqs + bit;  in aspeed_scu_ic_irq_handler_combined()
94 		generic_handle_domain_irq(scu_ic->irq_domain, bit - scu_ic->irq_shift);  in aspeed_scu_ic_irq_handler_combined()
95 		writel((readl(scu_ic->base) & ~mask) | BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT),  in aspeed_scu_ic_irq_handler_combined()
96 		       scu_ic->base);  in aspeed_scu_ic_irq_handler_combined()
111 	mask = scu_ic->irq_enable;  in aspeed_scu_ic_irq_handler_split()
112 	sts = readl(scu_ic->base + scu_ic->isr);  in aspeed_scu_ic_irq_handler_split()
113 	enabled = sts & scu_ic->irq_enable;  in aspeed_scu_ic_irq_handler_split()
114 	sts = readl(scu_ic->base + scu_ic->isr);  in aspeed_scu_ic_irq_handler_split()
117 	bit = scu_ic->irq_shift;  in aspeed_scu_ic_irq_handler_split()
118 	max = scu_ic->num_irqs + bit;  in aspeed_scu_ic_irq_handler_split()
121 		generic_handle_domain_irq(scu_ic->irq_domain, bit - scu_ic->irq_shift);  in aspeed_scu_ic_irq_handler_split()
123 		writel(BIT(bit), scu_ic->base + scu_ic->isr);  in aspeed_scu_ic_irq_handler_split()
132 	unsigned int bit = BIT(data->hwirq + scu_ic->irq_shift);  in aspeed_scu_ic_irq_mask_combined()
133 	unsigned int mask = bit | (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);  in aspeed_scu_ic_irq_mask_combined()
140 	writel(readl(scu_ic->base) & ~mask, scu_ic->base);  in aspeed_scu_ic_irq_mask_combined()
146 	unsigned int bit = BIT(data->hwirq + scu_ic->irq_shift);  in aspeed_scu_ic_irq_unmask_combined()
147 	unsigned int mask = bit | (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);  in aspeed_scu_ic_irq_unmask_combined()
154 	writel((readl(scu_ic->base) & ~mask) | bit, scu_ic->base);  in aspeed_scu_ic_irq_unmask_combined()
160 	unsigned int mask = BIT(data->hwirq + scu_ic->irq_shift);  in aspeed_scu_ic_irq_mask_split()
162 	writel(readl(scu_ic->base) & ~mask, scu_ic->base + scu_ic->ier);  in aspeed_scu_ic_irq_mask_split()
168 	unsigned int bit = BIT(data->hwirq + scu_ic->irq_shift);  in aspeed_scu_ic_irq_unmask_split()
170 	writel(readl(scu_ic->base) | bit, scu_ic->base + scu_ic->ier);  in aspeed_scu_ic_irq_unmask_split()
177 	return -EINVAL;  in aspeed_scu_ic_irq_set_affinity()
181 	.name			= "aspeed-scu-ic",
188 	.name			= "ast2700-scu-ic",
197 	struct aspeed_scu_ic *scu_ic = domain->host_data;  in aspeed_scu_ic_map()
203 	irq_set_chip_data(irq, domain->host_data);  in aspeed_scu_ic_map()
217 	scu_ic->base = of_iomap(node, 0);  in aspeed_scu_ic_of_init_common()
218 	if (!scu_ic->base) {  in aspeed_scu_ic_of_init_common()
219 		rc = -ENOMEM;  in aspeed_scu_ic_of_init_common()
224 		writel(AST2700_SCU_IC_STATUS, scu_ic->base + scu_ic->isr);  in aspeed_scu_ic_of_init_common()
225 		writel(0, scu_ic->base + scu_ic->ier);  in aspeed_scu_ic_of_init_common()
227 		writel(ASPEED_SCU_IC_STATUS, scu_ic->base);  in aspeed_scu_ic_of_init_common()
228 		writel(0, scu_ic->base);  in aspeed_scu_ic_of_init_common()
233 		rc = -EINVAL;  in aspeed_scu_ic_of_init_common()
237 	scu_ic->irq_domain = irq_domain_create_linear(of_fwnode_handle(node), scu_ic->num_irqs,  in aspeed_scu_ic_of_init_common()
239 	if (!scu_ic->irq_domain) {  in aspeed_scu_ic_of_init_common()
240 		rc = -ENOMEM;  in aspeed_scu_ic_of_init_common()
272 		return -ENODEV;  in aspeed_scu_ic_of_init()
276 		return -ENOMEM;  in aspeed_scu_ic_of_init()
278 	scu_ic->irq_enable	= variant->irq_enable;  in aspeed_scu_ic_of_init()
279 	scu_ic->irq_shift	= variant->irq_shift;  in aspeed_scu_ic_of_init()
280 	scu_ic->num_irqs	= variant->num_irqs;  in aspeed_scu_ic_of_init()
281 	scu_ic->ier		= variant->ier;  in aspeed_scu_ic_of_init()
282 	scu_ic->isr		= variant->isr;  in aspeed_scu_ic_of_init()
287 IRQCHIP_DECLARE(ast2400_scu_ic, "aspeed,ast2400-scu-ic", aspeed_scu_ic_of_init);
288 IRQCHIP_DECLARE(ast2500_scu_ic, "aspeed,ast2500-scu-ic", aspeed_scu_ic_of_init);
289 IRQCHIP_DECLARE(ast2600_scu_ic0, "aspeed,ast2600-scu-ic0", aspeed_scu_ic_of_init);
290 IRQCHIP_DECLARE(ast2600_scu_ic1, "aspeed,ast2600-scu-ic1", aspeed_scu_ic_of_init);
291 IRQCHIP_DECLARE(ast2700_scu_ic0, "aspeed,ast2700-scu-ic0", aspeed_scu_ic_of_init);
292 IRQCHIP_DECLARE(ast2700_scu_ic1, "aspeed,ast2700-scu-ic1", aspeed_scu_ic_of_init);
293 IRQCHIP_DECLARE(ast2700_scu_ic2, "aspeed,ast2700-scu-ic2", aspeed_scu_ic_of_init);
294 IRQCHIP_DECLARE(ast2700_scu_ic3, "aspeed,ast2700-scu-ic3", aspeed_scu_ic_of_init);