Lines Matching +full:mt8192 +full:- +full:pcie
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
6 #include <linux/arm-smccc.h>
17 #include <linux/io-pgtable.h>
35 #include <dt-bindings/memory/mtk-memory-port.h>
151 ((((pdata)->flags) & (mask)) == (_x))
207 * is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the
209 * 0x40000000-0x44000000.
271 * In the sharing pgtable case, list data->list to the global list like m4ulist.
272 * In the non-sharing pgtable case, list data->list to the itself hw_list_head.
294 return component_bind_all(dev, &data->larb_imu); in mtk_iommu_bind()
301 component_unbind_all(dev, &data->larb_imu); in mtk_iommu_unbind()
320 * |---A---|---B---|---C---|---D---|---E---|
321 * +--I/O--+------------Memory-------------+
327 * |---E---|---B---|---C---|---D---|
328 * +------------Memory-------------+
341 #define MTK_IOMMU_IOVA_SZ_4G (SZ_4G - SZ_8M) /* 8M as gap */
378 struct mtk_iommu_bank_data *bank = &data->bank[0]; in mtk_iommu_tlb_flush_all()
379 void __iomem *base = bank->base; in mtk_iommu_tlb_flush_all()
382 spin_lock_irqsave(&bank->tlb_lock, flags); in mtk_iommu_tlb_flush_all()
383 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg); in mtk_iommu_tlb_flush_all()
386 spin_unlock_irqrestore(&bank->tlb_lock, flags); in mtk_iommu_tlb_flush_all()
392 struct list_head *head = bank->parent_data->hw_list; in mtk_iommu_tlb_flush_range_sync()
417 check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO); in mtk_iommu_tlb_flush_range_sync()
420 if (pm_runtime_get_if_in_use(data->dev) <= 0) in mtk_iommu_tlb_flush_range_sync()
424 curbank = &data->bank[bank->id]; in mtk_iommu_tlb_flush_range_sync()
425 base = curbank->base; in mtk_iommu_tlb_flush_range_sync()
427 spin_lock_irqsave(&curbank->tlb_lock, flags); in mtk_iommu_tlb_flush_range_sync()
429 base + data->plat_data->inv_sel_reg); in mtk_iommu_tlb_flush_range_sync()
432 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), in mtk_iommu_tlb_flush_range_sync()
442 spin_unlock_irqrestore(&curbank->tlb_lock, flags); in mtk_iommu_tlb_flush_range_sync()
445 dev_warn(data->dev, in mtk_iommu_tlb_flush_range_sync()
451 pm_runtime_put(data->dev); in mtk_iommu_tlb_flush_range_sync()
458 struct mtk_iommu_data *data = bank->parent_data; in mtk_iommu_isr()
459 struct mtk_iommu_domain *dom = bank->m4u_dom; in mtk_iommu_isr()
462 const struct mtk_iommu_plat_data *plat_data = data->plat_data; in mtk_iommu_isr()
463 void __iomem *base = bank->base; in mtk_iommu_isr()
504 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; in mtk_iommu_isr()
507 if (!dom || report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova, in mtk_iommu_isr()
510 bank->parent_dev, in mtk_iommu_isr()
532 if (plat_data->banks_num == 1) in mtk_iommu_get_bank_id()
535 for (i = 0; i < fwspec->num_ids; i++) in mtk_iommu_get_bank_id()
536 portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); in mtk_iommu_get_bank_id()
538 for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) { in mtk_iommu_get_bank_id()
539 if (!plat_data->banks_enable[i]) in mtk_iommu_get_bank_id()
542 if (portmsk & plat_data->banks_portmsk[i]) { in mtk_iommu_get_bank_id()
558 if (plat_data->iova_region_nr == 1) in mtk_iommu_get_iova_region_id()
561 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); in mtk_iommu_get_iova_region_id()
562 for (i = 0; i < fwspec->num_ids; i++) in mtk_iommu_get_iova_region_id()
563 portidmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); in mtk_iommu_get_iova_region_id()
565 for (i = 0; i < plat_data->iova_region_nr; i++) { in mtk_iommu_get_iova_region_id()
566 rgn_larb_msk = plat_data->iova_region_larb_msk[i]; in mtk_iommu_get_iova_region_id()
574 dev_err(dev, "Can NOT find the region for larb(%d-%x).\n", in mtk_iommu_get_iova_region_id()
576 return -EINVAL; in mtk_iommu_get_iova_region_id()
590 for (i = 0; i < fwspec->num_ids; ++i) { in mtk_iommu_config()
591 portid = MTK_M4U_TO_PORT(fwspec->ids[i]); in mtk_iommu_config()
595 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { in mtk_iommu_config()
597 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); in mtk_iommu_config()
598 larb_mmu = &data->larb_imu[larbid]; in mtk_iommu_config()
599 region = data->plat_data->iova_region + regionid; in mtk_iommu_config()
602 larb_mmu->bank[portid] = upper_32_bits(region->iova_base); in mtk_iommu_config()
604 dev_dbg(dev, "%s iommu for larb(%s) port 0x%lx region %d rgn-bank %d.\n", in mtk_iommu_config()
605 enable ? "enable" : "disable", dev_name(larb_mmu->dev), in mtk_iommu_config()
606 portid_msk, regionid, upper_32_bits(region->iova_base)); in mtk_iommu_config()
609 larb_mmu->mmu |= portid_msk; in mtk_iommu_config()
611 larb_mmu->mmu &= ~portid_msk; in mtk_iommu_config()
612 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { in mtk_iommu_config()
613 if (MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) { in mtk_iommu_config()
619 /* PCI dev has only one output id, enable the next writing bit for PCIe */ in mtk_iommu_config()
621 if (fwspec->num_ids != 1) { in mtk_iommu_config()
623 return -ENODEV; in mtk_iommu_config()
628 ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, in mtk_iommu_config()
634 dev_name(data->dev), portid_msk, ret); in mtk_iommu_config()
643 struct mtk_iommu_domain *share_dom = data->share_dom; in mtk_iommu_domain_finalise()
648 dom->iop = share_dom->iop; in mtk_iommu_domain_finalise()
649 dom->cfg = share_dom->cfg; in mtk_iommu_domain_finalise()
650 dom->domain.pgsize_bitmap = share_dom->cfg.pgsize_bitmap; in mtk_iommu_domain_finalise()
654 dom->cfg = (struct io_pgtable_cfg) { in mtk_iommu_domain_finalise()
659 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, in mtk_iommu_domain_finalise()
660 .iommu_dev = data->dev, in mtk_iommu_domain_finalise()
663 if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) in mtk_iommu_domain_finalise()
664 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT; in mtk_iommu_domain_finalise()
666 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) in mtk_iommu_domain_finalise()
667 dom->cfg.oas = data->enable_4GB ? 33 : 32; in mtk_iommu_domain_finalise()
669 dom->cfg.oas = 35; in mtk_iommu_domain_finalise()
671 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); in mtk_iommu_domain_finalise()
672 if (!dom->iop) { in mtk_iommu_domain_finalise()
673 dev_err(data->dev, "Failed to alloc io pgtable\n"); in mtk_iommu_domain_finalise()
674 return -ENOMEM; in mtk_iommu_domain_finalise()
678 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; in mtk_iommu_domain_finalise()
680 data->share_dom = dom; in mtk_iommu_domain_finalise()
684 region = data->plat_data->iova_region + region_id; in mtk_iommu_domain_finalise()
685 dom->domain.geometry.aperture_start = region->iova_base; in mtk_iommu_domain_finalise()
686 dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; in mtk_iommu_domain_finalise()
687 dom->domain.geometry.force_aperture = true; in mtk_iommu_domain_finalise()
698 mutex_init(&dom->mutex); in mtk_iommu_domain_alloc_paging()
700 return &dom->domain; in mtk_iommu_domain_alloc_paging()
713 struct list_head *hw_list = data->hw_list; in mtk_iommu_attach_device()
714 struct device *m4udev = data->dev; in mtk_iommu_attach_device()
719 region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data); in mtk_iommu_attach_device()
723 bankid = mtk_iommu_get_bank_id(dev, data->plat_data); in mtk_iommu_attach_device()
724 mutex_lock(&dom->mutex); in mtk_iommu_attach_device()
725 if (!dom->bank) { in mtk_iommu_attach_device()
729 mutex_lock(&frstdata->mutex); in mtk_iommu_attach_device()
731 mutex_unlock(&frstdata->mutex); in mtk_iommu_attach_device()
733 mutex_unlock(&dom->mutex); in mtk_iommu_attach_device()
736 dom->bank = &data->bank[bankid]; in mtk_iommu_attach_device()
738 mutex_unlock(&dom->mutex); in mtk_iommu_attach_device()
740 mutex_lock(&data->mutex); in mtk_iommu_attach_device()
741 bank = &data->bank[bankid]; in mtk_iommu_attach_device()
742 if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */ in mtk_iommu_attach_device()
754 bank->m4u_dom = dom; in mtk_iommu_attach_device()
755 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_attach_device()
759 mutex_unlock(&data->mutex); in mtk_iommu_attach_device()
772 mutex_unlock(&data->mutex); in mtk_iommu_attach_device()
805 if (dom->bank->parent_data->enable_4GB) in mtk_iommu_map()
809 return dom->iop->map_pages(dom->iop, iova, paddr, pgsize, pgcount, prot, gfp, mapped); in mtk_iommu_map()
819 return dom->iop->unmap_pages(dom->iop, iova, pgsize, pgcount, gather); in mtk_iommu_unmap()
826 if (dom->bank) in mtk_iommu_flush_iotlb_all()
827 mtk_iommu_tlb_flush_all(dom->bank->parent_data); in mtk_iommu_flush_iotlb_all()
834 size_t length = gather->end - gather->start + 1; in mtk_iommu_iotlb_sync()
836 mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank); in mtk_iommu_iotlb_sync()
844 mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank); in mtk_iommu_sync_map()
854 pa = dom->iop->iova_to_phys(dom->iop, iova); in mtk_iommu_iova_to_phys()
856 dom->bank->parent_data->enable_4GB && in mtk_iommu_iova_to_phys()
871 if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) in mtk_iommu_probe_device()
872 return &data->iommu; in mtk_iommu_probe_device()
875 * Link the consumer device with the smi-larb device(supplier). in mtk_iommu_probe_device()
879 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); in mtk_iommu_probe_device()
881 return ERR_PTR(-EINVAL); in mtk_iommu_probe_device()
883 for (i = 1; i < fwspec->num_ids; i++) { in mtk_iommu_probe_device()
884 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); in mtk_iommu_probe_device()
886 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", in mtk_iommu_probe_device()
888 return ERR_PTR(-EINVAL); in mtk_iommu_probe_device()
891 larbdev = data->larb_imu[larbid].dev; in mtk_iommu_probe_device()
893 return ERR_PTR(-EINVAL); in mtk_iommu_probe_device()
899 return &data->iommu; in mtk_iommu_probe_device()
910 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { in mtk_iommu_release_device()
911 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); in mtk_iommu_release_device()
912 larbdev = data->larb_imu[larbid].dev; in mtk_iommu_release_device()
935 struct list_head *hw_list = c_data->hw_list; in mtk_iommu_device_group()
941 return ERR_PTR(-ENODEV); in mtk_iommu_device_group()
943 groupid = mtk_iommu_get_group_id(dev, data->plat_data); in mtk_iommu_device_group()
947 mutex_lock(&data->mutex); in mtk_iommu_device_group()
948 group = data->m4u_group[groupid]; in mtk_iommu_device_group()
952 data->m4u_group[groupid] = group; in mtk_iommu_device_group()
956 mutex_unlock(&data->mutex); in mtk_iommu_device_group()
965 if (args->args_count != 1) { in mtk_iommu_of_xlate()
966 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", in mtk_iommu_of_xlate()
967 args->args_count); in mtk_iommu_of_xlate()
968 return -EINVAL; in mtk_iommu_of_xlate()
973 m4updev = of_find_device_by_node(args->np); in mtk_iommu_of_xlate()
975 return -EINVAL; in mtk_iommu_of_xlate()
980 return iommu_fwspec_add_ids(dev, args->args, 1); in mtk_iommu_of_xlate()
987 unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i; in mtk_iommu_get_resv_regions()
994 curdom = data->plat_data->iova_region + regionid; in mtk_iommu_get_resv_regions()
995 for (i = 0; i < data->plat_data->iova_region_nr; i++) { in mtk_iommu_get_resv_regions()
996 resv = data->plat_data->iova_region + i; in mtk_iommu_get_resv_regions()
999 if (resv->iova_base <= curdom->iova_base || in mtk_iommu_get_resv_regions()
1000 resv->iova_base + resv->size >= curdom->iova_base + curdom->size) in mtk_iommu_get_resv_regions()
1003 region = iommu_alloc_resv_region(resv->iova_base, resv->size, in mtk_iommu_get_resv_regions()
1009 list_add_tail(®ion->list, head); in mtk_iommu_get_resv_regions()
1037 const struct mtk_iommu_bank_data *bankx = &data->bank[bankid]; in mtk_iommu_hw_init()
1038 const struct mtk_iommu_bank_data *bank0 = &data->bank[0]; in mtk_iommu_hw_init()
1042 * Global control settings are in bank0. May re-init these global registers in mtk_iommu_hw_init()
1045 if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) { in mtk_iommu_hw_init()
1049 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG); in mtk_iommu_hw_init()
1052 writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG); in mtk_iommu_hw_init()
1054 if (data->enable_4GB && in mtk_iommu_hw_init()
1055 MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { in mtk_iommu_hw_init()
1061 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG); in mtk_iommu_hw_init()
1063 if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE)) in mtk_iommu_hw_init()
1064 writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS); in mtk_iommu_hw_init()
1066 writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS); in mtk_iommu_hw_init()
1068 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { in mtk_iommu_hw_init()
1070 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_hw_init()
1072 writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_hw_init()
1075 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { in mtk_iommu_hw_init()
1079 regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL); in mtk_iommu_hw_init()
1080 if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE)) in mtk_iommu_hw_init()
1082 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) in mtk_iommu_hw_init()
1085 writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL); in mtk_iommu_hw_init()
1094 writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0); in mtk_iommu_hw_init()
1103 writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL); in mtk_iommu_hw_init()
1105 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) in mtk_iommu_hw_init()
1106 regval = (data->protect_base >> 1) | (data->enable_4GB << 31); in mtk_iommu_hw_init()
1108 regval = lower_32_bits(data->protect_base) | in mtk_iommu_hw_init()
1109 upper_32_bits(data->protect_base); in mtk_iommu_hw_init()
1110 writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR); in mtk_iommu_hw_init()
1112 if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0, in mtk_iommu_hw_init()
1113 dev_name(bankx->parent_dev), (void *)bankx)) { in mtk_iommu_hw_init()
1114 writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_hw_init()
1115 dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq); in mtk_iommu_hw_init()
1116 return -ENODEV; in mtk_iommu_hw_init()
1135 larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL); in mtk_iommu_mm_dts_parse()
1139 return -EINVAL; in mtk_iommu_mm_dts_parse()
1145 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); in mtk_iommu_mm_dts_parse()
1147 ret = -EINVAL; in mtk_iommu_mm_dts_parse()
1156 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); in mtk_iommu_mm_dts_parse()
1161 ret = -EINVAL; in mtk_iommu_mm_dts_parse()
1168 ret = -ENODEV; in mtk_iommu_mm_dts_parse()
1171 if (data->larb_imu[id].dev) { in mtk_iommu_mm_dts_parse()
1173 ret = -EEXIST; in mtk_iommu_mm_dts_parse()
1176 data->larb_imu[id].dev = &plarbdev->dev; in mtk_iommu_mm_dts_parse()
1178 if (!plarbdev->dev.driver) { in mtk_iommu_mm_dts_parse()
1179 ret = -EPROBE_DEFER; in mtk_iommu_mm_dts_parse()
1183 /* Get smi-(sub)-common dev from the last larb. */ in mtk_iommu_mm_dts_parse()
1186 ret = -EINVAL; in mtk_iommu_mm_dts_parse()
1191 * It may have two level smi-common. the node is smi-sub-common if it in mtk_iommu_mm_dts_parse()
1192 * has a new mediatek,smi property. otherwise it is smi-commmon. in mtk_iommu_mm_dts_parse()
1202 * smi-common. in mtk_iommu_mm_dts_parse()
1209 ret = -EINVAL; in mtk_iommu_mm_dts_parse()
1215 component_match_add(dev, match, component_compare_dev, &plarbdev->dev); in mtk_iommu_mm_dts_parse()
1220 return -EINVAL; in mtk_iommu_mm_dts_parse()
1225 return -ENODEV; in mtk_iommu_mm_dts_parse()
1226 data->smicomm_dev = &pcommdev->dev; in mtk_iommu_mm_dts_parse()
1228 link = device_link_add(data->smicomm_dev, dev, in mtk_iommu_mm_dts_parse()
1232 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); in mtk_iommu_mm_dts_parse()
1233 return -EINVAL; in mtk_iommu_mm_dts_parse()
1238 for (i = MTK_LARB_NR_MAX - 1; i >= 0; i--) { in mtk_iommu_mm_dts_parse()
1239 if (!data->larb_imu[i].dev) in mtk_iommu_mm_dts_parse()
1241 put_device(data->larb_imu[i].dev); in mtk_iommu_mm_dts_parse()
1249 struct device *dev = &pdev->dev; in mtk_iommu_probe()
1263 return -ENOMEM; in mtk_iommu_probe()
1264 data->dev = dev; in mtk_iommu_probe()
1265 data->plat_data = of_device_get_match_data(dev); in mtk_iommu_probe()
1270 return -ENOMEM; in mtk_iommu_probe()
1271 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); in mtk_iommu_probe()
1273 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { in mtk_iommu_probe()
1274 infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg"); in mtk_iommu_probe()
1284 switch (data->plat_data->m4u_plat) { in mtk_iommu_probe()
1286 p = "mediatek,mt2712-infracfg"; in mtk_iommu_probe()
1289 p = "mediatek,mt8173-infracfg"; in mtk_iommu_probe()
1303 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); in mtk_iommu_probe()
1306 banks_num = data->plat_data->banks_num; in mtk_iommu_probe()
1309 return -EINVAL; in mtk_iommu_probe()
1312 return -EINVAL; in mtk_iommu_probe()
1317 ioaddr = res->start; in mtk_iommu_probe()
1319 data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL); in mtk_iommu_probe()
1320 if (!data->bank) in mtk_iommu_probe()
1321 return -ENOMEM; in mtk_iommu_probe()
1324 if (!data->plat_data->banks_enable[i]) in mtk_iommu_probe()
1326 bank = &data->bank[i]; in mtk_iommu_probe()
1327 bank->id = i; in mtk_iommu_probe()
1328 bank->base = base + i * MTK_IOMMU_BANK_SZ; in mtk_iommu_probe()
1329 bank->m4u_dom = NULL; in mtk_iommu_probe()
1331 bank->irq = platform_get_irq(pdev, i); in mtk_iommu_probe()
1332 if (bank->irq < 0) in mtk_iommu_probe()
1333 return bank->irq; in mtk_iommu_probe()
1334 bank->parent_dev = dev; in mtk_iommu_probe()
1335 bank->parent_data = data; in mtk_iommu_probe()
1336 spin_lock_init(&bank->tlb_lock); in mtk_iommu_probe()
1339 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { in mtk_iommu_probe()
1340 data->bclk = devm_clk_get(dev, "bclk"); in mtk_iommu_probe()
1341 if (IS_ERR(data->bclk)) in mtk_iommu_probe()
1342 return PTR_ERR(data->bclk); in mtk_iommu_probe()
1345 if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) { in mtk_iommu_probe()
1355 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { in mtk_iommu_probe()
1361 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && in mtk_iommu_probe()
1362 !MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) { in mtk_iommu_probe()
1363 p = data->plat_data->pericfg_comp_str; in mtk_iommu_probe()
1364 data->pericfg = syscon_regmap_lookup_by_compatible(p); in mtk_iommu_probe()
1365 if (IS_ERR(data->pericfg)) { in mtk_iommu_probe()
1366 ret = PTR_ERR(data->pericfg); in mtk_iommu_probe()
1372 mutex_init(&data->mutex); in mtk_iommu_probe()
1374 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, in mtk_iommu_probe()
1375 "mtk-iommu.%pa", &ioaddr); in mtk_iommu_probe()
1379 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); in mtk_iommu_probe()
1383 if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) { in mtk_iommu_probe()
1384 list_add_tail(&data->list, data->plat_data->hw_list); in mtk_iommu_probe()
1385 data->hw_list = data->plat_data->hw_list; in mtk_iommu_probe()
1387 INIT_LIST_HEAD(&data->hw_list_head); in mtk_iommu_probe()
1388 list_add_tail(&data->list, &data->hw_list_head); in mtk_iommu_probe()
1389 data->hw_list = &data->hw_list_head; in mtk_iommu_probe()
1392 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { in mtk_iommu_probe()
1400 list_del(&data->list); in mtk_iommu_probe()
1401 iommu_device_unregister(&data->iommu); in mtk_iommu_probe()
1403 iommu_device_sysfs_remove(&data->iommu); in mtk_iommu_probe()
1405 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) in mtk_iommu_probe()
1406 device_link_remove(data->smicomm_dev, dev); in mtk_iommu_probe()
1418 iommu_device_sysfs_remove(&data->iommu); in mtk_iommu_remove()
1419 iommu_device_unregister(&data->iommu); in mtk_iommu_remove()
1421 list_del(&data->list); in mtk_iommu_remove()
1423 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { in mtk_iommu_remove()
1424 device_link_remove(data->smicomm_dev, &pdev->dev); in mtk_iommu_remove()
1425 component_master_del(&pdev->dev, &mtk_iommu_com_ops); in mtk_iommu_remove()
1427 pm_runtime_disable(&pdev->dev); in mtk_iommu_remove()
1428 for (i = 0; i < data->plat_data->banks_num; i++) { in mtk_iommu_remove()
1429 bank = &data->bank[i]; in mtk_iommu_remove()
1430 if (!bank->m4u_dom) in mtk_iommu_remove()
1432 devm_free_irq(&pdev->dev, bank->irq, bank); in mtk_iommu_remove()
1439 struct mtk_iommu_suspend_reg *reg = &data->reg; in mtk_iommu_runtime_suspend()
1443 base = data->bank[i].base; in mtk_iommu_runtime_suspend()
1444 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_runtime_suspend()
1445 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); in mtk_iommu_runtime_suspend()
1446 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); in mtk_iommu_runtime_suspend()
1447 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); in mtk_iommu_runtime_suspend()
1448 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); in mtk_iommu_runtime_suspend()
1450 if (!data->plat_data->banks_enable[i]) in mtk_iommu_runtime_suspend()
1452 base = data->bank[i].base; in mtk_iommu_runtime_suspend()
1453 reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0); in mtk_iommu_runtime_suspend()
1454 reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); in mtk_iommu_runtime_suspend()
1455 reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR); in mtk_iommu_runtime_suspend()
1456 } while (++i < data->plat_data->banks_num); in mtk_iommu_runtime_suspend()
1457 clk_disable_unprepare(data->bclk); in mtk_iommu_runtime_suspend()
1464 struct mtk_iommu_suspend_reg *reg = &data->reg; in mtk_iommu_runtime_resume()
1469 ret = clk_prepare_enable(data->bclk); in mtk_iommu_runtime_resume()
1471 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); in mtk_iommu_runtime_resume()
1479 if (!reg->wr_len_ctrl) in mtk_iommu_runtime_resume()
1482 base = data->bank[i].base; in mtk_iommu_runtime_resume()
1483 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_runtime_resume()
1484 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); in mtk_iommu_runtime_resume()
1485 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); in mtk_iommu_runtime_resume()
1486 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); in mtk_iommu_runtime_resume()
1487 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); in mtk_iommu_runtime_resume()
1489 m4u_dom = data->bank[i].m4u_dom; in mtk_iommu_runtime_resume()
1490 if (!data->plat_data->banks_enable[i] || !m4u_dom) in mtk_iommu_runtime_resume()
1492 base = data->bank[i].base; in mtk_iommu_runtime_resume()
1493 writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0); in mtk_iommu_runtime_resume()
1494 writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL); in mtk_iommu_runtime_resume()
1495 writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR); in mtk_iommu_runtime_resume()
1496 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_runtime_resume()
1497 } while (++i < data->plat_data->banks_num); in mtk_iommu_runtime_resume()
1704 .pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
1708 .banks_portmsk = {[0] = GENMASK(19, 16), /* PCIe */
1776 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1777 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1778 { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data},
1779 { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1780 { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1781 { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
1782 { .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */
1783 { .compatible = "mediatek,mt8188-iommu-infra", .data = &mt8188_data_infra},
1784 { .compatible = "mediatek,mt8188-iommu-vdo", .data = &mt8188_data_vdo},
1785 { .compatible = "mediatek,mt8188-iommu-vpp", .data = &mt8188_data_vpp},
1786 { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
1787 { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
1788 { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo},
1789 { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp},
1790 { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data},
1799 .name = "mtk-iommu",