Lines Matching +full:rcar +full:- +full:gen2 +full:- +full:can
1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
29 #include <asm/dma-iommu.h>
32 #define arm_iommu_attach_device(...) -ENODEV
37 #define IPMMU_CTX_INVALID -1
93 /* -----------------------------------------------------------------------------
100 #define IMCTR 0x0000 /* R-Car Gen2/3 */
101 #define IMCTR_INTEN (1 << 2) /* R-Car Gen2/3 */
102 #define IMCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */
103 #define IMCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */
105 #define IMTTBCR 0x0008 /* R-Car Gen2/3 */
106 #define IMTTBCR_EAE (1 << 31) /* R-Car Gen2/3 */
107 #define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) /* R-Car Gen2 only */
108 #define IMTTBCR_ORGN0_WB_WA (1 << 10) /* R-Car Gen2 only */
109 #define IMTTBCR_IRGN0_WB_WA (1 << 8) /* R-Car Gen2 only */
110 #define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) /* R-Car Gen3 only */
111 #define IMTTBCR_SL0_LVL_1 (1 << 4) /* R-Car Gen2 only */
113 #define IMBUSCR 0x000c /* R-Car Gen2 only */
114 #define IMBUSCR_DVM (1 << 2) /* R-Car Gen2 only */
115 #define IMBUSCR_BUSSEL_MASK (3 << 0) /* R-Car Gen2 only */
117 #define IMTTLBR0 0x0010 /* R-Car Gen2/3 */
118 #define IMTTUBR0 0x0014 /* R-Car Gen2/3 */
120 #define IMSTR 0x0020 /* R-Car Gen2/3 */
121 #define IMSTR_MHIT (1 << 4) /* R-Car Gen2/3 */
122 #define IMSTR_ABORT (1 << 2) /* R-Car Gen2/3 */
123 #define IMSTR_PF (1 << 1) /* R-Car Gen2/3 */
124 #define IMSTR_TF (1 << 0) /* R-Car Gen2/3 */
126 #define IMMAIR0 0x0028 /* R-Car Gen2/3 */
128 #define IMELAR 0x0030 /* R-Car Gen2/3, IMEAR on R-Car Gen2 */
129 #define IMEUAR 0x0034 /* R-Car Gen3 only */
133 #define IMUCTR0(n) (0x0300 + ((n) * 16)) /* R-Car Gen2/3 */
134 #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) /* R-Car Gen3 only */
135 #define IMUCTR_TTSEL_MMU(n) ((n) << 4) /* R-Car Gen2/3 */
136 #define IMUCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */
137 #define IMUCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */
140 #define IMUASID0(n) (0x0308 + ((n) * 16)) /* R-Car Gen2/3 */
141 #define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) /* R-Car Gen3 only */
143 /* -----------------------------------------------------------------------------
151 return mmu->root == mmu; in ipmmu_is_root()
173 /* -----------------------------------------------------------------------------
179 return ioread32(mmu->base + offset); in ipmmu_read()
185 iowrite32(data, mmu->base + offset); in ipmmu_write()
191 unsigned int base = mmu->features->ctx_offset_base; in ipmmu_ctx_reg()
194 base += 0x800 - 8 * 0x40; in ipmmu_ctx_reg()
196 return base + context_id * mmu->features->ctx_offset_stride + reg; in ipmmu_ctx_reg()
214 return ipmmu_ctx_read(domain->mmu->root, domain->context_id, reg); in ipmmu_ctx_read_root()
220 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data); in ipmmu_ctx_write_root()
226 if (domain->mmu != domain->mmu->root) in ipmmu_ctx_write_all()
227 ipmmu_ctx_write(domain->mmu, domain->context_id, reg, data); in ipmmu_ctx_write_all()
229 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data); in ipmmu_ctx_write_all()
234 return mmu->features->utlb_offset_base + reg; in ipmmu_utlb_reg()
249 /* -----------------------------------------------------------------------------
261 dev_err_ratelimited(domain->mmu->dev, in ipmmu_tlb_sync()
262 "TLB sync timed out -- MMU may be deadlocked\n"); in ipmmu_tlb_sync()
282 struct ipmmu_vmsa_device *mmu = domain->mmu; in ipmmu_utlb_enable()
285 * TODO: Reference-count the microTLB as several bus masters can be in ipmmu_utlb_enable()
292 ipmmu_imuctr_write(mmu, utlb, IMUCTR_TTSEL_MMU(domain->context_id) | in ipmmu_utlb_enable()
294 mmu->utlb_ctx[utlb] = domain->context_id; in ipmmu_utlb_enable()
303 struct ipmmu_vmsa_device *mmu = domain->mmu; in ipmmu_utlb_disable()
306 mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID; in ipmmu_utlb_disable()
327 /* -----------------------------------------------------------------------------
337 spin_lock_irqsave(&mmu->lock, flags); in ipmmu_domain_allocate_context()
339 ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx); in ipmmu_domain_allocate_context()
340 if (ret != mmu->num_ctx) { in ipmmu_domain_allocate_context()
341 mmu->domains[ret] = domain; in ipmmu_domain_allocate_context()
342 set_bit(ret, mmu->ctx); in ipmmu_domain_allocate_context()
344 ret = -EBUSY; in ipmmu_domain_allocate_context()
346 spin_unlock_irqrestore(&mmu->lock, flags); in ipmmu_domain_allocate_context()
356 spin_lock_irqsave(&mmu->lock, flags); in ipmmu_domain_free_context()
358 clear_bit(context_id, mmu->ctx); in ipmmu_domain_free_context()
359 mmu->domains[context_id] = NULL; in ipmmu_domain_free_context()
361 spin_unlock_irqrestore(&mmu->lock, flags); in ipmmu_domain_free_context()
370 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; in ipmmu_domain_setup_context()
376 * We use long descriptors and allocate the whole 32-bit VA space to in ipmmu_domain_setup_context()
379 if (domain->mmu->features->twobit_imttbcr_sl0) in ipmmu_domain_setup_context()
384 if (domain->mmu->features->cache_snoop) in ipmmu_domain_setup_context()
392 domain->cfg.arm_lpae_s1_cfg.mair); in ipmmu_domain_setup_context()
395 if (domain->mmu->features->setup_imbuscr) in ipmmu_domain_setup_context()
408 * Enable the MMU and interrupt generation. The long-descriptor in ipmmu_domain_setup_context()
424 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory in ipmmu_domain_init_context()
425 * access, Long-descriptor format" that the NStable bit being set in a in ipmmu_domain_init_context()
430 * non-secure mode. in ipmmu_domain_init_context()
432 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS; in ipmmu_domain_init_context()
433 domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K; in ipmmu_domain_init_context()
434 domain->cfg.ias = 32; in ipmmu_domain_init_context()
435 domain->cfg.oas = 40; in ipmmu_domain_init_context()
436 domain->cfg.tlb = &ipmmu_flush_ops; in ipmmu_domain_init_context()
437 domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32); in ipmmu_domain_init_context()
438 domain->io_domain.geometry.force_aperture = true; in ipmmu_domain_init_context()
441 * cache handling. For now, delegate it to the io-pgtable code. in ipmmu_domain_init_context()
443 domain->cfg.coherent_walk = false; in ipmmu_domain_init_context()
444 domain->cfg.iommu_dev = domain->mmu->root->dev; in ipmmu_domain_init_context()
449 ret = ipmmu_domain_allocate_context(domain->mmu->root, domain); in ipmmu_domain_init_context()
453 domain->context_id = ret; in ipmmu_domain_init_context()
455 domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg, in ipmmu_domain_init_context()
457 if (!domain->iop) { in ipmmu_domain_init_context()
458 ipmmu_domain_free_context(domain->mmu->root, in ipmmu_domain_init_context()
459 domain->context_id); in ipmmu_domain_init_context()
460 return -EINVAL; in ipmmu_domain_init_context()
469 if (!domain->mmu) in ipmmu_domain_destroy_context()
480 ipmmu_domain_free_context(domain->mmu->root, domain->context_id); in ipmmu_domain_destroy_context()
483 /* -----------------------------------------------------------------------------
490 struct ipmmu_vmsa_device *mmu = domain->mmu; in ipmmu_domain_irq()
512 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%lx\n", in ipmmu_domain_irq()
515 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%lx\n", in ipmmu_domain_irq()
527 if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0)) in ipmmu_domain_irq()
530 dev_err_ratelimited(mmu->dev, in ipmmu_domain_irq()
544 spin_lock_irqsave(&mmu->lock, flags); in ipmmu_irq()
549 for (i = 0; i < mmu->num_ctx; i++) { in ipmmu_irq()
550 if (!mmu->domains[i]) in ipmmu_irq()
552 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED) in ipmmu_irq()
556 spin_unlock_irqrestore(&mmu->lock, flags); in ipmmu_irq()
561 /* -----------------------------------------------------------------------------
573 mutex_init(&domain->mutex); in ipmmu_domain_alloc_paging()
575 return &domain->io_domain; in ipmmu_domain_alloc_paging()
587 free_io_pgtable_ops(domain->iop); in ipmmu_domain_free()
602 return -ENXIO; in ipmmu_attach_device()
605 mutex_lock(&domain->mutex); in ipmmu_attach_device()
607 if (!domain->mmu) { in ipmmu_attach_device()
609 domain->mmu = mmu; in ipmmu_attach_device()
613 domain->mmu = NULL; in ipmmu_attach_device()
616 domain->context_id); in ipmmu_attach_device()
618 } else if (domain->mmu != mmu) { in ipmmu_attach_device()
620 * Something is wrong, we can't attach two devices using in ipmmu_attach_device()
623 ret = -EINVAL; in ipmmu_attach_device()
625 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id); in ipmmu_attach_device()
627 mutex_unlock(&domain->mutex); in ipmmu_attach_device()
632 for (i = 0; i < fwspec->num_ids; ++i) in ipmmu_attach_device()
633 ipmmu_utlb_enable(domain, fwspec->ids[i]); in ipmmu_attach_device()
650 for (i = 0; i < fwspec->num_ids; ++i) in ipmmu_iommu_identity_attach()
651 ipmmu_utlb_disable(domain, fwspec->ids[i]); in ipmmu_iommu_identity_attach()
674 return domain->iop->map_pages(domain->iop, iova, paddr, pgsize, pgcount, in ipmmu_map()
684 return domain->iop->unmap_pages(domain->iop, iova, pgsize, pgcount, gather); in ipmmu_unmap()
691 if (domain->mmu) in ipmmu_flush_iotlb_all()
708 return domain->iop->iova_to_phys(domain->iop, iova); in ipmmu_iova_to_phys()
716 ipmmu_pdev = of_find_device_by_node(args->np); in ipmmu_init_platform_device()
718 return -ENODEV; in ipmmu_init_platform_device()
726 { .family = "R-Car Gen3", },
727 { .family = "R-Car Gen4", },
751 * R-Car Gen3/4 and RZ/G2 use the allow list to opt-in devices. in ipmmu_device_is_allowed()
757 /* Check whether this SoC can use the IPMMU correctly or not */ in ipmmu_device_is_allowed()
765 /* Check whether this device can work with the IPMMU */ in ipmmu_device_is_allowed()
779 return -ENODEV; in ipmmu_of_xlate()
781 iommu_fwspec_add_ids(dev, spec->args, 1); in ipmmu_of_xlate()
783 /* Initialize once - xlate() will call multiple times */ in ipmmu_of_xlate()
800 * - Create one mapping per context (TLB). in ipmmu_init_arm_mapping()
801 * - Make the mapping size configurable ? We currently use a 2GB mapping in ipmmu_init_arm_mapping()
804 if (!mmu->mapping) { in ipmmu_init_arm_mapping()
809 dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n"); in ipmmu_init_arm_mapping()
814 mmu->mapping = mapping; in ipmmu_init_arm_mapping()
818 ret = arm_iommu_attach_device(dev, mmu->mapping); in ipmmu_init_arm_mapping()
827 if (mmu->mapping) in ipmmu_init_arm_mapping()
828 arm_iommu_release_mapping(mmu->mapping); in ipmmu_init_arm_mapping()
841 return ERR_PTR(-ENODEV); in ipmmu_probe_device()
843 return &mmu->iommu; in ipmmu_probe_device()
854 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); in ipmmu_probe_finalize()
863 for (i = 0; i < fwspec->num_ids; ++i) { in ipmmu_release_device()
864 unsigned int utlb = fwspec->ids[i]; in ipmmu_release_device()
867 mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID; in ipmmu_release_device()
870 arm_iommu_release_mapping(mmu->mapping); in ipmmu_release_device()
898 /* -----------------------------------------------------------------------------
907 for (i = 0; i < mmu->num_ctx; ++i) in ipmmu_device_reset()
955 .compatible = "renesas,ipmmu-vmsa",
958 .compatible = "renesas,ipmmu-r8a774a1",
961 .compatible = "renesas,ipmmu-r8a774b1",
964 .compatible = "renesas,ipmmu-r8a774c0",
967 .compatible = "renesas,ipmmu-r8a774e1",
970 .compatible = "renesas,ipmmu-r8a7795",
973 .compatible = "renesas,ipmmu-r8a7796",
976 .compatible = "renesas,ipmmu-r8a77961",
979 .compatible = "renesas,ipmmu-r8a77965",
982 .compatible = "renesas,ipmmu-r8a77970",
985 .compatible = "renesas,ipmmu-r8a77980",
988 .compatible = "renesas,ipmmu-r8a77990",
991 .compatible = "renesas,ipmmu-r8a77995",
994 .compatible = "renesas,ipmmu-r8a779a0",
997 .compatible = "renesas,rcar-gen4-ipmmu-vmsa",
1010 mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL); in ipmmu_probe()
1012 dev_err(&pdev->dev, "cannot allocate device data\n"); in ipmmu_probe()
1013 return -ENOMEM; in ipmmu_probe()
1016 mmu->dev = &pdev->dev; in ipmmu_probe()
1017 spin_lock_init(&mmu->lock); in ipmmu_probe()
1018 bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); in ipmmu_probe()
1019 mmu->features = of_device_get_match_data(&pdev->dev); in ipmmu_probe()
1020 memset(mmu->utlb_ctx, IPMMU_CTX_INVALID, mmu->features->num_utlbs); in ipmmu_probe()
1021 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); in ipmmu_probe()
1026 mmu->base = devm_platform_ioremap_resource(pdev, 0); in ipmmu_probe()
1027 if (IS_ERR(mmu->base)) in ipmmu_probe()
1028 return PTR_ERR(mmu->base); in ipmmu_probe()
1031 * The IPMMU has two register banks, for secure and non-secure modes. in ipmmu_probe()
1034 * mode the non-secure register bank is also available at an offset. in ipmmu_probe()
1038 * non-secure operation with the main register bank were not successful. in ipmmu_probe()
1039 * Offset the registers base unconditionally to point to the non-secure in ipmmu_probe()
1042 if (mmu->features->use_ns_alias_offset) in ipmmu_probe()
1043 mmu->base += IM_NS_ALIAS_OFFSET; in ipmmu_probe()
1045 mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts); in ipmmu_probe()
1049 * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property. in ipmmu_probe()
1051 if (!mmu->features->has_cache_leaf_nodes || in ipmmu_probe()
1052 !of_property_present(pdev->dev.of_node, "renesas,ipmmu-main")) in ipmmu_probe()
1053 mmu->root = mmu; in ipmmu_probe()
1055 mmu->root = ipmmu_find_root(); in ipmmu_probe()
1060 if (!mmu->root) in ipmmu_probe()
1061 return -EPROBE_DEFER; in ipmmu_probe()
1069 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0, in ipmmu_probe()
1070 dev_name(&pdev->dev), mmu); in ipmmu_probe()
1072 dev_err(&pdev->dev, "failed to request IRQ %d\n", irq); in ipmmu_probe()
1078 if (mmu->features->reserved_context) { in ipmmu_probe()
1079 dev_info(&pdev->dev, "IPMMU context 0 is reserved\n"); in ipmmu_probe()
1080 set_bit(0, mmu->ctx); in ipmmu_probe()
1086 * - R-Car Gen2 IPMMU (all devices registered) in ipmmu_probe()
1087 * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device) in ipmmu_probe()
1089 if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) { in ipmmu_probe()
1090 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL, in ipmmu_probe()
1091 dev_name(&pdev->dev)); in ipmmu_probe()
1095 ret = iommu_device_register(&mmu->iommu, &ipmmu_ops, &pdev->dev); in ipmmu_probe()
1101 * We can't create the ARM mapping here as it requires the bus to have in ipmmu_probe()
1115 iommu_device_sysfs_remove(&mmu->iommu); in ipmmu_remove()
1116 iommu_device_unregister(&mmu->iommu); in ipmmu_remove()
1118 arm_iommu_release_mapping(mmu->mapping); in ipmmu_remove()
1132 for (i = 0; i < mmu->num_ctx; i++) { in ipmmu_resume_noirq()
1133 if (!mmu->domains[i]) in ipmmu_resume_noirq()
1136 ipmmu_domain_setup_context(mmu->domains[i]); in ipmmu_resume_noirq()
1140 /* Re-enable active micro-TLBs */ in ipmmu_resume_noirq()
1141 for (i = 0; i < mmu->features->num_utlbs; i++) { in ipmmu_resume_noirq()
1142 if (mmu->utlb_ctx[i] == IPMMU_CTX_INVALID) in ipmmu_resume_noirq()
1145 ipmmu_utlb_enable(mmu->root->domains[mmu->utlb_ctx[i]], i); in ipmmu_resume_noirq()
1157 .name = "ipmmu-vmsa",