Lines Matching full:invalidation
85 #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
86 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
87 #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
88 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
89 #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
90 #define DMAR_IQER_REG 0xb0 /* Invalidation queue error record register */
338 #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */
339 #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */
340 #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */
430 /* PASID cache invalidation granu */
483 void *desc; /* invalidation queue */
722 struct q_inval *qi; /* Queued invalidation info */
1106 * The least significant zero bit indicates the invalidation address in qi_desc_dev_iotlb_pasid()