Lines Matching defs:intel_iommu

706 struct intel_iommu {  struct
707 	void __iomem	*reg; /* Pointer to hardware regs, virtual addr */
708 	u64 		reg_phys; /* physical address of hw register set */
709 	u64		reg_size; /* size of hw register set */
710 	u64		cap;
711 	u64		ecap;
712 	u64		vccap;
713 	u64		ecmdcap[DMA_MAX_NUM_ECMDCAP];
714 	u32		gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
715 	raw_spinlock_t	register_lock; /* protect register handling */
716 	int		seq_id;	/* sequence id of the iommu */
717 	int		agaw; /* agaw of this iommu */
718 	int		msagaw; /* max sagaw of this iommu */
719 	unsigned int	irq, pr_irq, perf_irq;
720 	u16		segment;     /* PCI segment# */
721 	unsigned char	name[16];    /* Device Name */
725 	struct mutex	did_lock;
726 	struct ida	domain_ida; /* domain id allocator */
727 	unsigned long	*copied_tables; /* bitmap of copied tables */
728 	spinlock_t	lock; /* protect context, domain ids */
729 	struct root_entry *root_entry; /* virtual address */
731 	struct iommu_flush flush;
733 	struct page_req_dsc *prq;
734 	unsigned char prq_name[16];    /* Name for PRQ interrupt */
735 	unsigned long prq_seq_number;
736 	struct completion prq_complete;
737 	struct iopf_queue *iopf_queue;
738 	unsigned char iopfq_name[16];
740 	struct mutex iopf_lock;
741 	struct q_inval  *qi;            /* Queued invalidation info */
742 	u32 iommu_state[MAX_SR_DMAR_REGS]; /* Store iommu states between suspend and resume.*/
745 	struct rb_root device_rbtree;
747 	spinlock_t device_rbtree_lock;
750 	struct ir_table *ir_table;	/* Interrupt remapping info */
751 	struct irq_domain *ir_domain;
753 	struct iommu_device iommu;  /* IOMMU core code handle */
754 	int		node;
755 	u32		flags;      /* Software defined flags */
757 	struct dmar_drhd_unit *drhd;
781 	struct intel_iommu *iommu; /* IOMMU used by this device */  argument