Lines Matching +full:sc7180 +full:- +full:mdss
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
14 #include "arm-smmu.h"
15 #include "arm-smmu-qcom.h"
17 #define QCOM_DUMMY_VAL -1
20 * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
38 { .compatible = "qcom,adreno-gmu",
40 { .compatible = "qcom,adreno-smmu",
44 { .compatible = "qcom,sc7280-mdss",
46 { .compatible = "qcom,sc7280-venus",
48 { .compatible = "qcom,sm8550-mdss",
66 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
89 if (qsmmu->stall_enabled & BIT(idx))
99 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
100 struct arm_smmu_device *smmu = smmu_domain->smmu;
102 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);
103 info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);
104 info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
105 info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
106 info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
107 info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
108 info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
114 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
115 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);
118 qsmmu->stall_enabled |= BIT(cfg->cbndx);
120 qsmmu->stall_enabled &= ~BIT(cfg->cbndx);
126 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
127 struct arm_smmu_device *smmu = smmu_domain->smmu;
133 arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
139 struct arm_smmu_device *smmu = smmu_domain->smmu;
140 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
144 ret = pm_runtime_resume_and_get(smmu->dev);
146 dev_err(smmu->dev, "failed to get runtime PM: %d\n", ret);
150 reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR);
154 arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg);
155 pm_runtime_put_autosuspend(smmu->dev);
161 struct arm_smmu_device *smmu = smmu_domain->smmu;
164 ret = pm_runtime_resume_and_get(smmu->dev);
166 dev_err(smmu->dev, "failed to get runtime PM: %d\n", ret);
171 smmu->base + ARM_SMMU_GFX_PRR_CFG_LADDR);
173 smmu->base + ARM_SMMU_GFX_PRR_CFG_UADDR);
174 pm_runtime_put_autosuspend(smmu->dev);
186 * identify it and configure it for per-instance pagetables
188 for (i = 0; i < fwspec->num_ids; i++) {
189 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);
203 io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
204 return &pgtable->cfg;
209 * The GPU driver will call this to enable TTBR0 when per-instance pagetables
217 struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
218 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
219 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];
222 if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)
223 return -EINVAL;
228 if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
229 return -EINVAL;
232 cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);
233 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
235 u32 tcr = cb->tcr[0];
238 if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
239 return -EINVAL;
244 cb->tcr[0] = tcr;
245 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
246 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
249 arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);
269 count = smmu->num_context_banks;
272 return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);
277 const struct device_node *np = smmu->dev->of_node;
279 if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2"))
296 arm_smmu_cb_write(smmu, cbndx, ARM_SMMU_CB_ACTLR, (unsigned long)match->data);
302 const struct device_node *np = smmu_domain->smmu->dev->of_node;
303 struct arm_smmu_device *smmu = smmu_domain->smmu;
306 int cbndx = smmu_domain->cfg.cbndx;
309 smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
311 client_match = qsmmu->data->client_match;
321 * All targets that use the qcom,adreno-smmu compatible string *should*
322 * be AARCH64 stage 1 but double check because the arm-smmu code assumes
325 if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&
326 (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&
327 (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
328 pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;
335 priv->cookie = smmu_domain;
336 priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
337 priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
338 priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
339 priv->set_stall = qcom_adreno_smmu_set_stall;
340 priv->resume_translation = qcom_adreno_smmu_resume_translation;
341 priv->set_prr_bit = NULL;
342 priv->set_prr_addr = NULL;
344 if (of_device_is_compatible(np, "qcom,smmu-500") &&
345 of_device_is_compatible(np, "qcom,adreno-smmu")) {
346 priv->set_prr_bit = qcom_adreno_smmu_set_prr_bit;
347 priv->set_prr_addr = qcom_adreno_smmu_set_prr_addr;
355 { .compatible = "qcom,adreno-gmu" },
357 { .compatible = "qcom,mdss" },
358 { .compatible = "qcom,qcm2290-mdss" },
359 { .compatible = "qcom,sc7180-mdss" },
360 { .compatible = "qcom,sc7180-mss-pil" },
361 { .compatible = "qcom,sc7280-mdss" },
362 { .compatible = "qcom,sc7280-mss-pil" },
363 { .compatible = "qcom,sc8180x-mdss" },
364 { .compatible = "qcom,sc8280xp-mdss" },
365 { .compatible = "qcom,sdm670-mdss" },
366 { .compatible = "qcom,sdm845-mdss" },
367 { .compatible = "qcom,sdm845-mss-pil" },
368 { .compatible = "qcom,sm6350-mdss" },
369 { .compatible = "qcom,sm6375-mdss" },
370 { .compatible = "qcom,sm8150-mdss" },
371 { .compatible = "qcom,sm8250-mdss" },
372 { .compatible = "qcom,x1e80100-mdss" },
379 struct arm_smmu_device *smmu = smmu_domain->smmu;
382 int cbndx = smmu_domain->cfg.cbndx;
384 smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
386 client_match = qsmmu->data->client_match;
406 if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") &&
407 smmu->num_context_banks == 13) {
408 smmu->num_context_banks = 12;
409 } else if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2")) {
410 if (smmu->num_context_banks == 21) /* SDM630 / SDM660 A2NOC SMMU */
411 smmu->num_context_banks = 7;
412 else if (smmu->num_context_banks == 14) /* SDM630 / SDM660 LPASS SMMU */
413 smmu->num_context_banks = 13;
423 if (smmu->num_mapping_groups > 128) {
424 dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");
425 smmu->num_mapping_groups = 128;
428 last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
442 qsmmu->bypass_quirk = true;
443 qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
445 set_bit(qsmmu->bypass_cbndx, smmu->context_map);
447 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
450 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
453 for (i = 0; i < smmu->num_mapping_groups; i++) {
459 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
460 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
461 smmu->smrs[i].valid = true;
463 smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
464 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
465 smmu->s2crs[i].cbndx = 0xff;
475 smmu->features &= ~ARM_SMMU_FEAT_FMT_AARCH64_16K;
478 if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2") &&
479 smmu->num_context_banks == 5)
480 smmu->num_context_banks = 2;
487 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
489 u32 cbndx = s2cr->cbndx;
490 u32 type = s2cr->type;
493 if (qsmmu->bypass_quirk) {
502 cbndx = qsmmu->bypass_cbndx;
516 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
535 * To address performance degradation in non-real time clients,
536 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
538 * call handlers to turn on/off the wait-for-safe logic.
542 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");
602 const struct device_node *np = smmu->dev->of_node;
607 return ERR_PTR(-EINVAL);
609 if (np && of_device_is_compatible(np, "qcom,adreno-smmu"))
610 impl = data->adreno_impl;
612 impl = data->impl;
619 return ERR_PTR(dev_err_probe(smmu->dev, -EPROBE_DEFER,
622 qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);
624 return ERR_PTR(-ENOMEM);
626 qsmmu->smmu.impl = impl;
627 qsmmu->data = data;
629 return &qsmmu->smmu;
661 * by the separate sdm845-smmu-v2 device.
674 * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
675 * special handling and can not be covered by the qcom,smmu-500 entry.
678 { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
679 { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
680 { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
681 { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data },
682 { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
683 { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data },
684 { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
685 { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
686 { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
687 { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
688 { .compatible = "qcom,sdm670-smmu-v2", .data = &qcom_smmu_v2_data },
689 { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
690 { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
691 { .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
692 { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
693 { .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },
694 { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
695 { .compatible = "qcom,sm6375-smmu-v2", .data = &qcom_smmu_v2_data },
696 { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
697 { .compatible = "qcom,sm7150-smmu-v2", .data = &qcom_smmu_v2_data },
698 { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
699 { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
700 { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
701 { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
702 { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
708 { "LENOVO", "CB-01 ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
716 struct device *dev = &pdev->dev;
725 if (dev->pm_domain) {
734 { .compatible = "qcom,sc7280-tbu" },
735 { .compatible = "qcom,sdm845-tbu" },
749 const struct device_node *np = smmu->dev->of_node;
766 return qcom_smmu_create(smmu, match->data);
770 * qcom_smmu_impl_of_match[] table, and GPU per-process page-
773 WARN(of_device_is_compatible(np, "qcom,adreno-smmu"),
775 dev_name(smmu->dev));