Lines Matching +full:msm8996 +full:- +full:smmu +full:- +full:v2
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
14 #include "arm-smmu.h"
15 #include "arm-smmu-qcom.h"
17 #define QCOM_DUMMY_VAL -1
19 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) in to_qcom_smmu() argument
21 return container_of(smmu, struct qcom_smmu, smmu); in to_qcom_smmu()
24 static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, in qcom_smmu_tlb_sync() argument
30 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL); in qcom_smmu_tlb_sync()
32 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { in qcom_smmu_tlb_sync()
33 reg = arm_smmu_readl(smmu, page, status); in qcom_smmu_tlb_sync()
41 qcom_smmu_tlb_sync_debug(smmu); in qcom_smmu_tlb_sync()
44 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, in qcom_adreno_smmu_write_sctlr() argument
47 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); in qcom_adreno_smmu_write_sctlr()
55 if (qsmmu->stall_enabled & BIT(idx)) in qcom_adreno_smmu_write_sctlr()
58 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in qcom_adreno_smmu_write_sctlr()
65 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_get_fault_info()
66 struct arm_smmu_device *smmu = smmu_domain->smmu; in qcom_adreno_smmu_get_fault_info() local
68 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); in qcom_adreno_smmu_get_fault_info()
69 info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); in qcom_adreno_smmu_get_fault_info()
70 info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); in qcom_adreno_smmu_get_fault_info()
71 info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); in qcom_adreno_smmu_get_fault_info()
72 info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); in qcom_adreno_smmu_get_fault_info()
73 info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); in qcom_adreno_smmu_get_fault_info()
74 info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); in qcom_adreno_smmu_get_fault_info()
80 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_set_stall()
81 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu); in qcom_adreno_smmu_set_stall()
84 qsmmu->stall_enabled |= BIT(cfg->cbndx); in qcom_adreno_smmu_set_stall()
86 qsmmu->stall_enabled &= ~BIT(cfg->cbndx); in qcom_adreno_smmu_set_stall()
92 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_resume_translation()
93 struct arm_smmu_device *smmu = smmu_domain->smmu; in qcom_adreno_smmu_resume_translation() local
99 arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg); in qcom_adreno_smmu_resume_translation()
111 * identify it and configure it for per-instance pagetables in qcom_adreno_smmu_is_gpu_device()
113 for (i = 0; i < fwspec->num_ids; i++) { in qcom_adreno_smmu_is_gpu_device()
114 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); in qcom_adreno_smmu_is_gpu_device()
128 io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); in qcom_adreno_smmu_get_ttbr1_cfg()
129 return &pgtable->cfg; in qcom_adreno_smmu_get_ttbr1_cfg()
134 * The GPU driver will call this to enable TTBR0 when per-instance pagetables
142 struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); in qcom_adreno_smmu_set_ttbr0_cfg()
143 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_set_ttbr0_cfg()
144 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; in qcom_adreno_smmu_set_ttbr0_cfg()
147 if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) in qcom_adreno_smmu_set_ttbr0_cfg()
148 return -EINVAL; in qcom_adreno_smmu_set_ttbr0_cfg()
153 if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) in qcom_adreno_smmu_set_ttbr0_cfg()
154 return -EINVAL; in qcom_adreno_smmu_set_ttbr0_cfg()
157 cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); in qcom_adreno_smmu_set_ttbr0_cfg()
158 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
160 u32 tcr = cb->tcr[0]; in qcom_adreno_smmu_set_ttbr0_cfg()
163 if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) in qcom_adreno_smmu_set_ttbr0_cfg()
164 return -EINVAL; in qcom_adreno_smmu_set_ttbr0_cfg()
169 cb->tcr[0] = tcr; in qcom_adreno_smmu_set_ttbr0_cfg()
170 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in qcom_adreno_smmu_set_ttbr0_cfg()
171 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
174 arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); in qcom_adreno_smmu_set_ttbr0_cfg()
180 struct arm_smmu_device *smmu, in qcom_adreno_smmu_alloc_context_bank() argument
194 count = smmu->num_context_banks; in qcom_adreno_smmu_alloc_context_bank()
197 return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); in qcom_adreno_smmu_alloc_context_bank()
200 static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) in qcom_adreno_can_do_ttbr1() argument
202 const struct device_node *np = smmu->dev->of_node; in qcom_adreno_can_do_ttbr1()
204 if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) in qcom_adreno_can_do_ttbr1()
215 smmu_domain->cfg.flush_walk_prefer_tlbiasid = true; in qcom_adreno_smmu_init_context()
222 * All targets that use the qcom,adreno-smmu compatible string *should* in qcom_adreno_smmu_init_context()
223 * be AARCH64 stage 1 but double check because the arm-smmu code assumes in qcom_adreno_smmu_init_context()
226 if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) && in qcom_adreno_smmu_init_context()
227 (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && in qcom_adreno_smmu_init_context()
228 (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) in qcom_adreno_smmu_init_context()
229 pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; in qcom_adreno_smmu_init_context()
236 priv->cookie = smmu_domain; in qcom_adreno_smmu_init_context()
237 priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; in qcom_adreno_smmu_init_context()
238 priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; in qcom_adreno_smmu_init_context()
239 priv->get_fault_info = qcom_adreno_smmu_get_fault_info; in qcom_adreno_smmu_init_context()
240 priv->set_stall = qcom_adreno_smmu_set_stall; in qcom_adreno_smmu_init_context()
241 priv->resume_translation = qcom_adreno_smmu_resume_translation; in qcom_adreno_smmu_init_context()
248 { .compatible = "qcom,adreno-gmu" },
251 { .compatible = "qcom,qcm2290-mdss" },
252 { .compatible = "qcom,sc7180-mdss" },
253 { .compatible = "qcom,sc7180-mss-pil" },
254 { .compatible = "qcom,sc7280-mdss" },
255 { .compatible = "qcom,sc7280-mss-pil" },
256 { .compatible = "qcom,sc8180x-mdss" },
257 { .compatible = "qcom,sc8280xp-mdss" },
258 { .compatible = "qcom,sdm670-mdss" },
259 { .compatible = "qcom,sdm845-mdss" },
260 { .compatible = "qcom,sdm845-mss-pil" },
261 { .compatible = "qcom,sm6350-mdss" },
262 { .compatible = "qcom,sm6375-mdss" },
263 { .compatible = "qcom,sm8150-mdss" },
264 { .compatible = "qcom,sm8250-mdss" },
265 { .compatible = "qcom,x1e80100-mdss" },
272 smmu_domain->cfg.flush_walk_prefer_tlbiasid = true; in qcom_smmu_init_context()
277 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) in qcom_smmu_cfg_probe() argument
279 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); in qcom_smmu_cfg_probe()
286 * MSM8998 LPASS SMMU reports 13 context banks, but accessing in qcom_smmu_cfg_probe()
289 if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") && in qcom_smmu_cfg_probe()
290 smmu->num_context_banks == 13) { in qcom_smmu_cfg_probe()
291 smmu->num_context_banks = 12; in qcom_smmu_cfg_probe()
292 } else if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2")) { in qcom_smmu_cfg_probe()
293 if (smmu->num_context_banks == 21) /* SDM630 / SDM660 A2NOC SMMU */ in qcom_smmu_cfg_probe()
294 smmu->num_context_banks = 7; in qcom_smmu_cfg_probe()
295 else if (smmu->num_context_banks == 14) /* SDM630 / SDM660 LPASS SMMU */ in qcom_smmu_cfg_probe()
296 smmu->num_context_banks = 13; in qcom_smmu_cfg_probe()
300 * Some platforms support more than the Arm SMMU architected maximum of in qcom_smmu_cfg_probe()
306 if (smmu->num_mapping_groups > 128) { in qcom_smmu_cfg_probe()
307 dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n"); in qcom_smmu_cfg_probe()
308 smmu->num_mapping_groups = 128; in qcom_smmu_cfg_probe()
311 last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); in qcom_smmu_cfg_probe()
322 arm_smmu_gr0_write(smmu, last_s2cr, reg); in qcom_smmu_cfg_probe()
323 reg = arm_smmu_gr0_read(smmu, last_s2cr); in qcom_smmu_cfg_probe()
325 qsmmu->bypass_quirk = true; in qcom_smmu_cfg_probe()
326 qsmmu->bypass_cbndx = smmu->num_context_banks - 1; in qcom_smmu_cfg_probe()
328 set_bit(qsmmu->bypass_cbndx, smmu->context_map); in qcom_smmu_cfg_probe()
330 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); in qcom_smmu_cfg_probe()
333 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg); in qcom_smmu_cfg_probe()
336 for (i = 0; i < smmu->num_mapping_groups; i++) { in qcom_smmu_cfg_probe()
337 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); in qcom_smmu_cfg_probe()
342 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); in qcom_smmu_cfg_probe()
343 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); in qcom_smmu_cfg_probe()
344 smmu->smrs[i].valid = true; in qcom_smmu_cfg_probe()
346 smmu->s2crs[i].type = S2CR_TYPE_BYPASS; in qcom_smmu_cfg_probe()
347 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; in qcom_smmu_cfg_probe()
348 smmu->s2crs[i].cbndx = 0xff; in qcom_smmu_cfg_probe()
355 static int qcom_adreno_smmuv2_cfg_probe(struct arm_smmu_device *smmu) in qcom_adreno_smmuv2_cfg_probe() argument
358 smmu->features &= ~ARM_SMMU_FEAT_FMT_AARCH64_16K; in qcom_adreno_smmuv2_cfg_probe()
361 if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2") && in qcom_adreno_smmuv2_cfg_probe()
362 smmu->num_context_banks == 5) in qcom_adreno_smmuv2_cfg_probe()
363 smmu->num_context_banks = 2; in qcom_adreno_smmuv2_cfg_probe()
368 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) in qcom_smmu_write_s2cr() argument
370 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; in qcom_smmu_write_s2cr()
371 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); in qcom_smmu_write_s2cr()
372 u32 cbndx = s2cr->cbndx; in qcom_smmu_write_s2cr()
373 u32 type = s2cr->type; in qcom_smmu_write_s2cr()
376 if (qsmmu->bypass_quirk) { in qcom_smmu_write_s2cr()
385 cbndx = qsmmu->bypass_cbndx; in qcom_smmu_write_s2cr()
399 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); in qcom_smmu_write_s2cr()
400 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); in qcom_smmu_write_s2cr()
411 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) in qcom_sdm845_smmu500_reset() argument
415 arm_mmu500_reset(smmu); in qcom_sdm845_smmu500_reset()
418 * To address performance degradation in non-real time clients, in qcom_sdm845_smmu500_reset()
419 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards, in qcom_sdm845_smmu500_reset()
421 * call handlers to turn on/off the wait-for-safe logic. in qcom_sdm845_smmu500_reset()
425 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n"); in qcom_sdm845_smmu500_reset()
482 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, in qcom_smmu_create() argument
485 const struct device_node *np = smmu->dev->of_node; in qcom_smmu_create()
490 return ERR_PTR(-EINVAL); in qcom_smmu_create()
492 if (np && of_device_is_compatible(np, "qcom,adreno-smmu")) in qcom_smmu_create()
493 impl = data->adreno_impl; in qcom_smmu_create()
495 impl = data->impl; in qcom_smmu_create()
498 return smmu; in qcom_smmu_create()
502 return ERR_PTR(dev_err_probe(smmu->dev, -EPROBE_DEFER, in qcom_smmu_create()
505 qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL); in qcom_smmu_create()
507 return ERR_PTR(-ENOMEM); in qcom_smmu_create()
509 qsmmu->smmu.impl = impl; in qcom_smmu_create()
510 qsmmu->cfg = data->cfg; in qcom_smmu_create()
512 return &qsmmu->smmu; in qcom_smmu_create()
527 * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
543 * No need for adreno impl here. On sdm845 the Adreno SMMU is handled
544 * by the separate sdm845-smmu-v2 device.
556 * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
557 * special handling and can not be covered by the qcom,smmu-500 entry.
560 { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
561 { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
562 { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
563 { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data },
564 { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
565 { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data },
566 { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
567 { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
568 { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
569 { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
570 { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
571 { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
572 { .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
573 { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
574 { .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },
575 { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
576 { .compatible = "qcom,sm6375-smmu-v2", .data = &qcom_smmu_v2_data },
577 { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
578 { .compatible = "qcom,sm7150-smmu-v2", .data = &qcom_smmu_v2_data },
579 { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
580 { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
581 { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
582 { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
583 { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
589 { "LENOVO", "CB-01 ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
590 { "QCOM ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
597 struct device *dev = &pdev->dev; in qcom_smmu_tbu_probe()
606 if (dev->pm_domain) { in qcom_smmu_tbu_probe()
615 { .compatible = "qcom,sc7280-tbu" },
616 { .compatible = "qcom,sdm845-tbu" },
628 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) in qcom_smmu_impl_init() argument
630 const struct device_node *np = smmu->dev->of_node; in qcom_smmu_impl_init()
641 return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data); in qcom_smmu_impl_init()
647 return qcom_smmu_create(smmu, match->data); in qcom_smmu_impl_init()
651 * qcom_smmu_impl_of_match[] table, and GPU per-process page- in qcom_smmu_impl_init()
654 WARN(of_device_is_compatible(np, "qcom,adreno-smmu"), in qcom_smmu_impl_init()
656 dev_name(smmu->dev)); in qcom_smmu_impl_init()
658 return smmu; in qcom_smmu_impl_init()