Lines Matching refs:vcmdq
232 static inline char *lvcmdq_error_header(struct tegra241_vcmdq *vcmdq,
236 if (WARN_ON(!vcmdq->vintf))
239 vcmdq->vintf->idx, vcmdq->idx, vcmdq->lidx);
243 static inline int vcmdq_write_config(struct tegra241_vcmdq *vcmdq, u32 regval)
245 char header[64], *h = lvcmdq_error_header(vcmdq, header, 64);
247 return tegra241_cmdqv_write_config(vcmdq->cmdqv,
248 REG_VCMDQ_PAGE0(vcmdq, CONFIG),
249 REG_VCMDQ_PAGE0(vcmdq, STATUS),
250 regval, h, &vcmdq->enabled);
264 struct tegra241_vcmdq *vcmdq = vintf->lvcmdqs[lidx];
265 u32 gerror = readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERROR));
267 __arm_smmu_cmdq_skip_err(&vintf->cmdqv->smmu, &vcmdq->cmdq);
268 writel(gerror, REG_VCMDQ_PAGE0(vcmdq, GERRORN));
324 struct tegra241_vcmdq *vcmdq;
342 vcmdq = vintf->lvcmdqs[lidx];
343 if (!vcmdq || !READ_ONCE(vcmdq->enabled))
347 if (!arm_smmu_cmdq_supports_cmd(&vcmdq->cmdq, ent))
349 return &vcmdq->cmdq;
354 static void tegra241_vcmdq_hw_deinit(struct tegra241_vcmdq *vcmdq)
356 char header[64], *h = lvcmdq_error_header(vcmdq, header, 64);
359 if (vcmdq_write_config(vcmdq, 0)) {
360 dev_err(vcmdq->cmdqv->dev,
362 readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERRORN)),
363 readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERROR)),
364 readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, CONS)));
366 writel_relaxed(0, REG_VCMDQ_PAGE0(vcmdq, PROD));
367 writel_relaxed(0, REG_VCMDQ_PAGE0(vcmdq, CONS));
368 writeq_relaxed(0, REG_VCMDQ_PAGE1(vcmdq, BASE));
369 writeq_relaxed(0, REG_VCMDQ_PAGE1(vcmdq, CONS_INDX_BASE));
371 gerrorn = readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERRORN));
372 gerror = readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERROR));
374 dev_warn(vcmdq->cmdqv->dev,
376 writel(gerror, REG_VCMDQ_PAGE0(vcmdq, GERRORN));
379 dev_dbg(vcmdq->cmdqv->dev, "%sdeinited\n", h);
382 static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq)
384 char header[64], *h = lvcmdq_error_header(vcmdq, header, 64);
388 tegra241_vcmdq_hw_deinit(vcmdq);
391 writeq_relaxed(vcmdq->cmdq.q.q_base, REG_VCMDQ_PAGE1(vcmdq, BASE));
393 ret = vcmdq_write_config(vcmdq, VCMDQ_EN);
395 dev_err(vcmdq->cmdqv->dev,
397 readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERRORN)),
398 readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERROR)),
399 readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, CONS)));
403 dev_dbg(vcmdq->cmdqv->dev, "%sinited\n", h);
490 static void tegra241_vcmdq_free_smmu_cmdq(struct tegra241_vcmdq *vcmdq)
492 struct arm_smmu_queue *q = &vcmdq->cmdq.q;
498 dmam_free_coherent(vcmdq->cmdqv->smmu.dev, qsz, q->base, q->base_dma);
501 static int tegra241_vcmdq_alloc_smmu_cmdq(struct tegra241_vcmdq *vcmdq)
503 struct arm_smmu_device *smmu = &vcmdq->cmdqv->smmu;
504 struct arm_smmu_cmdq *cmdq = &vcmdq->cmdq;
510 snprintf(name, 16, "vcmdq%u", vcmdq->idx);
518 ret = arm_smmu_init_one_queue(smmu, q, vcmdq->page0,
528 if (!vcmdq->vintf->hyp_own)
542 struct tegra241_vcmdq *vcmdq)
547 vcmdq->idx = idx * cmdqv->num_lvcmdqs_per_vintf + lidx;
548 vcmdq->lidx = lidx;
549 vcmdq->cmdqv = cmdqv;
550 vcmdq->vintf = vintf;
551 vcmdq->page0 = cmdqv->base + TEGRA241_VINTFi_LVCMDQ_PAGE0(idx, lidx);
552 vcmdq->page1 = cmdqv->base + TEGRA241_VINTFi_LVCMDQ_PAGE1(idx, lidx);
554 vintf->lvcmdqs[lidx] = vcmdq;
560 struct tegra241_vcmdq *vcmdq = vintf->lvcmdqs[lidx];
563 tegra241_vcmdq_free_smmu_cmdq(vcmdq);
567 "%sdeallocated\n", lvcmdq_error_header(vcmdq, header, 64));
568 kfree(vcmdq);
575 struct tegra241_vcmdq *vcmdq;
579 vcmdq = kzalloc(sizeof(*vcmdq), GFP_KERNEL);
580 if (!vcmdq)
583 ret = tegra241_vintf_init_lvcmdq(vintf, lidx, vcmdq);
588 ret = tegra241_vcmdq_alloc_smmu_cmdq(vcmdq);
593 "%sallocated\n", lvcmdq_error_header(vcmdq, header, 64));
594 return vcmdq;
599 kfree(vcmdq);
782 struct tegra241_vcmdq *vcmdq;
784 vcmdq = tegra241_vintf_alloc_lvcmdq(vintf, lidx);
785 if (IS_ERR(vcmdq))