Lines Matching +full:acquisition +full:- +full:time +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/io-pgtable.h>
27 #include <linux/pci-ats.h>
32 #include "arm-smmu-v3.h"
33 #include "../../dma-iommu.h"
38 "Disable MSI-based polling for CMD_SYNC completion.");
81 { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
82 { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"},
95 if (of_property_read_bool(smmu->dev->of_node, in parse_driver_options()
97 smmu->options |= arm_smmu_options[i].opt; in parse_driver_options()
98 dev_notice(smmu->dev, "option %s\n", in parse_driver_options()
104 /* Low-level queue manipulation functions */
109 prod = Q_IDX(q, q->prod); in queue_has_space()
110 cons = Q_IDX(q, q->cons); in queue_has_space()
112 if (Q_WRP(q, q->prod) == Q_WRP(q, q->cons)) in queue_has_space()
113 space = (1 << q->max_n_shift) - (prod - cons); in queue_has_space()
115 space = cons - prod; in queue_has_space()
122 return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) && in queue_full()
123 Q_WRP(q, q->prod) != Q_WRP(q, q->cons); in queue_full()
128 return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) && in queue_empty()
129 Q_WRP(q, q->prod) == Q_WRP(q, q->cons); in queue_empty()
134 return ((Q_WRP(q, q->cons) == Q_WRP(q, prod)) && in queue_consumed()
135 (Q_IDX(q, q->cons) > Q_IDX(q, prod))) || in queue_consumed()
136 ((Q_WRP(q, q->cons) != Q_WRP(q, prod)) && in queue_consumed()
137 (Q_IDX(q, q->cons) <= Q_IDX(q, prod))); in queue_consumed()
147 writel_relaxed(q->llq.cons, q->cons_reg); in queue_sync_cons_out()
152 u32 cons = (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1; in queue_inc_cons()
153 q->cons = Q_OVF(q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons); in queue_inc_cons()
158 struct arm_smmu_ll_queue *llq = &q->llq; in queue_sync_cons_ovf()
160 if (likely(Q_OVF(llq->prod) == Q_OVF(llq->cons))) in queue_sync_cons_ovf()
163 llq->cons = Q_OVF(llq->prod) | Q_WRP(llq, llq->cons) | in queue_sync_cons_ovf()
164 Q_IDX(llq, llq->cons); in queue_sync_cons_ovf()
178 prod = readl(q->prod_reg); in queue_sync_prod_in()
180 if (Q_OVF(prod) != Q_OVF(q->llq.prod)) in queue_sync_prod_in()
181 ret = -EOVERFLOW; in queue_sync_prod_in()
183 q->llq.prod = prod; in queue_sync_prod_in()
189 u32 prod = (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + n; in queue_inc_prod_n()
190 return Q_OVF(q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod); in queue_inc_prod_n()
196 qp->delay = 1; in queue_poll_init()
197 qp->spin_cnt = 0; in queue_poll_init()
198 qp->wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV); in queue_poll_init()
199 qp->timeout = ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US); in queue_poll_init()
204 if (ktime_compare(ktime_get(), qp->timeout) > 0) in queue_poll()
205 return -ETIMEDOUT; in queue_poll()
207 if (qp->wfe) { in queue_poll()
209 } else if (++qp->spin_cnt < ARM_SMMU_POLL_SPIN_COUNT) { in queue_poll()
212 udelay(qp->delay); in queue_poll()
213 qp->delay *= 2; in queue_poll()
214 qp->spin_cnt = 0; in queue_poll()
238 if (queue_empty(&q->llq)) in queue_remove_raw()
239 return -EAGAIN; in queue_remove_raw()
241 queue_read(ent, Q_ENT(q, q->llq.cons), q->ent_dwords); in queue_remove_raw()
242 queue_inc_cons(&q->llq); in queue_remove_raw()
247 /* High-level queue accessors */
251 cmd[0] |= FIELD_PREP(CMDQ_0_OP, ent->opcode); in arm_smmu_cmdq_build_cmd()
253 switch (ent->opcode) { in arm_smmu_cmdq_build_cmd()
258 cmd[0] |= FIELD_PREP(CMDQ_PREFETCH_0_SID, ent->prefetch.sid); in arm_smmu_cmdq_build_cmd()
261 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SSID, ent->cfgi.ssid); in arm_smmu_cmdq_build_cmd()
264 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid); in arm_smmu_cmdq_build_cmd()
265 cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, ent->cfgi.leaf); in arm_smmu_cmdq_build_cmd()
268 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid); in arm_smmu_cmdq_build_cmd()
275 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); in arm_smmu_cmdq_build_cmd()
278 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num); in arm_smmu_cmdq_build_cmd()
279 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale); in arm_smmu_cmdq_build_cmd()
280 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); in arm_smmu_cmdq_build_cmd()
281 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf); in arm_smmu_cmdq_build_cmd()
282 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl); in arm_smmu_cmdq_build_cmd()
283 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg); in arm_smmu_cmdq_build_cmd()
284 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK; in arm_smmu_cmdq_build_cmd()
287 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num); in arm_smmu_cmdq_build_cmd()
288 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale); in arm_smmu_cmdq_build_cmd()
289 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); in arm_smmu_cmdq_build_cmd()
290 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf); in arm_smmu_cmdq_build_cmd()
291 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl); in arm_smmu_cmdq_build_cmd()
292 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg); in arm_smmu_cmdq_build_cmd()
293 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK; in arm_smmu_cmdq_build_cmd()
296 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); in arm_smmu_cmdq_build_cmd()
300 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); in arm_smmu_cmdq_build_cmd()
303 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); in arm_smmu_cmdq_build_cmd()
306 cmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid); in arm_smmu_cmdq_build_cmd()
307 cmd[0] |= FIELD_PREP(CMDQ_ATC_0_GLOBAL, ent->atc.global); in arm_smmu_cmdq_build_cmd()
308 cmd[0] |= FIELD_PREP(CMDQ_ATC_0_SSID, ent->atc.ssid); in arm_smmu_cmdq_build_cmd()
309 cmd[0] |= FIELD_PREP(CMDQ_ATC_0_SID, ent->atc.sid); in arm_smmu_cmdq_build_cmd()
310 cmd[1] |= FIELD_PREP(CMDQ_ATC_1_SIZE, ent->atc.size); in arm_smmu_cmdq_build_cmd()
311 cmd[1] |= ent->atc.addr & CMDQ_ATC_1_ADDR_MASK; in arm_smmu_cmdq_build_cmd()
314 cmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid); in arm_smmu_cmdq_build_cmd()
315 cmd[0] |= FIELD_PREP(CMDQ_PRI_0_SSID, ent->pri.ssid); in arm_smmu_cmdq_build_cmd()
316 cmd[0] |= FIELD_PREP(CMDQ_PRI_0_SID, ent->pri.sid); in arm_smmu_cmdq_build_cmd()
317 cmd[1] |= FIELD_PREP(CMDQ_PRI_1_GRPID, ent->pri.grpid); in arm_smmu_cmdq_build_cmd()
318 switch (ent->pri.resp) { in arm_smmu_cmdq_build_cmd()
324 return -EINVAL; in arm_smmu_cmdq_build_cmd()
326 cmd[1] |= FIELD_PREP(CMDQ_PRI_1_RESP, ent->pri.resp); in arm_smmu_cmdq_build_cmd()
329 cmd[0] |= FIELD_PREP(CMDQ_RESUME_0_SID, ent->resume.sid); in arm_smmu_cmdq_build_cmd()
330 cmd[0] |= FIELD_PREP(CMDQ_RESUME_0_RESP, ent->resume.resp); in arm_smmu_cmdq_build_cmd()
331 cmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag); in arm_smmu_cmdq_build_cmd()
334 if (ent->sync.msiaddr) { in arm_smmu_cmdq_build_cmd()
336 cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; in arm_smmu_cmdq_build_cmd()
344 return -ENOENT; in arm_smmu_cmdq_build_cmd()
355 if (smmu->impl_ops && smmu->impl_ops->get_secondary_cmdq) in arm_smmu_get_cmdq()
356 cmdq = smmu->impl_ops->get_secondary_cmdq(smmu, ent); in arm_smmu_get_cmdq()
358 return cmdq ?: &smmu->cmdq; in arm_smmu_get_cmdq()
364 if (cmdq == &smmu->cmdq) in arm_smmu_cmdq_needs_busy_polling()
367 return smmu->options & ARM_SMMU_OPT_TEGRA241_CMDQV; in arm_smmu_cmdq_needs_busy_polling()
373 struct arm_smmu_queue *q = &cmdq->q; in arm_smmu_cmdq_build_sync_cmd()
382 if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { in arm_smmu_cmdq_build_sync_cmd()
383 ent.sync.msiaddr = q->base_dma + Q_IDX(&q->llq, prod) * in arm_smmu_cmdq_build_sync_cmd()
384 q->ent_dwords * 8; in arm_smmu_cmdq_build_sync_cmd()
401 struct arm_smmu_queue *q = &cmdq->q; in __arm_smmu_cmdq_skip_err()
405 u32 cons = readl_relaxed(q->cons_reg); in __arm_smmu_cmdq_skip_err()
411 dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, in __arm_smmu_cmdq_skip_err()
416 dev_err(smmu->dev, "retrying command fetch\n"); in __arm_smmu_cmdq_skip_err()
437 queue_read(cmd, Q_ENT(q, cons), q->ent_dwords); in __arm_smmu_cmdq_skip_err()
438 dev_err(smmu->dev, "skipping command in error state:\n"); in __arm_smmu_cmdq_skip_err()
440 dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); in __arm_smmu_cmdq_skip_err()
447 queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); in __arm_smmu_cmdq_skip_err()
452 __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq); in arm_smmu_cmdq_skip_err()
459 * - The only LOCK routines are exclusive_trylock() and shared_lock().
463 * - The UNLOCK routines are supplemented with shared_tryunlock(), which
477 if (atomic_fetch_inc_relaxed(&cmdq->lock) >= 0) in arm_smmu_cmdq_shared_lock()
481 val = atomic_cond_read_relaxed(&cmdq->lock, VAL >= 0); in arm_smmu_cmdq_shared_lock()
482 } while (atomic_cmpxchg_relaxed(&cmdq->lock, val, val + 1) != val); in arm_smmu_cmdq_shared_lock()
487 (void)atomic_dec_return_release(&cmdq->lock); in arm_smmu_cmdq_shared_unlock()
492 if (atomic_read(&cmdq->lock) == 1) in arm_smmu_cmdq_shared_tryunlock()
503 __ret = !atomic_cmpxchg_relaxed(&cmdq->lock, 0, INT_MIN); \
511 atomic_set_release(&cmdq->lock, 0); \
520 * you like mixed-size concurrency, dependency ordering and relaxed atomics,
526 * the time comes. The algorithm is roughly:
560 .max_n_shift = cmdq->q.llq.max_n_shift, in __arm_smmu_cmdq_poll_set_valid_map()
575 ptr = &cmdq->valid_map[swidx]; in __arm_smmu_cmdq_poll_set_valid_map()
580 mask = GENMASK(limit - 1, sbidx); in __arm_smmu_cmdq_poll_set_valid_map()
584 * that a zero-initialised queue is invalid and, after marking in __arm_smmu_cmdq_poll_set_valid_map()
597 llq.prod = queue_inc_prod_n(&llq, limit - sbidx); in __arm_smmu_cmdq_poll_set_valid_map()
615 /* Wait for the command queue to become non-full */
629 WRITE_ONCE(cmdq->q.llq.cons, readl_relaxed(cmdq->q.cons_reg)); in arm_smmu_cmdq_poll_until_not_full()
631 llq->val = READ_ONCE(cmdq->q.llq.val); in arm_smmu_cmdq_poll_until_not_full()
637 llq->val = READ_ONCE(cmdq->q.llq.val); in arm_smmu_cmdq_poll_until_not_full()
657 u32 *cmd = (u32 *)(Q_ENT(&cmdq->q, llq->prod)); in __arm_smmu_cmdq_poll_until_msi()
667 llq->cons = ret ? llq->prod : queue_inc_prod_n(llq, 1); in __arm_smmu_cmdq_poll_until_msi()
672 * Wait until the SMMU cons index passes llq->prod.
680 u32 prod = llq->prod; in __arm_smmu_cmdq_poll_until_consumed()
684 llq->val = READ_ONCE(cmdq->q.llq.val); in __arm_smmu_cmdq_poll_until_consumed()
699 * cmdq->q.llq.cons. Roughly speaking: in __arm_smmu_cmdq_poll_until_consumed()
717 * Requires us to see CPU 0's shared_lock() acquisition. in __arm_smmu_cmdq_poll_until_consumed()
719 llq->cons = readl(cmdq->q.cons_reg); in __arm_smmu_cmdq_poll_until_consumed()
729 if (smmu->options & ARM_SMMU_OPT_MSIPOLL && in arm_smmu_cmdq_poll_until_sync()
741 .max_n_shift = cmdq->q.llq.max_n_shift, in arm_smmu_cmdq_write_entries()
749 queue_write(Q_ENT(&cmdq->q, prod), cmd, CMDQ_ENT_DWORDS); in arm_smmu_cmdq_write_entries()
757 * - There is a dma_wmb() before publishing any commands to the queue.
761 * - On completion of a CMD_SYNC, there is a control dependency.
765 * - Command insertion is totally ordered, so if two CPUs each race to
780 llq.max_n_shift = cmdq->q.llq.max_n_shift; in arm_smmu_cmdq_issue_cmdlist()
784 llq.val = READ_ONCE(cmdq->q.llq.val); in arm_smmu_cmdq_issue_cmdlist()
791 dev_err_ratelimited(smmu->dev, "CMDQ timeout\n"); in arm_smmu_cmdq_issue_cmdlist()
799 old = cmpxchg_relaxed(&cmdq->q.llq.val, llq.val, head.val); in arm_smmu_cmdq_issue_cmdlist()
817 queue_write(Q_ENT(&cmdq->q, prod), cmd_sync, CMDQ_ENT_DWORDS); in arm_smmu_cmdq_issue_cmdlist()
835 atomic_cond_read_relaxed(&cmdq->owner_prod, VAL == llq.prod); in arm_smmu_cmdq_issue_cmdlist()
839 &cmdq->q.llq.atomic.prod); in arm_smmu_cmdq_issue_cmdlist()
853 writel_relaxed(prod, cmdq->q.prod_reg); in arm_smmu_cmdq_issue_cmdlist()
860 atomic_set_release(&cmdq->owner_prod, prod); in arm_smmu_cmdq_issue_cmdlist()
868 dev_err_ratelimited(smmu->dev, in arm_smmu_cmdq_issue_cmdlist()
871 readl_relaxed(cmdq->q.prod_reg), in arm_smmu_cmdq_issue_cmdlist()
872 readl_relaxed(cmdq->q.cons_reg)); in arm_smmu_cmdq_issue_cmdlist()
877 * reader, in which case we can safely update cmdq->q.llq.cons in arm_smmu_cmdq_issue_cmdlist()
880 WRITE_ONCE(cmdq->q.llq.cons, llq.cons); in arm_smmu_cmdq_issue_cmdlist()
896 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", in __arm_smmu_cmdq_issue_cmd()
897 ent->opcode); in __arm_smmu_cmdq_issue_cmd()
898 return -EINVAL; in __arm_smmu_cmdq_issue_cmd()
921 cmds->num = 0; in arm_smmu_cmdq_batch_init()
922 cmds->cmdq = arm_smmu_get_cmdq(smmu, ent); in arm_smmu_cmdq_batch_init()
929 bool unsupported_cmd = !arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd); in arm_smmu_cmdq_batch_add()
930 bool force_sync = (cmds->num == CMDQ_BATCH_ENTRIES - 1) && in arm_smmu_cmdq_batch_add()
931 (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC); in arm_smmu_cmdq_batch_add()
935 arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, in arm_smmu_cmdq_batch_add()
936 cmds->num, true); in arm_smmu_cmdq_batch_add()
940 if (cmds->num == CMDQ_BATCH_ENTRIES) { in arm_smmu_cmdq_batch_add()
941 arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, in arm_smmu_cmdq_batch_add()
942 cmds->num, false); in arm_smmu_cmdq_batch_add()
946 index = cmds->num * CMDQ_ENT_DWORDS; in arm_smmu_cmdq_batch_add()
947 if (unlikely(arm_smmu_cmdq_build_cmd(&cmds->cmds[index], cmd))) { in arm_smmu_cmdq_batch_add()
948 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", in arm_smmu_cmdq_batch_add()
949 cmd->opcode); in arm_smmu_cmdq_batch_add()
953 cmds->num++; in arm_smmu_cmdq_batch_add()
959 return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, in arm_smmu_cmdq_batch_submit()
960 cmds->num, true); in arm_smmu_cmdq_batch_submit()
968 int sid = master->streams[0].id; in arm_smmu_page_response()
970 if (WARN_ON(!master->stall_enabled)) in arm_smmu_page_response()
975 cmd.resume.stag = resp->grpid; in arm_smmu_page_response()
976 switch (resp->code) { in arm_smmu_page_response()
988 arm_smmu_cmdq_issue_cmd(master->smmu, &cmd); in arm_smmu_page_response()
1001 .opcode = smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_asid()
1079 writer->ops->get_used(entry, cur_used); in arm_smmu_entry_qword_diff()
1080 writer->ops->get_used(target, target_used); in arm_smmu_entry_qword_diff()
1110 for (i = start; len != 0; len--, i++) { in entry_set()
1118 writer->ops->sync(writer); in entry_set()
1131 * determine which of three updates are required - disruptive, hitless or no
1135 * - Disrupting the entry (V=0)
1136 * - Fill now unused qwords, execpt qword 0 which contains V
1137 * - Make qword 0 have the final value and valid (V=1) with a single 64
1165 unsigned int critical_qword_index = ffs(used_qword_diff) - 1; in arm_smmu_write_entry()
1185 entry_set(writer, entry, target, 1, NUM_ENTRY_QWORDS - 1); in arm_smmu_write_entry()
1204 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_sync_cd()
1214 for (i = 0; i < master->num_streams; i++) { in arm_smmu_sync_cd()
1215 cmd.cfgi.sid = master->streams[i].id; in arm_smmu_sync_cd()
1228 WRITE_ONCE(dst->l2ptr, cpu_to_le64(val)); in arm_smmu_write_cd_l1_desc()
1233 return le64_to_cpu(src->l2ptr) & CTXDESC_L1_DESC_L2PTR_MASK; in arm_smmu_cd_l1_get_desc()
1240 struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; in arm_smmu_get_cd_ptr()
1245 if (cd_table->s1fmt == STRTAB_STE_0_S1FMT_LINEAR) in arm_smmu_get_cd_ptr()
1246 return &cd_table->linear.table[ssid]; in arm_smmu_get_cd_ptr()
1248 l2 = cd_table->l2.l2ptrs[arm_smmu_cdtab_l1_idx(ssid)]; in arm_smmu_get_cd_ptr()
1251 return &l2->cds[arm_smmu_cdtab_l2_idx(ssid)]; in arm_smmu_get_cd_ptr()
1257 struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; in arm_smmu_alloc_cd_ptr()
1258 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_alloc_cd_ptr()
1261 iommu_group_mutex_assert(master->dev); in arm_smmu_alloc_cd_ptr()
1268 if (cd_table->s1fmt == STRTAB_STE_0_S1FMT_64K_L2) { in arm_smmu_alloc_cd_ptr()
1270 struct arm_smmu_cdtab_l2 **l2ptr = &cd_table->l2.l2ptrs[idx]; in arm_smmu_alloc_cd_ptr()
1275 *l2ptr = dma_alloc_coherent(smmu->dev, sizeof(**l2ptr), in arm_smmu_alloc_cd_ptr()
1280 arm_smmu_write_cd_l1_desc(&cd_table->l2.l1tab[idx], in arm_smmu_alloc_cd_ptr()
1321 arm_smmu_sync_cd(writer->master, cd_writer->ssid, true); in arm_smmu_cd_writer_sync_entry()
1333 bool target_valid = target->data[0] & cpu_to_le64(CTXDESC_CD_0_V); in arm_smmu_write_cd_entry()
1334 bool cur_valid = cdptr->data[0] & cpu_to_le64(CTXDESC_CD_0_V); in arm_smmu_write_cd_entry()
1345 master->cd_table.used_ssids--; in arm_smmu_write_cd_entry()
1347 master->cd_table.used_ssids++; in arm_smmu_write_cd_entry()
1350 arm_smmu_write_entry(&cd_writer.writer, cdptr->data, target->data); in arm_smmu_write_cd_entry()
1357 struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; in arm_smmu_make_s1_cd()
1359 &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; in arm_smmu_make_s1_cd()
1360 typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = in arm_smmu_make_s1_cd()
1361 &pgtbl_cfg->arm_lpae_s1_cfg.tcr; in arm_smmu_make_s1_cd()
1365 target->data[0] = cpu_to_le64( in arm_smmu_make_s1_cd()
1366 FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | in arm_smmu_make_s1_cd()
1367 FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | in arm_smmu_make_s1_cd()
1368 FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | in arm_smmu_make_s1_cd()
1369 FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | in arm_smmu_make_s1_cd()
1370 FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | in arm_smmu_make_s1_cd()
1376 FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | in arm_smmu_make_s1_cd()
1378 (master->stall_enabled ? CTXDESC_CD_0_S : 0) | in arm_smmu_make_s1_cd()
1382 FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) in arm_smmu_make_s1_cd()
1386 if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_HD) in arm_smmu_make_s1_cd()
1387 target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HA | in arm_smmu_make_s1_cd()
1390 target->data[1] = cpu_to_le64(pgtbl_cfg->arm_lpae_s1_cfg.ttbr & in arm_smmu_make_s1_cd()
1392 target->data[3] = cpu_to_le64(pgtbl_cfg->arm_lpae_s1_cfg.mair); in arm_smmu_make_s1_cd()
1401 if (!arm_smmu_cdtab_allocated(&master->cd_table)) in arm_smmu_clear_cd()
1414 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_alloc_cd_tables()
1415 struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; in arm_smmu_alloc_cd_tables()
1417 cd_table->s1cdmax = master->ssid_bits; in arm_smmu_alloc_cd_tables()
1418 max_contexts = 1 << cd_table->s1cdmax; in arm_smmu_alloc_cd_tables()
1420 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || in arm_smmu_alloc_cd_tables()
1422 cd_table->s1fmt = STRTAB_STE_0_S1FMT_LINEAR; in arm_smmu_alloc_cd_tables()
1423 cd_table->linear.num_ents = max_contexts; in arm_smmu_alloc_cd_tables()
1426 cd_table->linear.table = dma_alloc_coherent(smmu->dev, l1size, in arm_smmu_alloc_cd_tables()
1427 &cd_table->cdtab_dma, in arm_smmu_alloc_cd_tables()
1429 if (!cd_table->linear.table) in arm_smmu_alloc_cd_tables()
1430 return -ENOMEM; in arm_smmu_alloc_cd_tables()
1432 cd_table->s1fmt = STRTAB_STE_0_S1FMT_64K_L2; in arm_smmu_alloc_cd_tables()
1433 cd_table->l2.num_l1_ents = in arm_smmu_alloc_cd_tables()
1436 cd_table->l2.l2ptrs = kcalloc(cd_table->l2.num_l1_ents, in arm_smmu_alloc_cd_tables()
1437 sizeof(*cd_table->l2.l2ptrs), in arm_smmu_alloc_cd_tables()
1439 if (!cd_table->l2.l2ptrs) in arm_smmu_alloc_cd_tables()
1440 return -ENOMEM; in arm_smmu_alloc_cd_tables()
1442 l1size = cd_table->l2.num_l1_ents * sizeof(struct arm_smmu_cdtab_l1); in arm_smmu_alloc_cd_tables()
1443 cd_table->l2.l1tab = dma_alloc_coherent(smmu->dev, l1size, in arm_smmu_alloc_cd_tables()
1444 &cd_table->cdtab_dma, in arm_smmu_alloc_cd_tables()
1446 if (!cd_table->l2.l2ptrs) { in arm_smmu_alloc_cd_tables()
1447 ret = -ENOMEM; in arm_smmu_alloc_cd_tables()
1454 kfree(cd_table->l2.l2ptrs); in arm_smmu_alloc_cd_tables()
1455 cd_table->l2.l2ptrs = NULL; in arm_smmu_alloc_cd_tables()
1462 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_free_cd_tables()
1463 struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; in arm_smmu_free_cd_tables()
1465 if (cd_table->s1fmt != STRTAB_STE_0_S1FMT_LINEAR) { in arm_smmu_free_cd_tables()
1466 for (i = 0; i < cd_table->l2.num_l1_ents; i++) { in arm_smmu_free_cd_tables()
1467 if (!cd_table->l2.l2ptrs[i]) in arm_smmu_free_cd_tables()
1470 dma_free_coherent(smmu->dev, in arm_smmu_free_cd_tables()
1471 sizeof(*cd_table->l2.l2ptrs[i]), in arm_smmu_free_cd_tables()
1472 cd_table->l2.l2ptrs[i], in arm_smmu_free_cd_tables()
1473 arm_smmu_cd_l1_get_desc(&cd_table->l2.l1tab[i])); in arm_smmu_free_cd_tables()
1475 kfree(cd_table->l2.l2ptrs); in arm_smmu_free_cd_tables()
1477 dma_free_coherent(smmu->dev, in arm_smmu_free_cd_tables()
1478 cd_table->l2.num_l1_ents * in arm_smmu_free_cd_tables()
1480 cd_table->l2.l1tab, cd_table->cdtab_dma); in arm_smmu_free_cd_tables()
1482 dma_free_coherent(smmu->dev, in arm_smmu_free_cd_tables()
1483 cd_table->linear.num_ents * in arm_smmu_free_cd_tables()
1485 cd_table->linear.table, cd_table->cdtab_dma); in arm_smmu_free_cd_tables()
1499 WRITE_ONCE(dst->l2ptr, cpu_to_le64(val)); in arm_smmu_write_strtab_l1_desc()
1514 .sid = ste_writer->sid, in arm_smmu_ste_writer_sync_entry()
1519 arm_smmu_cmdq_issue_cmd_with_sync(writer->master->smmu, &cmd); in arm_smmu_ste_writer_sync_entry()
1531 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_write_ste()
1540 arm_smmu_write_entry(&ste_writer.writer, ste->data, target->data); in arm_smmu_write_ste()
1543 if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) { in arm_smmu_write_ste()
1557 target->data[0] = cpu_to_le64( in arm_smmu_make_abort_ste()
1568 target->data[0] = cpu_to_le64( in arm_smmu_make_bypass_ste()
1572 if (smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR) in arm_smmu_make_bypass_ste()
1573 target->data[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG, in arm_smmu_make_bypass_ste()
1583 struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; in arm_smmu_make_cdtable_ste()
1584 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_make_cdtable_ste()
1587 target->data[0] = cpu_to_le64( in arm_smmu_make_cdtable_ste()
1590 FIELD_PREP(STRTAB_STE_0_S1FMT, cd_table->s1fmt) | in arm_smmu_make_cdtable_ste()
1591 (cd_table->cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) | in arm_smmu_make_cdtable_ste()
1592 FIELD_PREP(STRTAB_STE_0_S1CDMAX, cd_table->s1cdmax)); in arm_smmu_make_cdtable_ste()
1594 target->data[1] = cpu_to_le64( in arm_smmu_make_cdtable_ste()
1599 ((smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_make_cdtable_ste()
1600 !master->stall_enabled) ? in arm_smmu_make_cdtable_ste()
1606 if ((smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR) && in arm_smmu_make_cdtable_ste()
1608 target->data[1] |= cpu_to_le64(FIELD_PREP( in arm_smmu_make_cdtable_ste()
1611 if (smmu->features & ARM_SMMU_FEAT_E2H) { in arm_smmu_make_cdtable_ste()
1615 * properly matched. This means either S/NS-EL2-E2H (hypervisor) in arm_smmu_make_cdtable_ste()
1616 * or NS-EL1 (guest). Since an SVA domain can be installed in a in arm_smmu_make_cdtable_ste()
1620 target->data[1] |= cpu_to_le64( in arm_smmu_make_cdtable_ste()
1623 target->data[1] |= cpu_to_le64( in arm_smmu_make_cdtable_ste()
1627 * VMID 0 is reserved for stage-2 bypass EL1 STEs, see in arm_smmu_make_cdtable_ste()
1630 target->data[2] = in arm_smmu_make_cdtable_ste()
1641 struct arm_smmu_s2_cfg *s2_cfg = &smmu_domain->s2_cfg; in arm_smmu_make_s2_domain_ste()
1643 &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; in arm_smmu_make_s2_domain_ste()
1644 typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr = in arm_smmu_make_s2_domain_ste()
1645 &pgtbl_cfg->arm_lpae_s2_cfg.vtcr; in arm_smmu_make_s2_domain_ste()
1647 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_make_s2_domain_ste()
1650 target->data[0] = cpu_to_le64( in arm_smmu_make_s2_domain_ste()
1654 target->data[1] = cpu_to_le64( in arm_smmu_make_s2_domain_ste()
1658 if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_S2FWB) in arm_smmu_make_s2_domain_ste()
1659 target->data[1] |= cpu_to_le64(STRTAB_STE_1_S2FWB); in arm_smmu_make_s2_domain_ste()
1660 if (smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR) in arm_smmu_make_s2_domain_ste()
1661 target->data[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG, in arm_smmu_make_s2_domain_ste()
1664 vtcr_val = FIELD_PREP(STRTAB_STE_2_VTCR_S2T0SZ, vtcr->tsz) | in arm_smmu_make_s2_domain_ste()
1665 FIELD_PREP(STRTAB_STE_2_VTCR_S2SL0, vtcr->sl) | in arm_smmu_make_s2_domain_ste()
1666 FIELD_PREP(STRTAB_STE_2_VTCR_S2IR0, vtcr->irgn) | in arm_smmu_make_s2_domain_ste()
1667 FIELD_PREP(STRTAB_STE_2_VTCR_S2OR0, vtcr->orgn) | in arm_smmu_make_s2_domain_ste()
1668 FIELD_PREP(STRTAB_STE_2_VTCR_S2SH0, vtcr->sh) | in arm_smmu_make_s2_domain_ste()
1669 FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, vtcr->tg) | in arm_smmu_make_s2_domain_ste()
1670 FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, vtcr->ps); in arm_smmu_make_s2_domain_ste()
1671 target->data[2] = cpu_to_le64( in arm_smmu_make_s2_domain_ste()
1672 FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | in arm_smmu_make_s2_domain_ste()
1679 (master->stall_enabled ? STRTAB_STE_2_S2S : 0) | in arm_smmu_make_s2_domain_ste()
1682 target->data[3] = cpu_to_le64(pgtbl_cfg->arm_lpae_s2_cfg.vttbr & in arm_smmu_make_s2_domain_ste()
1705 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_l2_strtab()
1708 l2table = &cfg->l2.l2ptrs[arm_smmu_strtab_l1_idx(sid)]; in arm_smmu_init_l2_strtab()
1712 *l2table = dmam_alloc_coherent(smmu->dev, sizeof(**l2table), in arm_smmu_init_l2_strtab()
1715 dev_err(smmu->dev, in arm_smmu_init_l2_strtab()
1718 return -ENOMEM; in arm_smmu_init_l2_strtab()
1721 arm_smmu_init_initial_stes((*l2table)->stes, in arm_smmu_init_l2_strtab()
1722 ARRAY_SIZE((*l2table)->stes)); in arm_smmu_init_l2_strtab()
1723 arm_smmu_write_strtab_l1_desc(&cfg->l2.l1tab[arm_smmu_strtab_l1_idx(sid)], in arm_smmu_init_l2_strtab()
1734 if (*sid_lhs < stream_rhs->id) in arm_smmu_streams_cmp_key()
1735 return -1; in arm_smmu_streams_cmp_key()
1736 if (*sid_lhs > stream_rhs->id) in arm_smmu_streams_cmp_key()
1745 &rb_entry(lhs, struct arm_smmu_stream, node)->id, rhs); in arm_smmu_streams_cmp_node()
1753 lockdep_assert_held(&smmu->streams_mutex); in arm_smmu_find_master()
1755 node = rb_find(&sid, &smmu->streams, arm_smmu_streams_cmp_key); in arm_smmu_find_master()
1758 return rb_entry(node, struct arm_smmu_stream, node)->master; in arm_smmu_find_master()
1779 return -EOPNOTSUPP; in arm_smmu_handle_evt()
1783 return -EOPNOTSUPP; in arm_smmu_handle_evt()
1796 flt->type = IOMMU_FAULT_PAGE_REQ; in arm_smmu_handle_evt()
1797 flt->prm = (struct iommu_fault_page_request) { in arm_smmu_handle_evt()
1805 flt->prm.flags |= IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; in arm_smmu_handle_evt()
1806 flt->prm.pasid = FIELD_GET(EVTQ_0_SSID, evt[0]); in arm_smmu_handle_evt()
1809 mutex_lock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1812 ret = -EINVAL; in arm_smmu_handle_evt()
1816 ret = iommu_report_device_fault(master->dev, &fault_evt); in arm_smmu_handle_evt()
1818 mutex_unlock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1826 struct arm_smmu_queue *q = &smmu->evtq.q; in arm_smmu_evtq_thread()
1827 struct arm_smmu_ll_queue *llq = &q->llq; in arm_smmu_evtq_thread()
1840 dev_info(smmu->dev, "event 0x%02x received:\n", id); in arm_smmu_evtq_thread()
1842 dev_info(smmu->dev, "\t0x%016llx\n", in arm_smmu_evtq_thread()
1852 if (queue_sync_prod_in(q) == -EOVERFLOW) in arm_smmu_evtq_thread()
1853 dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n"); in arm_smmu_evtq_thread()
1873 dev_info(smmu->dev, "unexpected PRI request received:\n"); in arm_smmu_handle_ppr()
1874 dev_info(smmu->dev, in arm_smmu_handle_ppr()
1902 struct arm_smmu_queue *q = &smmu->priq.q; in arm_smmu_priq_thread()
1903 struct arm_smmu_ll_queue *llq = &q->llq; in arm_smmu_priq_thread()
1910 if (queue_sync_prod_in(q) == -EOVERFLOW) in arm_smmu_priq_thread()
1911 dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n"); in arm_smmu_priq_thread()
1926 gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); in arm_smmu_gerror_handler()
1927 gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1933 dev_warn(smmu->dev, in arm_smmu_gerror_handler()
1938 dev_err(smmu->dev, "device has entered Service Failure Mode!\n"); in arm_smmu_gerror_handler()
1943 dev_warn(smmu->dev, "GERROR MSI write aborted\n"); in arm_smmu_gerror_handler()
1946 dev_warn(smmu->dev, "PRIQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1949 dev_warn(smmu->dev, "EVTQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1952 dev_warn(smmu->dev, "CMDQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1955 dev_err(smmu->dev, "PRIQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1958 dev_err(smmu->dev, "EVTQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1963 writel(gerror, smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1972 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_combined_irq_thread()
1990 /* ATC invalidates are always on 4096-bytes pages */ in arm_smmu_atc_inv_to_cmd()
2002 * When using STRTAB_STE_1_S1DSS_SSID0 (reserving CD 0 for non-PASID in arm_smmu_atc_inv_to_cmd()
2005 * This has the unpleasant side-effect of invalidating all PASID-tagged in arm_smmu_atc_inv_to_cmd()
2015 cmd->atc.size = ATC_INV_SIZE_ALL; in arm_smmu_atc_inv_to_cmd()
2020 page_end = (iova + size - 1) >> inval_grain_shift; in arm_smmu_atc_inv_to_cmd()
2025 * thus have to choose between grossly over-invalidating the region, or in arm_smmu_atc_inv_to_cmd()
2043 span_mask = (1ULL << log2_span) - 1; in arm_smmu_atc_inv_to_cmd()
2047 cmd->atc.addr = page_start << inval_grain_shift; in arm_smmu_atc_inv_to_cmd()
2048 cmd->atc.size = log2_span; in arm_smmu_atc_inv_to_cmd()
2060 arm_smmu_cmdq_batch_init(master->smmu, &cmds, &cmd); in arm_smmu_atc_inv_master()
2061 for (i = 0; i < master->num_streams; i++) { in arm_smmu_atc_inv_master()
2062 cmd.atc.sid = master->streams[i].id; in arm_smmu_atc_inv_master()
2063 arm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd); in arm_smmu_atc_inv_master()
2066 return arm_smmu_cmdq_batch_submit(master->smmu, &cmds); in arm_smmu_atc_inv_master()
2080 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_atc_inv_domain()
2097 if (!atomic_read(&smmu_domain->nr_ats_masters)) in arm_smmu_atc_inv_domain()
2100 arm_smmu_cmdq_batch_init(smmu_domain->smmu, &cmds, &cmd); in arm_smmu_atc_inv_domain()
2102 spin_lock_irqsave(&smmu_domain->devices_lock, flags); in arm_smmu_atc_inv_domain()
2103 list_for_each_entry(master_domain, &smmu_domain->devices, in arm_smmu_atc_inv_domain()
2105 struct arm_smmu_master *master = master_domain->master; in arm_smmu_atc_inv_domain()
2107 if (!master->ats_enabled) in arm_smmu_atc_inv_domain()
2110 if (master_domain->nested_ats_flush) { in arm_smmu_atc_inv_domain()
2117 arm_smmu_atc_inv_to_cmd(master_domain->ssid, iova, size, in arm_smmu_atc_inv_domain()
2121 for (i = 0; i < master->num_streams; i++) { in arm_smmu_atc_inv_domain()
2122 cmd.atc.sid = master->streams[i].id; in arm_smmu_atc_inv_domain()
2123 arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); in arm_smmu_atc_inv_domain()
2126 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); in arm_smmu_atc_inv_domain()
2128 return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds); in arm_smmu_atc_inv_domain()
2135 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_context()
2139 * NOTE: when io-pgtable is in non-strict mode, we may get here with in arm_smmu_tlb_inv_context()
2145 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { in arm_smmu_tlb_inv_context()
2146 arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); in arm_smmu_tlb_inv_context()
2149 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; in arm_smmu_tlb_inv_context()
2160 struct arm_smmu_device *smmu = smmu_domain->smmu; in __arm_smmu_tlb_inv_range()
2168 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
2170 tg = __ffs(smmu_domain->domain.pgsize_bitmap); in __arm_smmu_tlb_inv_range()
2175 cmd->tlbi.tg = (tg - 10) / 2; in __arm_smmu_tlb_inv_range()
2178 * Determine what level the granule is at. For non-leaf, both in __arm_smmu_tlb_inv_range()
2179 * io-pgtable and SVA pass a nominal last-level granule because in __arm_smmu_tlb_inv_range()
2185 if (cmd->tlbi.leaf) in __arm_smmu_tlb_inv_range()
2186 cmd->tlbi.ttl = 4 - ((ilog2(granule) - 3) / (tg - 3)); in __arm_smmu_tlb_inv_range()
2194 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
2206 cmd->tlbi.scale = scale; in __arm_smmu_tlb_inv_range()
2210 cmd->tlbi.num = num - 1; in __arm_smmu_tlb_inv_range()
2216 num_pages -= num << scale; in __arm_smmu_tlb_inv_range()
2219 cmd->tlbi.addr = iova; in __arm_smmu_tlb_inv_range()
2236 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { in arm_smmu_tlb_inv_range_domain()
2237 cmd.opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_domain()
2239 cmd.tlbi.asid = smmu_domain->cd.asid; in arm_smmu_tlb_inv_range_domain()
2242 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; in arm_smmu_tlb_inv_range_domain()
2246 if (smmu_domain->nest_parent) { in arm_smmu_tlb_inv_range_domain()
2252 arm_smmu_cmdq_issue_cmd_with_sync(smmu_domain->smmu, &cmd); in arm_smmu_tlb_inv_range_domain()
2256 * Unfortunately, this can't be leaf-only since we may have in arm_smmu_tlb_inv_range_domain()
2267 .opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_asid()
2283 struct iommu_domain *domain = &smmu_domain->domain; in arm_smmu_tlb_inv_page_nosync()
2304 return (smmu->features & features) == features; in arm_smmu_dbm_capable()
2315 return master->smmu->features & ARM_SMMU_FEAT_COHERENCY; in arm_smmu_capable()
2322 return arm_smmu_dbm_capable(master->smmu); in arm_smmu_capable()
2335 spin_lock_irqsave(&smmu_domain->devices_lock, flags); in arm_smmu_enforce_cache_coherency()
2336 list_for_each_entry(master_domain, &smmu_domain->devices, in arm_smmu_enforce_cache_coherency()
2338 if (!arm_smmu_master_canwbs(master_domain->master)) { in arm_smmu_enforce_cache_coherency()
2343 smmu_domain->enforce_cache_coherency = ret; in arm_smmu_enforce_cache_coherency()
2344 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); in arm_smmu_enforce_cache_coherency()
2354 return ERR_PTR(-ENOMEM); in arm_smmu_domain_alloc()
2356 mutex_init(&smmu_domain->init_mutex); in arm_smmu_domain_alloc()
2357 INIT_LIST_HEAD(&smmu_domain->devices); in arm_smmu_domain_alloc()
2358 spin_lock_init(&smmu_domain->devices_lock); in arm_smmu_domain_alloc()
2380 ret = arm_smmu_domain_finalise(smmu_domain, master->smmu, 0); in arm_smmu_domain_alloc_paging()
2386 return &smmu_domain->domain; in arm_smmu_domain_alloc_paging()
2392 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_free_paging()
2394 free_io_pgtable_ops(smmu_domain->pgtbl_ops); in arm_smmu_domain_free_paging()
2397 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { in arm_smmu_domain_free_paging()
2400 xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); in arm_smmu_domain_free_paging()
2403 struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; in arm_smmu_domain_free_paging()
2404 if (cfg->vmid) in arm_smmu_domain_free_paging()
2405 ida_free(&smmu->vmid_map, cfg->vmid); in arm_smmu_domain_free_paging()
2416 struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; in arm_smmu_domain_finalise_s1()
2421 XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); in arm_smmu_domain_finalise_s1()
2422 cd->asid = (u16)asid; in arm_smmu_domain_finalise_s1()
2431 struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; in arm_smmu_domain_finalise_s2()
2433 /* Reserve VMID 0 for stage-2 bypass STEs */ in arm_smmu_domain_finalise_s2()
2434 vmid = ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, in arm_smmu_domain_finalise_s2()
2439 cfg->vmid = (u16)vmid; in arm_smmu_domain_finalise_s2()
2455 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) in arm_smmu_domain_finalise()
2456 smmu_domain->stage = ARM_SMMU_DOMAIN_S2; in arm_smmu_domain_finalise()
2457 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_domain_finalise()
2458 smmu_domain->stage = ARM_SMMU_DOMAIN_S1; in arm_smmu_domain_finalise()
2461 .pgsize_bitmap = smmu->pgsize_bitmap, in arm_smmu_domain_finalise()
2462 .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENCY, in arm_smmu_domain_finalise()
2464 .iommu_dev = smmu->dev, in arm_smmu_domain_finalise()
2467 switch (smmu_domain->stage) { in arm_smmu_domain_finalise()
2469 unsigned long ias = (smmu->features & in arm_smmu_domain_finalise()
2473 pgtbl_cfg.oas = smmu->ias; in arm_smmu_domain_finalise()
2482 return -EOPNOTSUPP; in arm_smmu_domain_finalise()
2483 pgtbl_cfg.ias = smmu->ias; in arm_smmu_domain_finalise()
2484 pgtbl_cfg.oas = smmu->oas; in arm_smmu_domain_finalise()
2487 if ((smmu->features & ARM_SMMU_FEAT_S2FWB) && in arm_smmu_domain_finalise()
2492 return -EINVAL; in arm_smmu_domain_finalise()
2497 return -ENOMEM; in arm_smmu_domain_finalise()
2499 smmu_domain->domain.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; in arm_smmu_domain_finalise()
2500 smmu_domain->domain.geometry.aperture_end = (1UL << pgtbl_cfg.ias) - 1; in arm_smmu_domain_finalise()
2501 smmu_domain->domain.geometry.force_aperture = true; in arm_smmu_domain_finalise()
2502 if (enable_dirty && smmu_domain->stage == ARM_SMMU_DOMAIN_S1) in arm_smmu_domain_finalise()
2503 smmu_domain->domain.dirty_ops = &arm_smmu_dirty_ops; in arm_smmu_domain_finalise()
2511 smmu_domain->pgtbl_ops = pgtbl_ops; in arm_smmu_domain_finalise()
2512 smmu_domain->smmu = smmu; in arm_smmu_domain_finalise()
2519 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_get_step_for_sid()
2521 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { in arm_smmu_get_step_for_sid()
2522 /* Two-level walk */ in arm_smmu_get_step_for_sid()
2523 return &cfg->l2.l2ptrs[arm_smmu_strtab_l1_idx(sid)] in arm_smmu_get_step_for_sid()
2524 ->stes[arm_smmu_strtab_l2_idx(sid)]; in arm_smmu_get_step_for_sid()
2527 return &cfg->linear.table[sid]; in arm_smmu_get_step_for_sid()
2535 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_install_ste_for_dev()
2537 master->cd_table.in_ste = in arm_smmu_install_ste_for_dev()
2538 FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(target->data[0])) == in arm_smmu_install_ste_for_dev()
2540 master->ste_ats_enabled = in arm_smmu_install_ste_for_dev()
2541 FIELD_GET(STRTAB_STE_1_EATS, le64_to_cpu(target->data[1])) == in arm_smmu_install_ste_for_dev()
2544 for (i = 0; i < master->num_streams; ++i) { in arm_smmu_install_ste_for_dev()
2545 u32 sid = master->streams[i].id; in arm_smmu_install_ste_for_dev()
2551 if (master->streams[j].id == sid) in arm_smmu_install_ste_for_dev()
2562 struct device *dev = master->dev; in arm_smmu_ats_supported()
2563 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_ats_supported()
2566 if (!(smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_ats_supported()
2569 if (!(fwspec->flags & IOMMU_FWSPEC_PCI_RC_ATS)) in arm_smmu_ats_supported()
2579 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_enable_ats()
2582 stu = __ffs(smmu->pgsize_bitmap); in arm_smmu_enable_ats()
2583 pdev = to_pci_dev(master->dev); in arm_smmu_enable_ats()
2590 dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu); in arm_smmu_enable_ats()
2600 if (!dev_is_pci(master->dev)) in arm_smmu_enable_pasid()
2601 return -ENODEV; in arm_smmu_enable_pasid()
2603 pdev = to_pci_dev(master->dev); in arm_smmu_enable_pasid()
2615 dev_err(&pdev->dev, "Failed to enable PASID\n"); in arm_smmu_enable_pasid()
2619 master->ssid_bits = min_t(u8, ilog2(num_pasids), in arm_smmu_enable_pasid()
2620 master->smmu->ssid_bits); in arm_smmu_enable_pasid()
2628 if (!dev_is_pci(master->dev)) in arm_smmu_disable_pasid()
2631 pdev = to_pci_dev(master->dev); in arm_smmu_disable_pasid()
2633 if (!pdev->pasid_enabled) in arm_smmu_disable_pasid()
2636 master->ssid_bits = 0; in arm_smmu_disable_pasid()
2647 lockdep_assert_held(&smmu_domain->devices_lock); in arm_smmu_find_master_domain()
2649 list_for_each_entry(master_domain, &smmu_domain->devices, in arm_smmu_find_master_domain()
2651 if (master_domain->master == master && in arm_smmu_find_master_domain()
2652 master_domain->ssid == ssid && in arm_smmu_find_master_domain()
2653 master_domain->nested_ats_flush == nested_ats_flush) in arm_smmu_find_master_domain()
2660 * If the domain uses the smmu_domain->devices list return the arm_smmu_domain
2670 if ((domain->type & __IOMMU_DOMAIN_PAGING) || in to_smmu_domain_devices()
2671 domain->type == IOMMU_DOMAIN_SVA) in to_smmu_domain_devices()
2673 if (domain->type == IOMMU_DOMAIN_NESTED) in to_smmu_domain_devices()
2674 return to_smmu_nested_domain(domain)->vsmmu->s2_parent; in to_smmu_domain_devices()
2690 if (domain->type == IOMMU_DOMAIN_NESTED) in arm_smmu_remove_master_domain()
2691 nested_ats_flush = to_smmu_nested_domain(domain)->enable_ats; in arm_smmu_remove_master_domain()
2693 spin_lock_irqsave(&smmu_domain->devices_lock, flags); in arm_smmu_remove_master_domain()
2697 list_del(&master_domain->devices_elm); in arm_smmu_remove_master_domain()
2699 if (master->ats_enabled) in arm_smmu_remove_master_domain()
2700 atomic_dec(&smmu_domain->nr_ats_masters); in arm_smmu_remove_master_domain()
2702 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); in arm_smmu_remove_master_domain()
2722 * new_domain can be a non-paging domain. In this case ATS will not be enabled,
2728 struct arm_smmu_master *master = state->master; in arm_smmu_attach_prepare()
2741 if (smmu_domain || state->cd_needs_ats) { in arm_smmu_attach_prepare()
2752 state->ats_enabled = !state->disable_ats && in arm_smmu_attach_prepare()
2759 return -ENOMEM; in arm_smmu_attach_prepare()
2760 master_domain->master = master; in arm_smmu_attach_prepare()
2761 master_domain->ssid = state->ssid; in arm_smmu_attach_prepare()
2762 if (new_domain->type == IOMMU_DOMAIN_NESTED) in arm_smmu_attach_prepare()
2763 master_domain->nested_ats_flush = in arm_smmu_attach_prepare()
2764 to_smmu_nested_domain(new_domain)->enable_ats; in arm_smmu_attach_prepare()
2776 * Notice if we are re-attaching the same domain then the list in arm_smmu_attach_prepare()
2780 spin_lock_irqsave(&smmu_domain->devices_lock, flags); in arm_smmu_attach_prepare()
2781 if (smmu_domain->enforce_cache_coherency && in arm_smmu_attach_prepare()
2783 spin_unlock_irqrestore(&smmu_domain->devices_lock, in arm_smmu_attach_prepare()
2786 return -EINVAL; in arm_smmu_attach_prepare()
2789 if (state->ats_enabled) in arm_smmu_attach_prepare()
2790 atomic_inc(&smmu_domain->nr_ats_masters); in arm_smmu_attach_prepare()
2791 list_add(&master_domain->devices_elm, &smmu_domain->devices); in arm_smmu_attach_prepare()
2792 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); in arm_smmu_attach_prepare()
2795 if (!state->ats_enabled && master->ats_enabled) { in arm_smmu_attach_prepare()
2796 pci_disable_ats(to_pci_dev(master->dev)); in arm_smmu_attach_prepare()
2810 * smmu_domain->devices list.
2814 struct arm_smmu_master *master = state->master; in arm_smmu_attach_commit()
2818 if (state->ats_enabled && !master->ats_enabled) { in arm_smmu_attach_commit()
2820 } else if (state->ats_enabled && master->ats_enabled) { in arm_smmu_attach_commit()
2826 arm_smmu_atc_inv_master(master, state->ssid); in arm_smmu_attach_commit()
2827 } else if (!state->ats_enabled && master->ats_enabled) { in arm_smmu_attach_commit()
2831 master->ats_enabled = state->ats_enabled; in arm_smmu_attach_commit()
2833 arm_smmu_remove_master_domain(master, state->old_domain, state->ssid); in arm_smmu_attach_commit()
2851 return -ENOENT; in arm_smmu_attach_dev()
2854 smmu = master->smmu; in arm_smmu_attach_dev()
2856 mutex_lock(&smmu_domain->init_mutex); in arm_smmu_attach_dev()
2858 if (!smmu_domain->smmu) { in arm_smmu_attach_dev()
2860 } else if (smmu_domain->smmu != smmu) in arm_smmu_attach_dev()
2861 ret = -EINVAL; in arm_smmu_attach_dev()
2863 mutex_unlock(&smmu_domain->init_mutex); in arm_smmu_attach_dev()
2867 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { in arm_smmu_attach_dev()
2870 return -ENOMEM; in arm_smmu_attach_dev()
2871 } else if (arm_smmu_ssids_in_use(&master->cd_table)) in arm_smmu_attach_dev()
2872 return -EBUSY; in arm_smmu_attach_dev()
2877 * This allows the STE and the smmu_domain->devices list to in arm_smmu_attach_dev()
2888 switch (smmu_domain->stage) { in arm_smmu_attach_dev()
2919 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_s1_set_dev_pasid()
2923 mutex_lock(&smmu_domain->init_mutex); in arm_smmu_s1_set_dev_pasid()
2924 if (!smmu_domain->smmu) in arm_smmu_s1_set_dev_pasid()
2926 else if (smmu_domain->smmu != smmu) in arm_smmu_s1_set_dev_pasid()
2927 ret = -EINVAL; in arm_smmu_s1_set_dev_pasid()
2928 mutex_unlock(&smmu_domain->init_mutex); in arm_smmu_s1_set_dev_pasid()
2932 if (smmu_domain->stage != ARM_SMMU_DOMAIN_S1) in arm_smmu_s1_set_dev_pasid()
2933 return -EINVAL; in arm_smmu_s1_set_dev_pasid()
2951 if (master->cd_table.in_ste && master->ste_ats_enabled == ats_enabled) in arm_smmu_update_ste()
2954 if (sid_domain->type == IOMMU_DOMAIN_IDENTITY) in arm_smmu_update_ste()
2957 WARN_ON(sid_domain->type != IOMMU_DOMAIN_BLOCKED); in arm_smmu_update_ste()
2973 struct iommu_domain *sid_domain = iommu_get_domain_for_dev(master->dev); in arm_smmu_set_pasid()
2984 if (smmu_domain->smmu != master->smmu) in arm_smmu_set_pasid()
2985 return -EINVAL; in arm_smmu_set_pasid()
2987 if (!master->cd_table.in_ste && in arm_smmu_set_pasid()
2988 sid_domain->type != IOMMU_DOMAIN_IDENTITY && in arm_smmu_set_pasid()
2989 sid_domain->type != IOMMU_DOMAIN_BLOCKED) in arm_smmu_set_pasid()
2990 return -EINVAL; in arm_smmu_set_pasid()
2994 return -ENOMEM; in arm_smmu_set_pasid()
2997 ret = arm_smmu_attach_prepare(&state, &smmu_domain->domain); in arm_smmu_set_pasid()
3005 cd->data[0] &= ~cpu_to_le64(CTXDESC_CD_0_ASID); in arm_smmu_set_pasid()
3006 cd->data[0] |= cpu_to_le64( in arm_smmu_set_pasid()
3007 FIELD_PREP(CTXDESC_CD_0_ASID, smmu_domain->cd.asid)); in arm_smmu_set_pasid()
3029 if (master->ats_enabled) in arm_smmu_remove_dev_pasid()
3031 arm_smmu_remove_master_domain(master, &smmu_domain->domain, pasid); in arm_smmu_remove_dev_pasid()
3036 * to a non-cd_table one. in arm_smmu_remove_dev_pasid()
3038 if (!arm_smmu_ssids_in_use(&master->cd_table)) { in arm_smmu_remove_dev_pasid()
3040 iommu_get_domain_for_dev(master->dev); in arm_smmu_remove_dev_pasid()
3042 if (sid_domain->type == IOMMU_DOMAIN_IDENTITY || in arm_smmu_remove_dev_pasid()
3043 sid_domain->type == IOMMU_DOMAIN_BLOCKED) in arm_smmu_remove_dev_pasid()
3044 sid_domain->ops->attach_dev(sid_domain, dev); in arm_smmu_remove_dev_pasid()
3070 if (arm_smmu_ssids_in_use(&master->cd_table)) { in arm_smmu_attach_dev_ste()
3088 * arm_smmu_domain->devices to avoid races updating the same context in arm_smmu_attach_dev_ste()
3100 arm_smmu_make_bypass_ste(master->smmu, &ste); in arm_smmu_attach_dev_identity()
3146 return ERR_PTR(-EOPNOTSUPP); in arm_smmu_domain_alloc_paging_flags()
3148 return ERR_PTR(-EOPNOTSUPP); in arm_smmu_domain_alloc_paging_flags()
3158 if (!(master->smmu->features & ARM_SMMU_FEAT_NESTING)) { in arm_smmu_domain_alloc_paging_flags()
3159 ret = -EOPNOTSUPP; in arm_smmu_domain_alloc_paging_flags()
3162 smmu_domain->stage = ARM_SMMU_DOMAIN_S2; in arm_smmu_domain_alloc_paging_flags()
3163 smmu_domain->nest_parent = true; in arm_smmu_domain_alloc_paging_flags()
3166 smmu_domain->domain.type = IOMMU_DOMAIN_UNMANAGED; in arm_smmu_domain_alloc_paging_flags()
3167 smmu_domain->domain.ops = arm_smmu_ops.default_domain_ops; in arm_smmu_domain_alloc_paging_flags()
3168 ret = arm_smmu_domain_finalise(smmu_domain, master->smmu, flags); in arm_smmu_domain_alloc_paging_flags()
3171 return &smmu_domain->domain; in arm_smmu_domain_alloc_paging_flags()
3182 struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops; in arm_smmu_map_pages()
3185 return -ENODEV; in arm_smmu_map_pages()
3187 return ops->map_pages(ops, iova, paddr, pgsize, pgcount, prot, gfp, mapped); in arm_smmu_map_pages()
3195 struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; in arm_smmu_unmap_pages()
3200 return ops->unmap_pages(ops, iova, pgsize, pgcount, gather); in arm_smmu_unmap_pages()
3207 if (smmu_domain->smmu) in arm_smmu_flush_iotlb_all()
3216 if (!gather->pgsize) in arm_smmu_iotlb_sync()
3219 arm_smmu_tlb_inv_range_domain(gather->start, in arm_smmu_iotlb_sync()
3220 gather->end - gather->start + 1, in arm_smmu_iotlb_sync()
3221 gather->pgsize, true, smmu_domain); in arm_smmu_iotlb_sync()
3227 struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops; in arm_smmu_iova_to_phys()
3232 return ops->iova_to_phys(ops, iova); in arm_smmu_iova_to_phys()
3248 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_sid_in_range()
3249 return arm_smmu_strtab_l1_idx(sid) < smmu->strtab_cfg.l2.num_l1_ents; in arm_smmu_sid_in_range()
3250 return sid < smmu->strtab_cfg.linear.num_ents; in arm_smmu_sid_in_range()
3257 return -ERANGE; in arm_smmu_init_sid_strtab()
3260 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_init_sid_strtab()
3271 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); in arm_smmu_insert_master()
3273 master->streams = kcalloc(fwspec->num_ids, sizeof(*master->streams), in arm_smmu_insert_master()
3275 if (!master->streams) in arm_smmu_insert_master()
3276 return -ENOMEM; in arm_smmu_insert_master()
3277 master->num_streams = fwspec->num_ids; in arm_smmu_insert_master()
3279 mutex_lock(&smmu->streams_mutex); in arm_smmu_insert_master()
3280 for (i = 0; i < fwspec->num_ids; i++) { in arm_smmu_insert_master()
3281 struct arm_smmu_stream *new_stream = &master->streams[i]; in arm_smmu_insert_master()
3282 u32 sid = fwspec->ids[i]; in arm_smmu_insert_master()
3284 new_stream->id = sid; in arm_smmu_insert_master()
3285 new_stream->master = master; in arm_smmu_insert_master()
3292 if (rb_find_add(&new_stream->node, &smmu->streams, in arm_smmu_insert_master()
3294 dev_warn(master->dev, "stream %u already in tree\n", in arm_smmu_insert_master()
3296 ret = -EINVAL; in arm_smmu_insert_master()
3302 for (i--; i >= 0; i--) in arm_smmu_insert_master()
3303 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_insert_master()
3304 kfree(master->streams); in arm_smmu_insert_master()
3306 mutex_unlock(&smmu->streams_mutex); in arm_smmu_insert_master()
3314 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_remove_master()
3315 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); in arm_smmu_remove_master()
3317 if (!smmu || !master->streams) in arm_smmu_remove_master()
3320 mutex_lock(&smmu->streams_mutex); in arm_smmu_remove_master()
3321 for (i = 0; i < fwspec->num_ids; i++) in arm_smmu_remove_master()
3322 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_remove_master()
3323 mutex_unlock(&smmu->streams_mutex); in arm_smmu_remove_master()
3325 kfree(master->streams); in arm_smmu_remove_master()
3336 return ERR_PTR(-EBUSY); in arm_smmu_probe_device()
3338 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); in arm_smmu_probe_device()
3340 return ERR_PTR(-ENODEV); in arm_smmu_probe_device()
3344 return ERR_PTR(-ENOMEM); in arm_smmu_probe_device()
3346 master->dev = dev; in arm_smmu_probe_device()
3347 master->smmu = smmu; in arm_smmu_probe_device()
3354 device_property_read_u32(dev, "pasid-num-bits", &master->ssid_bits); in arm_smmu_probe_device()
3355 master->ssid_bits = min(smmu->ssid_bits, master->ssid_bits); in arm_smmu_probe_device()
3359 * PCI Express Base 4.0r1.0 - 10.5.1.3 ATS Control Register in arm_smmu_probe_device()
3367 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) in arm_smmu_probe_device()
3368 master->ssid_bits = min_t(u8, master->ssid_bits, in arm_smmu_probe_device()
3371 if ((smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_probe_device()
3372 device_property_read_bool(dev, "dma-can-stall")) || in arm_smmu_probe_device()
3373 smmu->features & ARM_SMMU_FEAT_STALL_FORCE) in arm_smmu_probe_device()
3374 master->stall_enabled = true; in arm_smmu_probe_device()
3377 unsigned int stu = __ffs(smmu->pgsize_bitmap); in arm_smmu_probe_device()
3382 return &smmu->iommu; in arm_smmu_probe_device()
3394 iopf_queue_remove_device(master->smmu->evtq.iopf, dev); in arm_smmu_release_device()
3397 if (dev->iommu->require_direct) in arm_smmu_release_device()
3404 if (arm_smmu_cdtab_allocated(&master->cd_table)) in arm_smmu_release_device()
3415 struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; in arm_smmu_read_and_clear_dirty()
3417 return ops->read_and_clear_dirty(ops, iova, size, flags, dirty); in arm_smmu_read_and_clear_dirty()
3436 * aliases, since the necessary ID-to-device lookup becomes rather in arm_smmu_device_group()
3437 * impractical given a potential sparse 32-bit stream ID space. in arm_smmu_device_group()
3450 return iommu_fwspec_add_ids(dev, args->args, 1); in arm_smmu_of_xlate()
3464 list_add_tail(®ion->list, head); in arm_smmu_get_resv_regions()
3475 return -ENODEV; in arm_smmu_dev_enable_feature()
3480 return -EINVAL; in arm_smmu_dev_enable_feature()
3481 if (master->iopf_enabled) in arm_smmu_dev_enable_feature()
3482 return -EBUSY; in arm_smmu_dev_enable_feature()
3483 master->iopf_enabled = true; in arm_smmu_dev_enable_feature()
3487 return -EINVAL; in arm_smmu_dev_enable_feature()
3489 return -EBUSY; in arm_smmu_dev_enable_feature()
3492 return -EINVAL; in arm_smmu_dev_enable_feature()
3502 return -EINVAL; in arm_smmu_dev_disable_feature()
3506 if (!master->iopf_enabled) in arm_smmu_dev_disable_feature()
3507 return -EINVAL; in arm_smmu_dev_disable_feature()
3508 if (master->sva_enabled) in arm_smmu_dev_disable_feature()
3509 return -EBUSY; in arm_smmu_dev_disable_feature()
3510 master->iopf_enabled = false; in arm_smmu_dev_disable_feature()
3514 return -EINVAL; in arm_smmu_dev_disable_feature()
3517 return -EINVAL; in arm_smmu_dev_disable_feature()
3526 #define IS_HISI_PTT_DEVICE(pdev) ((pdev)->vendor == PCI_VENDOR_ID_HUAWEI && \
3527 (pdev)->device == 0xa12e)
3561 .pgsize_bitmap = -1UL, /* Restricted during device attach */
3590 qsz = ((1 << q->llq.max_n_shift) * dwords) << 3; in arm_smmu_init_one_queue()
3591 q->base = dmam_alloc_coherent(smmu->dev, qsz, &q->base_dma, in arm_smmu_init_one_queue()
3593 if (q->base || qsz < PAGE_SIZE) in arm_smmu_init_one_queue()
3596 q->llq.max_n_shift--; in arm_smmu_init_one_queue()
3599 if (!q->base) { in arm_smmu_init_one_queue()
3600 dev_err(smmu->dev, in arm_smmu_init_one_queue()
3603 return -ENOMEM; in arm_smmu_init_one_queue()
3606 if (!WARN_ON(q->base_dma & (qsz - 1))) { in arm_smmu_init_one_queue()
3607 dev_info(smmu->dev, "allocated %u entries for %s\n", in arm_smmu_init_one_queue()
3608 1 << q->llq.max_n_shift, name); in arm_smmu_init_one_queue()
3611 q->prod_reg = page + prod_off; in arm_smmu_init_one_queue()
3612 q->cons_reg = page + cons_off; in arm_smmu_init_one_queue()
3613 q->ent_dwords = dwords; in arm_smmu_init_one_queue()
3615 q->q_base = Q_BASE_RWA; in arm_smmu_init_one_queue()
3616 q->q_base |= q->base_dma & Q_BASE_ADDR_MASK; in arm_smmu_init_one_queue()
3617 q->q_base |= FIELD_PREP(Q_BASE_LOG2SIZE, q->llq.max_n_shift); in arm_smmu_init_one_queue()
3619 q->llq.prod = q->llq.cons = 0; in arm_smmu_init_one_queue()
3626 unsigned int nents = 1 << cmdq->q.llq.max_n_shift; in arm_smmu_cmdq_init()
3628 atomic_set(&cmdq->owner_prod, 0); in arm_smmu_cmdq_init()
3629 atomic_set(&cmdq->lock, 0); in arm_smmu_cmdq_init()
3631 cmdq->valid_map = (atomic_long_t *)devm_bitmap_zalloc(smmu->dev, nents, in arm_smmu_cmdq_init()
3633 if (!cmdq->valid_map) in arm_smmu_cmdq_init()
3634 return -ENOMEM; in arm_smmu_cmdq_init()
3644 ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, smmu->base, in arm_smmu_init_queues()
3650 ret = arm_smmu_cmdq_init(smmu, &smmu->cmdq); in arm_smmu_init_queues()
3655 ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1, in arm_smmu_init_queues()
3661 if ((smmu->features & ARM_SMMU_FEAT_SVA) && in arm_smmu_init_queues()
3662 (smmu->features & ARM_SMMU_FEAT_STALLS)) { in arm_smmu_init_queues()
3663 smmu->evtq.iopf = iopf_queue_alloc(dev_name(smmu->dev)); in arm_smmu_init_queues()
3664 if (!smmu->evtq.iopf) in arm_smmu_init_queues()
3665 return -ENOMEM; in arm_smmu_init_queues()
3669 if (!(smmu->features & ARM_SMMU_FEAT_PRI)) in arm_smmu_init_queues()
3672 return arm_smmu_init_one_queue(smmu, &smmu->priq.q, smmu->page1, in arm_smmu_init_queues()
3680 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_2lvl()
3682 arm_smmu_strtab_l1_idx((1ULL << smmu->sid_bits) - 1); in arm_smmu_init_strtab_2lvl()
3685 cfg->l2.num_l1_ents = min(last_sid_idx + 1, STRTAB_MAX_L1_ENTRIES); in arm_smmu_init_strtab_2lvl()
3686 if (cfg->l2.num_l1_ents <= last_sid_idx) in arm_smmu_init_strtab_2lvl()
3687 dev_warn(smmu->dev, in arm_smmu_init_strtab_2lvl()
3688 "2-level strtab only covers %u/%u bits of SID\n", in arm_smmu_init_strtab_2lvl()
3689 ilog2(cfg->l2.num_l1_ents * STRTAB_NUM_L2_STES), in arm_smmu_init_strtab_2lvl()
3690 smmu->sid_bits); in arm_smmu_init_strtab_2lvl()
3692 l1size = cfg->l2.num_l1_ents * sizeof(struct arm_smmu_strtab_l1); in arm_smmu_init_strtab_2lvl()
3693 cfg->l2.l1tab = dmam_alloc_coherent(smmu->dev, l1size, &cfg->l2.l1_dma, in arm_smmu_init_strtab_2lvl()
3695 if (!cfg->l2.l1tab) { in arm_smmu_init_strtab_2lvl()
3696 dev_err(smmu->dev, in arm_smmu_init_strtab_2lvl()
3699 return -ENOMEM; in arm_smmu_init_strtab_2lvl()
3702 cfg->l2.l2ptrs = devm_kcalloc(smmu->dev, cfg->l2.num_l1_ents, in arm_smmu_init_strtab_2lvl()
3703 sizeof(*cfg->l2.l2ptrs), GFP_KERNEL); in arm_smmu_init_strtab_2lvl()
3704 if (!cfg->l2.l2ptrs) in arm_smmu_init_strtab_2lvl()
3705 return -ENOMEM; in arm_smmu_init_strtab_2lvl()
3713 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_linear()
3715 size = (1 << smmu->sid_bits) * sizeof(struct arm_smmu_ste); in arm_smmu_init_strtab_linear()
3716 cfg->linear.table = dmam_alloc_coherent(smmu->dev, size, in arm_smmu_init_strtab_linear()
3717 &cfg->linear.ste_dma, in arm_smmu_init_strtab_linear()
3719 if (!cfg->linear.table) { in arm_smmu_init_strtab_linear()
3720 dev_err(smmu->dev, in arm_smmu_init_strtab_linear()
3723 return -ENOMEM; in arm_smmu_init_strtab_linear()
3725 cfg->linear.num_ents = 1 << smmu->sid_bits; in arm_smmu_init_strtab_linear()
3727 arm_smmu_init_initial_stes(cfg->linear.table, cfg->linear.num_ents); in arm_smmu_init_strtab_linear()
3735 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_init_strtab()
3742 ida_init(&smmu->vmid_map); in arm_smmu_init_strtab()
3751 mutex_init(&smmu->streams_mutex); in arm_smmu_init_structures()
3752 smmu->streams = RB_ROOT; in arm_smmu_init_structures()
3762 if (smmu->impl_ops && smmu->impl_ops->init_structures) in arm_smmu_init_structures()
3763 return smmu->impl_ops->init_structures(smmu); in arm_smmu_init_structures()
3773 writel_relaxed(val, smmu->base + reg_off); in arm_smmu_write_reg_sync()
3774 return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val, in arm_smmu_write_reg_sync()
3782 u32 reg, __iomem *gbpa = smmu->base + ARM_SMMU_GBPA; in arm_smmu_update_gbpa()
3796 dev_err(smmu->dev, "GBPA not responding to update\n"); in arm_smmu_update_gbpa()
3812 phys_addr_t *cfg = arm_smmu_msi_cfg[desc->msi_index]; in arm_smmu_write_msi_msg()
3814 doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo; in arm_smmu_write_msi_msg()
3817 writeq_relaxed(doorbell, smmu->base + cfg[0]); in arm_smmu_write_msi_msg()
3818 writel_relaxed(msg->data, smmu->base + cfg[1]); in arm_smmu_write_msi_msg()
3819 writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]); in arm_smmu_write_msi_msg()
3825 struct device *dev = smmu->dev; in arm_smmu_setup_msis()
3828 writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); in arm_smmu_setup_msis()
3829 writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); in arm_smmu_setup_msis()
3831 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_msis()
3832 writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0); in arm_smmu_setup_msis()
3834 nvec--; in arm_smmu_setup_msis()
3836 if (!(smmu->features & ARM_SMMU_FEAT_MSI)) in arm_smmu_setup_msis()
3839 if (!dev->msi.domain) { in arm_smmu_setup_msis()
3840 dev_info(smmu->dev, "msi_domain absent - falling back to wired irqs\n"); in arm_smmu_setup_msis()
3847 dev_warn(dev, "failed to allocate MSIs - falling back to wired irqs\n"); in arm_smmu_setup_msis()
3851 smmu->evtq.q.irq = msi_get_virq(dev, EVTQ_MSI_INDEX); in arm_smmu_setup_msis()
3852 smmu->gerr_irq = msi_get_virq(dev, GERROR_MSI_INDEX); in arm_smmu_setup_msis()
3853 smmu->priq.q.irq = msi_get_virq(dev, PRIQ_MSI_INDEX); in arm_smmu_setup_msis()
3866 irq = smmu->evtq.q.irq; in arm_smmu_setup_unique_irqs()
3868 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3871 "arm-smmu-v3-evtq", smmu); in arm_smmu_setup_unique_irqs()
3873 dev_warn(smmu->dev, "failed to enable evtq irq\n"); in arm_smmu_setup_unique_irqs()
3875 dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3878 irq = smmu->gerr_irq; in arm_smmu_setup_unique_irqs()
3880 ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler, in arm_smmu_setup_unique_irqs()
3881 0, "arm-smmu-v3-gerror", smmu); in arm_smmu_setup_unique_irqs()
3883 dev_warn(smmu->dev, "failed to enable gerror irq\n"); in arm_smmu_setup_unique_irqs()
3885 dev_warn(smmu->dev, "no gerr irq - errors will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3888 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_setup_unique_irqs()
3889 irq = smmu->priq.q.irq; in arm_smmu_setup_unique_irqs()
3891 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3894 "arm-smmu-v3-priq", in arm_smmu_setup_unique_irqs()
3897 dev_warn(smmu->dev, in arm_smmu_setup_unique_irqs()
3900 dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); in arm_smmu_setup_unique_irqs()
3914 dev_err(smmu->dev, "failed to disable irqs\n"); in arm_smmu_setup_irqs()
3918 irq = smmu->combined_irq; in arm_smmu_setup_irqs()
3924 ret = devm_request_threaded_irq(smmu->dev, irq, in arm_smmu_setup_irqs()
3928 "arm-smmu-v3-combined-irq", smmu); in arm_smmu_setup_irqs()
3930 dev_warn(smmu->dev, "failed to enable combined irq\n"); in arm_smmu_setup_irqs()
3934 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_irqs()
3941 dev_warn(smmu->dev, "failed to enable irqs\n"); in arm_smmu_setup_irqs()
3952 dev_err(smmu->dev, "failed to clear cr0\n"); in arm_smmu_device_disable()
3959 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_write_strtab()
3963 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { in arm_smmu_write_strtab()
3967 ilog2(cfg->l2.num_l1_ents) + STRTAB_SPLIT) | in arm_smmu_write_strtab()
3969 dma = cfg->l2.l1_dma; in arm_smmu_write_strtab()
3973 FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits); in arm_smmu_write_strtab()
3974 dma = cfg->linear.ste_dma; in arm_smmu_write_strtab()
3977 smmu->base + ARM_SMMU_STRTAB_BASE); in arm_smmu_write_strtab()
3978 writel_relaxed(reg, smmu->base + ARM_SMMU_STRTAB_BASE_CFG); in arm_smmu_write_strtab()
3988 reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); in arm_smmu_device_reset()
3990 dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); in arm_smmu_device_reset()
4005 writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); in arm_smmu_device_reset()
4010 if (smmu->features & ARM_SMMU_FEAT_E2H) in arm_smmu_device_reset()
4013 writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); in arm_smmu_device_reset()
4019 writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); in arm_smmu_device_reset()
4020 writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); in arm_smmu_device_reset()
4021 writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); in arm_smmu_device_reset()
4027 dev_err(smmu->dev, "failed to enable command queue\n"); in arm_smmu_device_reset()
4036 if (smmu->features & ARM_SMMU_FEAT_HYP) { in arm_smmu_device_reset()
4045 writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); in arm_smmu_device_reset()
4046 writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); in arm_smmu_device_reset()
4047 writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); in arm_smmu_device_reset()
4053 dev_err(smmu->dev, "failed to enable event queue\n"); in arm_smmu_device_reset()
4058 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_device_reset()
4059 writeq_relaxed(smmu->priq.q.q_base, in arm_smmu_device_reset()
4060 smmu->base + ARM_SMMU_PRIQ_BASE); in arm_smmu_device_reset()
4061 writel_relaxed(smmu->priq.q.llq.prod, in arm_smmu_device_reset()
4062 smmu->page1 + ARM_SMMU_PRIQ_PROD); in arm_smmu_device_reset()
4063 writel_relaxed(smmu->priq.q.llq.cons, in arm_smmu_device_reset()
4064 smmu->page1 + ARM_SMMU_PRIQ_CONS); in arm_smmu_device_reset()
4070 dev_err(smmu->dev, "failed to enable PRI queue\n"); in arm_smmu_device_reset()
4075 if (smmu->features & ARM_SMMU_FEAT_ATS) { in arm_smmu_device_reset()
4080 dev_err(smmu->dev, "failed to enable ATS check\n"); in arm_smmu_device_reset()
4087 dev_err(smmu->dev, "failed to setup irqs\n"); in arm_smmu_device_reset()
4099 dev_err(smmu->dev, "failed to enable SMMU interface\n"); in arm_smmu_device_reset()
4103 if (smmu->impl_ops && smmu->impl_ops->device_reset) { in arm_smmu_device_reset()
4104 ret = smmu->impl_ops->device_reset(smmu); in arm_smmu_device_reset()
4106 dev_err(smmu->dev, "failed to reset impl\n"); in arm_smmu_device_reset()
4123 reg = readl_relaxed(smmu->base + ARM_SMMU_IIDR); in arm_smmu_device_iidr_probe()
4135 smmu->features &= ~ARM_SMMU_FEAT_SEV; in arm_smmu_device_iidr_probe()
4138 smmu->features &= ~ARM_SMMU_FEAT_NESTING; in arm_smmu_device_iidr_probe()
4142 smmu->features &= ~ARM_SMMU_FEAT_BTM; in arm_smmu_device_iidr_probe()
4143 smmu->options |= ARM_SMMU_OPT_CMDQ_FORCE_SYNC; in arm_smmu_device_iidr_probe()
4145 smmu->features &= ~ARM_SMMU_FEAT_NESTING; in arm_smmu_device_iidr_probe()
4154 u32 fw_features = smmu->features & (ARM_SMMU_FEAT_HA | ARM_SMMU_FEAT_HD); in arm_smmu_get_httu()
4165 if (smmu->dev->of_node) in arm_smmu_get_httu()
4166 smmu->features |= hw_features; in arm_smmu_get_httu()
4169 dev_warn(smmu->dev, in arm_smmu_get_httu()
4177 bool coherent = smmu->features & ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_hw_probe()
4180 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); in arm_smmu_device_hw_probe()
4182 /* 2-level structures */ in arm_smmu_device_hw_probe()
4184 smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
4187 smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB; in arm_smmu_device_hw_probe()
4196 smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
4200 smmu->features |= ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
4204 smmu->features |= ARM_SMMU_FEAT_TT_LE; in arm_smmu_device_hw_probe()
4208 dev_err(smmu->dev, "unknown/unsupported TT endianness!\n"); in arm_smmu_device_hw_probe()
4209 return -ENXIO; in arm_smmu_device_hw_probe()
4214 smmu->features |= ARM_SMMU_FEAT_PRI; in arm_smmu_device_hw_probe()
4217 smmu->features |= ARM_SMMU_FEAT_ATS; in arm_smmu_device_hw_probe()
4220 smmu->features |= ARM_SMMU_FEAT_SEV; in arm_smmu_device_hw_probe()
4223 smmu->features |= ARM_SMMU_FEAT_MSI; in arm_smmu_device_hw_probe()
4225 smmu->options |= ARM_SMMU_OPT_MSIPOLL; in arm_smmu_device_hw_probe()
4229 smmu->features |= ARM_SMMU_FEAT_HYP; in arm_smmu_device_hw_probe()
4231 smmu->features |= ARM_SMMU_FEAT_E2H; in arm_smmu_device_hw_probe()
4241 dev_warn(smmu->dev, "IDR0.COHACC overridden by FW configuration (%s)\n", in arm_smmu_device_hw_probe()
4246 smmu->features |= ARM_SMMU_FEAT_STALL_FORCE; in arm_smmu_device_hw_probe()
4249 smmu->features |= ARM_SMMU_FEAT_STALLS; in arm_smmu_device_hw_probe()
4253 smmu->features |= ARM_SMMU_FEAT_TRANS_S1; in arm_smmu_device_hw_probe()
4256 smmu->features |= ARM_SMMU_FEAT_TRANS_S2; in arm_smmu_device_hw_probe()
4259 dev_err(smmu->dev, "no translation support!\n"); in arm_smmu_device_hw_probe()
4260 return -ENXIO; in arm_smmu_device_hw_probe()
4266 smmu->ias = 40; in arm_smmu_device_hw_probe()
4271 dev_err(smmu->dev, "AArch64 table format not supported!\n"); in arm_smmu_device_hw_probe()
4272 return -ENXIO; in arm_smmu_device_hw_probe()
4276 smmu->asid_bits = reg & IDR0_ASID16 ? 16 : 8; in arm_smmu_device_hw_probe()
4277 smmu->vmid_bits = reg & IDR0_VMID16 ? 16 : 8; in arm_smmu_device_hw_probe()
4280 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1); in arm_smmu_device_hw_probe()
4282 dev_err(smmu->dev, "embedded implementation not supported\n"); in arm_smmu_device_hw_probe()
4283 return -ENXIO; in arm_smmu_device_hw_probe()
4287 smmu->features |= ARM_SMMU_FEAT_ATTR_TYPES_OVR; in arm_smmu_device_hw_probe()
4290 smmu->cmdq.q.llq.max_n_shift = min_t(u32, CMDQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
4292 if (smmu->cmdq.q.llq.max_n_shift <= ilog2(CMDQ_BATCH_ENTRIES)) { in arm_smmu_device_hw_probe()
4297 * restrictions on the base pointer for a unit-length queue. in arm_smmu_device_hw_probe()
4299 dev_err(smmu->dev, "command queue size <= %d entries not supported\n", in arm_smmu_device_hw_probe()
4301 return -ENXIO; in arm_smmu_device_hw_probe()
4304 smmu->evtq.q.llq.max_n_shift = min_t(u32, EVTQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
4306 smmu->priq.q.llq.max_n_shift = min_t(u32, PRIQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
4310 smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg); in arm_smmu_device_hw_probe()
4311 smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg); in arm_smmu_device_hw_probe()
4312 smmu->iommu.max_pasids = 1UL << smmu->ssid_bits; in arm_smmu_device_hw_probe()
4318 if (smmu->sid_bits <= STRTAB_SPLIT) in arm_smmu_device_hw_probe()
4319 smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
4322 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3); in arm_smmu_device_hw_probe()
4324 smmu->features |= ARM_SMMU_FEAT_RANGE_INV; in arm_smmu_device_hw_probe()
4327 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); in arm_smmu_device_hw_probe()
4330 smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg); in arm_smmu_device_hw_probe()
4334 smmu->pgsize_bitmap |= SZ_64K | SZ_512M; in arm_smmu_device_hw_probe()
4336 smmu->pgsize_bitmap |= SZ_16K | SZ_32M; in arm_smmu_device_hw_probe()
4338 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; in arm_smmu_device_hw_probe()
4342 smmu->features |= ARM_SMMU_FEAT_VAX; in arm_smmu_device_hw_probe()
4347 smmu->oas = 32; in arm_smmu_device_hw_probe()
4350 smmu->oas = 36; in arm_smmu_device_hw_probe()
4353 smmu->oas = 40; in arm_smmu_device_hw_probe()
4356 smmu->oas = 42; in arm_smmu_device_hw_probe()
4359 smmu->oas = 44; in arm_smmu_device_hw_probe()
4362 smmu->oas = 52; in arm_smmu_device_hw_probe()
4363 smmu->pgsize_bitmap |= 1ULL << 42; /* 4TB */ in arm_smmu_device_hw_probe()
4366 dev_info(smmu->dev, in arm_smmu_device_hw_probe()
4367 "unknown output address size. Truncating to 48-bit\n"); in arm_smmu_device_hw_probe()
4370 smmu->oas = 48; in arm_smmu_device_hw_probe()
4373 if (arm_smmu_ops.pgsize_bitmap == -1UL) in arm_smmu_device_hw_probe()
4374 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
4376 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
4379 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas))) in arm_smmu_device_hw_probe()
4380 dev_warn(smmu->dev, in arm_smmu_device_hw_probe()
4383 smmu->ias = max(smmu->ias, smmu->oas); in arm_smmu_device_hw_probe()
4385 if ((smmu->features & ARM_SMMU_FEAT_TRANS_S1) && in arm_smmu_device_hw_probe()
4386 (smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_device_hw_probe()
4387 smmu->features |= ARM_SMMU_FEAT_NESTING; in arm_smmu_device_hw_probe()
4392 smmu->features |= ARM_SMMU_FEAT_SVA; in arm_smmu_device_hw_probe()
4394 dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n", in arm_smmu_device_hw_probe()
4395 smmu->ias, smmu->oas, smmu->features); in arm_smmu_device_hw_probe()
4404 const char *uid = kasprintf(GFP_KERNEL, "%u", node->identifier); in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4408 adev = acpi_dev_get_first_match_dev("NVDA200C", uid, -1); in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4411 smmu->impl_dev = &adev->dev; in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4412 smmu->options |= ARM_SMMU_OPT_TEGRA241_CMDQV; in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4413 dev_info(smmu->dev, "found companion CMDQV device: %s\n", in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4414 dev_name(smmu->impl_dev)); in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4429 (struct acpi_iort_smmu_v3 *)node->node_data; in acpi_smmu_iort_probe_model()
4431 switch (iort_smmu->model) { in acpi_smmu_iort_probe_model()
4433 smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY; in acpi_smmu_iort_probe_model()
4436 smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; in acpi_smmu_iort_probe_model()
4447 dev_notice(smmu->dev, "option mask 0x%x\n", smmu->options); in acpi_smmu_iort_probe_model()
4455 struct device *dev = smmu->dev; in arm_smmu_device_acpi_probe()
4461 iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data; in arm_smmu_device_acpi_probe()
4463 if (iort_smmu->flags & ACPI_IORT_SMMU_V3_COHACC_OVERRIDE) in arm_smmu_device_acpi_probe()
4464 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_acpi_probe()
4466 switch (FIELD_GET(ACPI_IORT_SMMU_V3_HTTU_OVERRIDE, iort_smmu->flags)) { in arm_smmu_device_acpi_probe()
4468 smmu->features |= ARM_SMMU_FEAT_HD; in arm_smmu_device_acpi_probe()
4471 smmu->features |= ARM_SMMU_FEAT_HA; in arm_smmu_device_acpi_probe()
4480 return -ENODEV; in arm_smmu_device_acpi_probe()
4487 struct device *dev = &pdev->dev; in arm_smmu_device_dt_probe()
4489 int ret = -EINVAL; in arm_smmu_device_dt_probe()
4491 if (of_property_read_u32(dev->of_node, "#iommu-cells", &cells)) in arm_smmu_device_dt_probe()
4492 dev_err(dev, "missing #iommu-cells property\n"); in arm_smmu_device_dt_probe()
4494 dev_err(dev, "invalid #iommu-cells value (%d)\n", cells); in arm_smmu_device_dt_probe()
4500 if (of_dma_is_coherent(dev->of_node)) in arm_smmu_device_dt_probe()
4501 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_dt_probe()
4508 if (smmu->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY) in arm_smmu_resource_size()
4528 iort_get_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_ste()
4535 for (i = 0; i < rmr->num_sids; i++) { in arm_smmu_rmr_install_bypass_ste()
4536 ret = arm_smmu_init_sid_strtab(smmu, rmr->sids[i]); in arm_smmu_rmr_install_bypass_ste()
4538 dev_err(smmu->dev, "RMR SID(0x%x) bypass failed\n", in arm_smmu_rmr_install_bypass_ste()
4539 rmr->sids[i]); in arm_smmu_rmr_install_bypass_ste()
4548 arm_smmu_get_step_for_sid(smmu, rmr->sids[i])); in arm_smmu_rmr_install_bypass_ste()
4552 iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_ste()
4559 if (smmu->impl_ops && smmu->impl_ops->device_remove) in arm_smmu_impl_remove()
4560 smmu->impl_ops->device_remove(smmu); in arm_smmu_impl_remove()
4570 struct arm_smmu_device *new_smmu = ERR_PTR(-ENODEV); in arm_smmu_impl_probe()
4573 if (smmu->impl_dev && (smmu->options & ARM_SMMU_OPT_TEGRA241_CMDQV)) in arm_smmu_impl_probe()
4576 if (new_smmu == ERR_PTR(-ENODEV)) in arm_smmu_impl_probe()
4581 ret = devm_add_action_or_reset(new_smmu->dev, arm_smmu_impl_remove, in arm_smmu_impl_probe()
4594 struct device *dev = &pdev->dev; in arm_smmu_device_probe()
4598 return -ENOMEM; in arm_smmu_device_probe()
4599 smmu->dev = dev; in arm_smmu_device_probe()
4601 if (dev->of_node) { in arm_smmu_device_probe()
4616 return -EINVAL; in arm_smmu_device_probe()
4619 return -EINVAL; in arm_smmu_device_probe()
4621 ioaddr = res->start; in arm_smmu_device_probe()
4627 smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ); in arm_smmu_device_probe()
4628 if (IS_ERR(smmu->base)) in arm_smmu_device_probe()
4629 return PTR_ERR(smmu->base); in arm_smmu_device_probe()
4632 smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K, in arm_smmu_device_probe()
4634 if (IS_ERR(smmu->page1)) in arm_smmu_device_probe()
4635 return PTR_ERR(smmu->page1); in arm_smmu_device_probe()
4637 smmu->page1 = smmu->base; in arm_smmu_device_probe()
4644 smmu->combined_irq = irq; in arm_smmu_device_probe()
4648 smmu->evtq.q.irq = irq; in arm_smmu_device_probe()
4652 smmu->priq.q.irq = irq; in arm_smmu_device_probe()
4656 smmu->gerr_irq = irq; in arm_smmu_device_probe()
4663 /* Initialise in-memory data structures */ in arm_smmu_device_probe()
4680 ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, in arm_smmu_device_probe()
4685 ret = iommu_device_register(&smmu->iommu, &arm_smmu_ops, dev); in arm_smmu_device_probe()
4688 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_probe()
4699 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_remove()
4700 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_remove()
4702 iopf_queue_free(smmu->evtq.iopf); in arm_smmu_device_remove()
4703 ida_destroy(&smmu->vmid_map); in arm_smmu_device_remove()
4714 { .compatible = "arm,smmu-v3", },
4727 .name = "arm-smmu-v3",
4740 MODULE_ALIAS("platform:arm-smmu-v3");