Lines Matching defs:smmu
33 #include "arm-smmu-v3.h"
111 static void parse_driver_options(struct arm_smmu_device *smmu)
116 if (of_property_read_bool(smmu->dev->of_node,
118 smmu->options |= arm_smmu_options[i].opt;
119 dev_notice(smmu->dev, "option %s\n",
214 static void queue_poll_init(struct arm_smmu_device *smmu,
219 qp->wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV);
371 static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu,
376 if (smmu->impl_ops && smmu->impl_ops->get_secondary_cmdq)
377 cmdq = smmu->impl_ops->get_secondary_cmdq(smmu, ent);
379 return cmdq ?: &smmu->cmdq;
382 static bool arm_smmu_cmdq_needs_busy_polling(struct arm_smmu_device *smmu,
385 if (cmdq == &smmu->cmdq)
388 return smmu->options & ARM_SMMU_OPT_TEGRA241_CMDQV;
391 static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu,
403 if (smmu->options & ARM_SMMU_OPT_MSIPOLL) {
409 if (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq))
413 void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu,
432 dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons,
437 dev_err(smmu->dev, "retrying command fetch\n");
459 dev_err(smmu->dev, "skipping command in error state:\n");
461 dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]);
465 if (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq))
471 static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)
473 __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq);
637 static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu,
656 queue_poll_init(smmu, &qp);
672 static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu,
680 queue_poll_init(smmu, &qp);
696 static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu,
704 queue_poll_init(smmu, &qp);
746 static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu,
750 if (smmu->options & ARM_SMMU_OPT_MSIPOLL &&
751 !arm_smmu_cmdq_needs_busy_polling(smmu, cmdq))
752 return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq);
754 return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq);
790 int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,
811 if (arm_smmu_cmdq_poll_until_not_full(smmu, cmdq, &llq))
812 dev_err_ratelimited(smmu->dev, "CMDQ timeout\n");
837 arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, cmdq, prod);
887 ret = arm_smmu_cmdq_poll_until_sync(smmu, cmdq, &llq);
889 dev_err_ratelimited(smmu->dev,
910 static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
917 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n",
923 smmu, arm_smmu_get_cmdq(smmu, ent), cmd, 1, sync);
926 static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
929 return __arm_smmu_cmdq_issue_cmd(smmu, ent, false);
932 static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu,
935 return __arm_smmu_cmdq_issue_cmd(smmu, ent, true);
938 static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu,
943 cmds->cmdq = arm_smmu_get_cmdq(smmu, ent);
946 static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu,
952 (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC);
956 arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds,
958 arm_smmu_cmdq_batch_init(smmu, cmds, cmd);
962 arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds,
964 arm_smmu_cmdq_batch_init(smmu, cmds, cmd);
969 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n",
977 static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu,
980 return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds,
1009 arm_smmu_cmdq_issue_cmd(master->smmu, &cmd);
1019 void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid)
1022 .opcode = smmu->features & ARM_SMMU_FEAT_E2H ?
1027 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);
1225 struct arm_smmu_device *smmu = master->smmu;
1234 arm_smmu_cmdq_batch_init(smmu, &cmds, &cmd);
1237 arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);
1240 arm_smmu_cmdq_batch_submit(smmu, &cmds);
1279 struct arm_smmu_device *smmu = master->smmu;
1296 *l2ptr = dma_alloc_coherent(smmu->dev, sizeof(**l2ptr),
1435 struct arm_smmu_device *smmu = master->smmu;
1441 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) ||
1447 cd_table->linear.table = dma_alloc_coherent(smmu->dev, l1size,
1464 cd_table->l2.l1tab = dma_alloc_coherent(smmu->dev, l1size,
1483 struct arm_smmu_device *smmu = master->smmu;
1491 dma_free_coherent(smmu->dev,
1498 dma_free_coherent(smmu->dev,
1503 dma_free_coherent(smmu->dev,
1540 arm_smmu_cmdq_issue_cmd_with_sync(writer->master->smmu, &cmd);
1552 struct arm_smmu_device *smmu = master->smmu;
1564 if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) {
1571 arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);
1585 void arm_smmu_make_bypass_ste(struct arm_smmu_device *smmu,
1593 if (smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR)
1605 struct arm_smmu_device *smmu = master->smmu;
1620 ((smmu->features & ARM_SMMU_FEAT_STALLS &&
1627 if ((smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR) &&
1632 if (smmu->features & ARM_SMMU_FEAT_E2H) {
1668 struct arm_smmu_device *smmu = master->smmu;
1681 if (smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR)
1723 static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid)
1726 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
1733 *l2table = dmam_alloc_coherent(smmu->dev, sizeof(**l2table),
1736 dev_err(smmu->dev,
1770 arm_smmu_find_master(struct arm_smmu_device *smmu, u32 sid)
1774 lockdep_assert_held(&smmu->streams_mutex);
1776 node = rb_find(&sid, &smmu->streams, arm_smmu_streams_cmp_key);
1783 static void arm_smmu_decode_event(struct arm_smmu_device *smmu, u64 *raw,
1809 mutex_lock(&smmu->streams_mutex);
1810 master = arm_smmu_find_master(smmu, event->sid);
1813 mutex_unlock(&smmu->streams_mutex);
1816 static int arm_smmu_handle_event(struct arm_smmu_device *smmu, u64 *evt,
1865 mutex_lock(&smmu->streams_mutex);
1866 master = arm_smmu_find_master(smmu, event->sid);
1879 mutex_unlock(&smmu->streams_mutex);
1883 static void arm_smmu_dump_raw_event(struct arm_smmu_device *smmu, u64 *raw,
1888 dev_err(smmu->dev, "event 0x%02x received:\n", event->id);
1891 dev_err(smmu->dev, "\t0x%016llx\n", raw[i]);
1898 static void arm_smmu_dump_event(struct arm_smmu_device *smmu, u64 *raw,
1905 arm_smmu_dump_raw_event(smmu, raw, evt);
1912 dev_err(smmu->dev, "event: %s client: %s sid: %#x ssid: %#x iova: %#llx ipa: %#llx",
1916 dev_err(smmu->dev, "%s %s %s %s \"%s\"%s%s stag: %#x",
1929 dev_err(smmu->dev, "event: %s client: %s sid: %#x ssid: %#x fetch_addr: %#llx",
1936 dev_err(smmu->dev, "event: %s client: %s sid: %#x ssid: %#x",
1946 struct arm_smmu_device *smmu = dev;
1947 struct arm_smmu_queue *q = &smmu->evtq.q;
1954 arm_smmu_decode_event(smmu, evt, &event);
1955 if (arm_smmu_handle_event(smmu, evt, &event))
1956 arm_smmu_dump_event(smmu, evt, &event, &rs);
1967 dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n");
1975 static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt)
1987 dev_info(smmu->dev, "unexpected PRI request received:\n");
1988 dev_info(smmu->dev,
2009 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
2015 struct arm_smmu_device *smmu = dev;
2016 struct arm_smmu_queue *q = &smmu->priq.q;
2022 arm_smmu_handle_ppr(smmu, evt);
2025 dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n");
2033 static int arm_smmu_device_disable(struct arm_smmu_device *smmu);
2038 struct arm_smmu_device *smmu = dev;
2040 gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR);
2041 gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN);
2047 dev_warn(smmu->dev,
2052 dev_err(smmu->dev, "device has entered Service Failure Mode!\n");
2053 arm_smmu_device_disable(smmu);
2057 dev_warn(smmu->dev, "GERROR MSI write aborted\n");
2060 dev_warn(smmu->dev, "PRIQ MSI write aborted\n");
2063 dev_warn(smmu->dev, "EVTQ MSI write aborted\n");
2066 dev_warn(smmu->dev, "CMDQ MSI write aborted\n");
2069 dev_err(smmu->dev, "PRIQ write aborted -- events may have been lost\n");
2072 dev_err(smmu->dev, "EVTQ write aborted -- events may have been lost\n");
2075 arm_smmu_cmdq_skip_err(smmu);
2077 writel(gerror, smmu->base + ARM_SMMU_GERRORN);
2083 struct arm_smmu_device *smmu = dev;
2086 if (smmu->features & ARM_SMMU_FEAT_PRI)
2174 arm_smmu_cmdq_batch_init(master->smmu, &cmds, &cmd);
2177 arm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd);
2180 return arm_smmu_cmdq_batch_submit(master->smmu, &cmds);
2194 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS))
2214 arm_smmu_cmdq_batch_init(smmu_domain->smmu, &cmds, &cmd);
2237 arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd);
2242 return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds);
2249 struct arm_smmu_device *smmu = smmu_domain->smmu;
2260 arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid);
2264 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);
2274 struct arm_smmu_device *smmu = smmu_domain->smmu;
2282 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) {
2305 arm_smmu_cmdq_batch_init(smmu, &cmds, cmd);
2308 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) {
2334 arm_smmu_cmdq_batch_add(smmu, &cmds, cmd);
2337 arm_smmu_cmdq_batch_submit(smmu, &cmds);
2351 cmd.opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ?
2366 arm_smmu_cmdq_issue_cmd_with_sync(smmu_domain->smmu, &cmd);
2381 .opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ?
2414 static bool arm_smmu_dbm_capable(struct arm_smmu_device *smmu)
2418 return (smmu->features & features) == features;
2429 return master->smmu->features & ARM_SMMU_FEAT_COHERENCY;
2436 return arm_smmu_dbm_capable(master->smmu);
2479 struct arm_smmu_device *smmu = smmu_domain->smmu;
2492 ida_free(&smmu->vmid_map, cfg->vmid);
2498 static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu,
2508 XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL);
2514 static int arm_smmu_domain_finalise_s2(struct arm_smmu_device *smmu,
2521 vmid = ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1,
2531 struct arm_smmu_device *smmu, u32 flags)
2537 int (*finalise_stage_fn)(struct arm_smmu_device *smmu,
2542 .pgsize_bitmap = smmu->pgsize_bitmap,
2543 .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENCY,
2545 .iommu_dev = smmu->dev,
2550 unsigned long ias = (smmu->features &
2554 pgtbl_cfg.oas = smmu->ias;
2564 pgtbl_cfg.ias = smmu->ias;
2565 pgtbl_cfg.oas = smmu->oas;
2568 if ((smmu->features & ARM_SMMU_FEAT_S2FWB) &&
2586 ret = finalise_stage_fn(smmu, smmu_domain);
2593 smmu_domain->smmu = smmu;
2598 arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid)
2600 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
2602 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
2616 struct arm_smmu_device *smmu = master->smmu;
2628 arm_smmu_get_step_for_sid(smmu, sid);
2644 struct arm_smmu_device *smmu = master->smmu;
2647 if (!(smmu->features & ARM_SMMU_FEAT_ATS))
2660 struct arm_smmu_device *smmu = master->smmu;
2663 stu = __ffs(smmu->pgsize_bitmap);
2701 master->smmu->ssid_bits);
2940 struct arm_smmu_device *smmu;
2953 smmu = master->smmu;
2955 if (smmu_domain->smmu != smmu)
3010 struct arm_smmu_device *smmu = master->smmu;
3013 if (smmu_domain->smmu != smmu)
3068 if (smmu_domain->smmu != master->smmu)
3187 arm_smmu_make_bypass_ste(master->smmu, &ste);
3229 struct arm_smmu_device *smmu = master->smmu;
3248 if (smmu->features & ARM_SMMU_FEAT_TRANS_S1)
3254 if (!(smmu->features & ARM_SMMU_FEAT_NESTING)) {
3264 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) {
3277 ret = arm_smmu_domain_finalise(smmu_domain, smmu, flags);
3316 if (smmu_domain->smmu)
3355 static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)
3357 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB)
3358 return arm_smmu_strtab_l1_idx(sid) < smmu->strtab_cfg.l2.num_l1_ents;
3359 return sid < smmu->strtab_cfg.linear.num_ents;
3362 static int arm_smmu_init_sid_strtab(struct arm_smmu_device *smmu, u32 sid)
3365 if (!arm_smmu_sid_in_range(smmu, sid))
3369 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB)
3370 return arm_smmu_init_l2_strtab(smmu, sid);
3375 static int arm_smmu_insert_master(struct arm_smmu_device *smmu,
3388 mutex_lock(&smmu->streams_mutex);
3396 ret = arm_smmu_init_sid_strtab(smmu, sid);
3401 if (rb_find_add(&new_stream->node, &smmu->streams,
3412 rb_erase(&master->streams[i].node, &smmu->streams);
3415 mutex_unlock(&smmu->streams_mutex);
3423 struct arm_smmu_device *smmu = master->smmu;
3426 if (!smmu || !master->streams)
3429 mutex_lock(&smmu->streams_mutex);
3431 rb_erase(&master->streams[i].node, &smmu->streams);
3432 mutex_unlock(&smmu->streams_mutex);
3440 struct arm_smmu_device *smmu;
3447 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode);
3448 if (!smmu)
3456 master->smmu = smmu;
3459 ret = arm_smmu_insert_master(smmu, master);
3464 master->ssid_bits = min(smmu->ssid_bits, master->ssid_bits);
3476 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB))
3480 if ((smmu->features & ARM_SMMU_FEAT_STALLS &&
3482 smmu->features & ARM_SMMU_FEAT_STALL_FORCE)
3486 unsigned int stu = __ffs(smmu->pgsize_bitmap);
3491 return &smmu->iommu;
3503 iopf_queue_remove_device(master->smmu->evtq.iopf, dev);
3689 int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
3698 q->base = dmam_alloc_coherent(smmu->dev, qsz, &q->base_dma,
3707 dev_err(smmu->dev,
3714 dev_info(smmu->dev, "allocated %u entries for %s\n",
3730 int arm_smmu_cmdq_init(struct arm_smmu_device *smmu,
3738 cmdq->valid_map = (atomic_long_t *)devm_bitmap_zalloc(smmu->dev, nents,
3746 static int arm_smmu_init_queues(struct arm_smmu_device *smmu)
3751 ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, smmu->base,
3757 ret = arm_smmu_cmdq_init(smmu, &smmu->cmdq);
3762 ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1,
3768 if ((smmu->features & ARM_SMMU_FEAT_SVA) &&
3769 (smmu->features & ARM_SMMU_FEAT_STALLS)) {
3770 smmu->evtq.iopf = iopf_queue_alloc(dev_name(smmu->dev));
3771 if (!smmu->evtq.iopf)
3776 if (!(smmu->features & ARM_SMMU_FEAT_PRI))
3779 return arm_smmu_init_one_queue(smmu, &smmu->priq.q, smmu->page1,
3784 static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu)
3787 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
3789 arm_smmu_strtab_l1_idx((1ULL << smmu->sid_bits) - 1);
3794 dev_warn(smmu->dev,
3797 smmu->sid_bits);
3800 cfg->l2.l1tab = dmam_alloc_coherent(smmu->dev, l1size, &cfg->l2.l1_dma,
3803 dev_err(smmu->dev,
3809 cfg->l2.l2ptrs = devm_kcalloc(smmu->dev, cfg->l2.num_l1_ents,
3817 static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu)
3820 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
3822 size = (1 << smmu->sid_bits) * sizeof(struct arm_smmu_ste);
3823 cfg->linear.table = dmam_alloc_coherent(smmu->dev, size,
3827 dev_err(smmu->dev,
3832 cfg->linear.num_ents = 1 << smmu->sid_bits;
3838 static int arm_smmu_init_strtab(struct arm_smmu_device *smmu)
3842 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB)
3843 ret = arm_smmu_init_strtab_2lvl(smmu);
3845 ret = arm_smmu_init_strtab_linear(smmu);
3849 ida_init(&smmu->vmid_map);
3854 static int arm_smmu_init_structures(struct arm_smmu_device *smmu)
3858 mutex_init(&smmu->streams_mutex);
3859 smmu->streams = RB_ROOT;
3861 ret = arm_smmu_init_queues(smmu);
3865 ret = arm_smmu_init_strtab(smmu);
3869 if (smmu->impl_ops && smmu->impl_ops->init_structures)
3870 return smmu->impl_ops->init_structures(smmu);
3875 static int arm_smmu_write_reg_sync(struct arm_smmu_device *smmu, u32 val,
3880 writel_relaxed(val, smmu->base + reg_off);
3881 return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val,
3886 static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr)
3889 u32 reg, __iomem *gbpa = smmu->base + ARM_SMMU_GBPA;
3903 dev_err(smmu->dev, "GBPA not responding to update\n");
3918 struct arm_smmu_device *smmu = dev_get_drvdata(dev);
3924 writeq_relaxed(doorbell, smmu->base + cfg[0]);
3925 writel_relaxed(msg->data, smmu->base + cfg[1]);
3926 writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]);
3929 static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
3932 struct device *dev = smmu->dev;
3935 writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0);
3936 writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0);
3938 if (smmu->features & ARM_SMMU_FEAT_PRI)
3939 writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0);
3943 if (!(smmu->features & ARM_SMMU_FEAT_MSI))
3947 dev_info(smmu->dev, "msi_domain absent - falling back to wired irqs\n");
3958 smmu->evtq.q.irq = msi_get_virq(dev, EVTQ_MSI_INDEX);
3959 smmu->gerr_irq = msi_get_virq(dev, GERROR_MSI_INDEX);
3960 smmu->priq.q.irq = msi_get_virq(dev, PRIQ_MSI_INDEX);
3966 static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)
3970 arm_smmu_setup_msis(smmu);
3973 irq = smmu->evtq.q.irq;
3975 ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
3978 "arm-smmu-v3-evtq", smmu);
3980 dev_warn(smmu->dev, "failed to enable evtq irq\n");
3982 dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n");
3985 irq = smmu->gerr_irq;
3987 ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler,
3988 0, "arm-smmu-v3-gerror", smmu);
3990 dev_warn(smmu->dev, "failed to enable gerror irq\n");
3992 dev_warn(smmu->dev, "no gerr irq - errors will not be reported!\n");
3995 if (smmu->features & ARM_SMMU_FEAT_PRI) {
3996 irq = smmu->priq.q.irq;
3998 ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
4001 "arm-smmu-v3-priq",
4002 smmu);
4004 dev_warn(smmu->dev,
4007 dev_warn(smmu->dev, "no priq irq - PRI will be broken\n");
4012 static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
4018 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL,
4021 dev_err(smmu->dev, "failed to disable irqs\n");
4025 irq = smmu->combined_irq;
4031 ret = devm_request_threaded_irq(smmu->dev, irq,
4035 "arm-smmu-v3-combined-irq", smmu);
4037 dev_warn(smmu->dev, "failed to enable combined irq\n");
4039 arm_smmu_setup_unique_irqs(smmu);
4041 if (smmu->features & ARM_SMMU_FEAT_PRI)
4045 ret = arm_smmu_write_reg_sync(smmu, irqen_flags,
4048 dev_warn(smmu->dev, "failed to enable irqs\n");
4053 static int arm_smmu_device_disable(struct arm_smmu_device *smmu)
4057 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_CR0, ARM_SMMU_CR0ACK);
4059 dev_err(smmu->dev, "failed to clear cr0\n");
4064 static void arm_smmu_write_strtab(struct arm_smmu_device *smmu)
4066 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
4070 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
4080 FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits);
4084 smmu->base + ARM_SMMU_STRTAB_BASE);
4085 writel_relaxed(reg, smmu->base + ARM_SMMU_STRTAB_BASE_CFG);
4088 static int arm_smmu_device_reset(struct arm_smmu_device *smmu)
4095 reg = readl_relaxed(smmu->base + ARM_SMMU_CR0);
4097 dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n");
4098 arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0);
4101 ret = arm_smmu_device_disable(smmu);
4112 writel_relaxed(reg, smmu->base + ARM_SMMU_CR1);
4117 if (smmu->features & ARM_SMMU_FEAT_E2H)
4120 writel_relaxed(reg, smmu->base + ARM_SMMU_CR2);
4123 arm_smmu_write_strtab(smmu);
4126 writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE);
4127 writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD);
4128 writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS);
4131 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
4134 dev_err(smmu->dev, "failed to enable command queue\n");
4140 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);
4143 if (smmu->features & ARM_SMMU_FEAT_HYP) {
4145 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);
4149 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);
4152 writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE);
4153 writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD);
4154 writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS);
4157 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
4160 dev_err(smmu->dev, "failed to enable event queue\n");
4165 if (smmu->features & ARM_SMMU_FEAT_PRI) {
4166 writeq_relaxed(smmu->priq.q.q_base,
4167 smmu->base + ARM_SMMU_PRIQ_BASE);
4168 writel_relaxed(smmu->priq.q.llq.prod,
4169 smmu->page1 + ARM_SMMU_PRIQ_PROD);
4170 writel_relaxed(smmu->priq.q.llq.cons,
4171 smmu->page1 + ARM_SMMU_PRIQ_CONS);
4174 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
4177 dev_err(smmu->dev, "failed to enable PRI queue\n");
4182 if (smmu->features & ARM_SMMU_FEAT_ATS) {
4184 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
4187 dev_err(smmu->dev, "failed to enable ATS check\n");
4192 ret = arm_smmu_setup_irqs(smmu);
4194 dev_err(smmu->dev, "failed to setup irqs\n");
4203 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
4206 dev_err(smmu->dev, "failed to enable SMMU interface\n");
4210 if (smmu->impl_ops && smmu->impl_ops->device_reset) {
4211 ret = smmu->impl_ops->device_reset(smmu);
4213 dev_err(smmu->dev, "failed to reset impl\n");
4225 static void arm_smmu_device_iidr_probe(struct arm_smmu_device *smmu)
4230 reg = readl_relaxed(smmu->base + ARM_SMMU_IIDR);
4242 smmu->features &= ~ARM_SMMU_FEAT_SEV;
4245 smmu->features &= ~ARM_SMMU_FEAT_NESTING;
4249 smmu->features &= ~ARM_SMMU_FEAT_BTM;
4250 smmu->options |= ARM_SMMU_OPT_CMDQ_FORCE_SYNC;
4252 smmu->features &= ~ARM_SMMU_FEAT_NESTING;
4259 static void arm_smmu_get_httu(struct arm_smmu_device *smmu, u32 reg)
4261 u32 fw_features = smmu->features & (ARM_SMMU_FEAT_HA | ARM_SMMU_FEAT_HD);
4272 if (smmu->dev->of_node)
4273 smmu->features |= hw_features;
4276 dev_warn(smmu->dev,
4281 static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
4284 bool coherent = smmu->features & ARM_SMMU_FEAT_COHERENCY;
4287 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0);
4291 smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB;
4294 smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB;
4303 smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE;
4307 smmu->features |= ARM_SMMU_FEAT_TT_BE;
4311 smmu->features |= ARM_SMMU_FEAT_TT_LE;
4315 dev_err(smmu->dev, "unknown/unsupported TT endianness!\n");
4321 smmu->features |= ARM_SMMU_FEAT_PRI;
4324 smmu->features |= ARM_SMMU_FEAT_ATS;
4327 smmu->features |= ARM_SMMU_FEAT_SEV;
4330 smmu->features |= ARM_SMMU_FEAT_MSI;
4332 smmu->options |= ARM_SMMU_OPT_MSIPOLL;
4336 smmu->features |= ARM_SMMU_FEAT_HYP;
4338 smmu->features |= ARM_SMMU_FEAT_E2H;
4341 arm_smmu_get_httu(smmu, reg);
4348 dev_warn(smmu->dev, "IDR0.COHACC overridden by FW configuration (%s)\n",
4353 smmu->features |= ARM_SMMU_FEAT_STALL_FORCE;
4356 smmu->features |= ARM_SMMU_FEAT_STALLS;
4360 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
4363 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
4366 dev_err(smmu->dev, "no translation support!\n");
4373 smmu->ias = 40;
4378 dev_err(smmu->dev, "AArch64 table format not supported!\n");
4383 smmu->asid_bits = reg & IDR0_ASID16 ? 16 : 8;
4384 smmu->vmid_bits = reg & IDR0_VMID16 ? 16 : 8;
4387 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1);
4389 dev_err(smmu->dev, "embedded implementation not supported\n");
4394 smmu->features |= ARM_SMMU_FEAT_ATTR_TYPES_OVR;
4397 smmu->cmdq.q.llq.max_n_shift = min_t(u32, CMDQ_MAX_SZ_SHIFT,
4399 if (smmu->cmdq.q.llq.max_n_shift <= ilog2(CMDQ_BATCH_ENTRIES)) {
4406 dev_err(smmu->dev, "command queue size <= %d entries not supported\n",
4411 smmu->evtq.q.llq.max_n_shift = min_t(u32, EVTQ_MAX_SZ_SHIFT,
4413 smmu->priq.q.llq.max_n_shift = min_t(u32, PRIQ_MAX_SZ_SHIFT,
4417 smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg);
4418 smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg);
4419 smmu->iommu.max_pasids = 1UL << smmu->ssid_bits;
4425 if (smmu->sid_bits <= STRTAB_SPLIT)
4426 smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB;
4429 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3);
4431 smmu->features |= ARM_SMMU_FEAT_RANGE_INV;
4434 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5);
4437 smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg);
4441 smmu->pgsize_bitmap |= SZ_64K | SZ_512M;
4443 smmu->pgsize_bitmap |= SZ_16K | SZ_32M;
4445 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
4449 smmu->features |= ARM_SMMU_FEAT_VAX;
4454 smmu->oas = 32;
4457 smmu->oas = 36;
4460 smmu->oas = 40;
4463 smmu->oas = 42;
4466 smmu->oas = 44;
4469 smmu->oas = 52;
4470 smmu->pgsize_bitmap |= 1ULL << 42; /* 4TB */
4473 dev_info(smmu->dev,
4477 smmu->oas = 48;
4481 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;
4483 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap;
4486 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas)))
4487 dev_warn(smmu->dev,
4490 smmu->ias = max(smmu->ias, smmu->oas);
4492 if ((smmu->features & ARM_SMMU_FEAT_TRANS_S1) &&
4493 (smmu->features & ARM_SMMU_FEAT_TRANS_S2))
4494 smmu->features |= ARM_SMMU_FEAT_NESTING;
4496 arm_smmu_device_iidr_probe(smmu);
4498 if (arm_smmu_sva_supported(smmu))
4499 smmu->features |= ARM_SMMU_FEAT_SVA;
4501 dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n",
4502 smmu->ias, smmu->oas, smmu->features);
4509 struct arm_smmu_device *smmu)
4518 smmu->impl_dev = &adev->dev;
4519 smmu->options |= ARM_SMMU_OPT_TEGRA241_CMDQV;
4520 dev_info(smmu->dev, "found companion CMDQV device: %s\n",
4521 dev_name(smmu->impl_dev));
4527 struct arm_smmu_device *smmu)
4533 struct arm_smmu_device *smmu)
4540 smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY;
4543 smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH;
4550 acpi_smmu_dsdt_probe_tegra241_cmdqv(node, smmu);
4554 dev_notice(smmu->dev, "option mask 0x%x\n", smmu->options);
4559 struct arm_smmu_device *smmu)
4562 struct device *dev = smmu->dev;
4571 smmu->features |= ARM_SMMU_FEAT_COHERENCY;
4575 smmu->features |= ARM_SMMU_FEAT_HD;
4578 smmu->features |= ARM_SMMU_FEAT_HA;
4581 return acpi_smmu_iort_probe_model(node, smmu);
4585 struct arm_smmu_device *smmu)
4592 struct arm_smmu_device *smmu)
4605 parse_driver_options(smmu);
4608 smmu->features |= ARM_SMMU_FEAT_COHERENCY;
4613 static unsigned long arm_smmu_resource_size(struct arm_smmu_device *smmu)
4615 if (smmu->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY)
4629 static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu)
4635 iort_get_rmr_sids(dev_fwnode(smmu->dev), &rmr_list);
4643 ret = arm_smmu_init_sid_strtab(smmu, rmr->sids[i]);
4645 dev_err(smmu->dev, "RMR SID(0x%x) bypass failed\n",
4654 arm_smmu_make_bypass_ste(smmu,
4655 arm_smmu_get_step_for_sid(smmu, rmr->sids[i]));
4659 iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list);
4664 struct arm_smmu_device *smmu = data;
4666 if (smmu->impl_ops && smmu->impl_ops->device_remove)
4667 smmu->impl_ops->device_remove(smmu);
4675 static struct arm_smmu_device *arm_smmu_impl_probe(struct arm_smmu_device *smmu)
4680 if (smmu->impl_dev && (smmu->options & ARM_SMMU_OPT_TEGRA241_CMDQV))
4681 new_smmu = tegra241_cmdqv_probe(smmu);
4684 return smmu;
4700 struct arm_smmu_device *smmu;
4703 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
4704 if (!smmu)
4706 smmu->dev = dev;
4709 ret = arm_smmu_device_dt_probe(pdev, smmu);
4711 ret = arm_smmu_device_acpi_probe(pdev, smmu);
4716 smmu = arm_smmu_impl_probe(smmu);
4717 if (IS_ERR(smmu))
4718 return PTR_ERR(smmu);
4724 if (resource_size(res) < arm_smmu_resource_size(smmu)) {
4734 smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ);
4735 if (IS_ERR(smmu->base))
4736 return PTR_ERR(smmu->base);
4738 if (arm_smmu_resource_size(smmu) > SZ_64K) {
4739 smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K,
4741 if (IS_ERR(smmu->page1))
4742 return PTR_ERR(smmu->page1);
4744 smmu->page1 = smmu->base;
4751 smmu->combined_irq = irq;
4755 smmu->evtq.q.irq = irq;
4759 smmu->priq.q.irq = irq;
4763 smmu->gerr_irq = irq;
4766 ret = arm_smmu_device_hw_probe(smmu);
4771 ret = arm_smmu_init_structures(smmu);
4776 platform_set_drvdata(pdev, smmu);
4779 arm_smmu_rmr_install_bypass_ste(smmu);
4782 ret = arm_smmu_device_reset(smmu);
4787 ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL,
4792 ret = iommu_device_register(&smmu->iommu, &arm_smmu_ops, dev);
4801 iommu_device_sysfs_remove(&smmu->iommu);
4803 arm_smmu_device_disable(smmu);
4805 iopf_queue_free(smmu->evtq.iopf);
4811 struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
4813 iommu_device_unregister(&smmu->iommu);
4814 iommu_device_sysfs_remove(&smmu->iommu);
4815 arm_smmu_device_disable(smmu);
4816 iopf_queue_free(smmu->evtq.iopf);
4817 ida_destroy(&smmu->vmid_map);
4822 struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
4824 arm_smmu_device_disable(smmu);
4828 { .compatible = "arm,smmu-v3", },
4841 .name = "arm-smmu-v3",
4854 MODULE_ALIAS("platform:arm-smmu-v3");