22 #define NUM_EXPECTED_SYNCS(x) x  macro
199 		test, &bypass_ste, &abort_ste, NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_ste_test_bypass_to_abort()
210 		test, &abort_ste, &bypass_ste, NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_ste_test_abort_to_bypass()
220 						       NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_ste_test_cdtable_to_abort()
230 						       NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_ste_test_abort_to_cdtable()
240 						       NUM_EXPECTED_SYNCS(3));  in arm_smmu_v3_write_ste_test_cdtable_to_bypass()
250 						       NUM_EXPECTED_SYNCS(3));  in arm_smmu_v3_write_ste_test_bypass_to_cdtable()
268 		test, &ste, &s1dss_bypass, NUM_EXPECTED_SYNCS(1));  in arm_smmu_v3_write_ste_test_cdtable_s1dss_change()
270 		test, &s1dss_bypass, &ste, NUM_EXPECTED_SYNCS(1));  in arm_smmu_v3_write_ste_test_cdtable_s1dss_change()
281 		test, &s1dss_bypass, &bypass_ste, NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_ste_test_s1dssbypass_to_stebypass()
292 		test, &bypass_ste, &s1dss_bypass, NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_ste_test_stebypass_to_s1dssbypass()
328 						       NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_ste_test_s2_to_abort()
337 						       NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_ste_test_abort_to_s2()
346 						       NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_ste_test_s2_to_bypass()
355 						       NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_ste_test_bypass_to_s2()
367 						       NUM_EXPECTED_SYNCS(3));  in arm_smmu_v3_write_ste_test_s1_to_s2()
379 						       NUM_EXPECTED_SYNCS(3));  in arm_smmu_v3_write_ste_test_s2_to_s1()
397 		test, &ste, &ste_2, NUM_EXPECTED_SYNCS(3));  in arm_smmu_v3_write_ste_test_non_hitless()
484 		test, &cd, &cd_2, NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_cd_test_s1_clear()
486 		test, &cd_2, &cd, NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_cd_test_s1_clear()
497 						      NUM_EXPECTED_SYNCS(1));  in arm_smmu_v3_write_cd_test_s1_change_asid()
499 						      NUM_EXPECTED_SYNCS(1));  in arm_smmu_v3_write_cd_test_s1_change_asid()
530 						       NUM_EXPECTED_SYNCS(3));  in arm_smmu_v3_write_ste_test_s1_to_s2_stall()
542 						       NUM_EXPECTED_SYNCS(3));  in arm_smmu_v3_write_ste_test_s2_to_s1_stall()
552 		test, &cd, &cd_2, NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_cd_test_sva_clear()
554 		test, &cd_2, &cd, NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_cd_test_sva_clear()
565 						      NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_cd_test_sva_release()
567 						      NUM_EXPECTED_SYNCS(2));  in arm_smmu_v3_write_cd_test_sva_release()