Lines Matching refs:reg_width
812 int reg_width; member
826 .reg_width = 8,
834 .reg_width = 8,
842 .reg_width = 1,
850 .reg_width = 1,
857 .reg_width = 1,
864 .reg_width = 1,
871 .reg_width = 3,
880 .reg_width = 1,
887 .reg_width = 4,
895 .reg_width = 4,
903 .reg_width = 2,
911 .reg_width = 2,
919 .reg_width = 5,
927 .reg_width = 5,
935 .reg_width = 10,
943 .reg_width = 2,
951 .reg_width = 1,
958 .reg_width = 1,
965 .reg_width = 1,
972 .reg_width = 1,
979 .reg_width = 1,
986 .reg_width = 2,
994 .reg_width = 8,
1003 .reg_width = 5,
1012 .reg_width = 3,
1021 .reg_width = 5,
1029 .reg_width = 4,
1037 .reg_width = 5,
1045 .reg_width = 5,
1053 .reg_width = 10,
1062 .reg_width = 4,
1071 .reg_width = 4,
1080 .reg_width = 8,
1090 .reg_width = 8,
1099 .reg_width = 8,
1107 .reg_width = 4,
1115 .reg_width = 4,
1123 .reg_width = 4,
1131 .reg_width = 4,
1139 .reg_width = 4,
1147 .reg_width = 4,
1155 .reg_width = 8,
1164 .reg_width = 1,
1172 .reg_width = 3,
1181 .reg_width = 1,
1189 .reg_width = 3,
1197 .reg_width = 8,
1205 .reg_width = 8,
1214 .reg_width = 8,
1224 .reg_width = 8,
1234 .reg_width = 5,
1244 .reg_width = 5,
1254 .reg_width = 8,
1264 .reg_width = 8,
1274 .reg_width = 8,
1284 .reg_width = 8,
1293 .reg_width = 4,
1303 .reg_width = 4,
1313 .reg_width = 8,
1321 .reg_width = 8,
1329 .reg_width = 8,
1337 .reg_width = 8,
1345 .reg_width = 8,
1354 .reg_width = 8,
1363 .reg_width = 8,
1373 .reg_width = 8,
1383 .reg_width = 8,
1393 .reg_width = 16,
1402 .reg_width = 16,
1410 .reg_width = 1,
1417 .reg_width = 16,
1426 .reg_width = 16,
1434 .reg_width = 16,
1442 .reg_width = 16,
1451 .reg_width = 16,
1459 .reg_width = 16,
1468 .reg_width = 16,
1476 .reg_width = 16,
2071 int reg_width = iqs7222_props[i].reg_width; in iqs7222_parse_props() local
2092 if (reg_width == 1) { in iqs7222_parse_props()
2102 if (reg_width == 1) { in iqs7222_parse_props()
2119 val_max = GENMASK(reg_width - 1, 0) * val_pitch; in iqs7222_parse_props()
2127 setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1, in iqs7222_parse_props()